CN100565842C - 包括金属栅电极的半导体器件的制造方法 - Google Patents

包括金属栅电极的半导体器件的制造方法 Download PDF

Info

Publication number
CN100565842C
CN100565842C CNB2005800297962A CN200580029796A CN100565842C CN 100565842 C CN100565842 C CN 100565842C CN B2005800297962 A CNB2005800297962 A CN B2005800297962A CN 200580029796 A CN200580029796 A CN 200580029796A CN 100565842 C CN100565842 C CN 100565842C
Authority
CN
China
Prior art keywords
layer
dielectric layer
ground floor
dusts
sacrificial structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005800297962A
Other languages
English (en)
Other versions
CN101010798A (zh
Inventor
J·布拉斯克
J·卡瓦利罗斯
M·多齐
S·达塔
U·沙阿
B·多勒
R·乔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN101010798A publication Critical patent/CN101010798A/zh
Application granted granted Critical
Publication of CN100565842C publication Critical patent/CN100565842C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

描述了一种半导体器件的制造方法。该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成于第一层上并比第一层宽。在去除牺牲层以生成沟槽后，在沟槽中形成金属栅电极。

Description

包括金属栅电极的半导体器件的制造方法
发明领域
本发明涉及半导体器件的制造方法，尤其涉及具有金属栅电极的半导体器件。
发明背景
当制造包括金属栅电极的CMOS器件时，可利用替代金属栅工艺来由不同的金属形成栅电极。在该工艺中，去除由一对隔片夹在中间的第一多晶硅层以在隔片之间形成沟槽。用第一金属填充该沟槽。然后去除第二多晶硅层，并用不同于第一金属的第二金属来替代第二多晶硅层。
在这一替代栅工艺中，第一和第二多晶硅层(将用金属替代)是限定用于随后形成的金属栅电极的栅长度的蚀刻多晶硅层。在具体的应用中，期望形成具有45nm(或更短)栅长度的金属栅电极。然而，利用常规的光刻技术可能无法形成适合于大批量制造的具有约45nm(或更小)宽度的蚀刻多晶硅层。
尽管可能难以形成极薄的蚀刻多晶硅层，但这样做的任何成功都将引发另一个问题-这些图案化多晶硅层是否具有基本垂直的侧壁。当去除这一图案化多晶硅层后，可能难以用各种材料来均匀地涂覆所得沟槽的侧壁。此外，可能无法用金属来完全填充这一沟槽，因为空隙可能形成于沟槽的中心处。
因此，需要一种用于制造包括金属栅电极的半导体器件的改进的方法。需要一种用于生成允许45nm(或更小)的栅长度，同时具有促进金属栅电极的形成的轮廓的图案化牺牲结构的方法。
附图简述
图1A-1I表示可在实现本发明方法的一个实施例时形成的结构的横截面图。
在这些附图中所示的特征不是按比例绘制的。
详细描述
描述了半导体器器件的制造方法。该方法包括在衬底上形成介电层，然后在介电层上形成包括第一层和第二层的牺牲结构，使得第二层比第一层宽。在去除牺牲结构以生成沟槽之后，在沟槽内形成金属栅电极。
在以下描述中，陈述了众多细节以提供对本发明的全面理解。然而，本领域的技术人员可以明白，本发明可通过除这里明确描述的方式之外的多种方式来实施。因此，本发明不限于以下公开的具体细节。
图1A-1I示出可在实现本发明方法的一个实施例时形成的结构的横截面图。最初，在衬底100上形成第一介电层101，在第一介电层101上形成第一层102，并在第一层102上形成第二层103。衬底100可包括可用作在将其上构造半导体器件的基础的任何材料。第一介电层101可包括二氧化硅、氮化二氧化硅、高介电常数(k)介电层、或可保护衬底100的其它材料。
在该实施例中，第一层102可包括可利用适当的湿法蚀刻工艺去除的材料。例如，第一层102可包括硅、含硅的合金、锗、或含锗的合金。第一层102的厚度较佳地在约100埃至约500埃之间。类似于第一层102，第二层103可包括例如硅、含硅的合金、锗、或含锗的合金。第二层103的厚度较佳地在约400埃至约800埃之间。第一介电层101、第一层102和第二层103可利用本领域的技术人员所清楚的常规处理步骤来形成。
在该实施例中，第一层102必须包括可选择性地去除的材料。例如，如果第一层102包括锗，则第二层103应包括硅或可在受到适当的蚀刻化学处理时以比去除第一层102的速率慢的速率去除的另一种材料。类似地，如果第一层102包括硅，则第二层103应包括锗或可以用比去除第一层102的速率慢的速率去除的另一种材料。虽然这里指出了可由其形成第一层102和第二层103的材料的几个例子，但可改为使用允许对于第二层103选择地去除第一层102的很多其它材料而不背离本发明的精神和范围。
随后，可利用常规的平板印刷和干法蚀刻工艺来形成第一层102和第二层103的图案。在一个较佳实施例中，在该工艺的这一阶段，第一层102和第二层103的宽度应均小于约1000埃，且较佳地在约400埃至约600埃之间。
在那之后，通过将第一层102和第二层103暴露于去除第一层102比去除第二层多得多的水溶液中来形成牺牲结构104和114。结果，第二层103比第一层102宽。如果第一层102包括锗而第二层103包括硅，则可通过将层102和103暴露于含有过氧化氢的水溶液中来形成牺牲结构104和114。在一个较佳实施例中，这一水溶液包括约2％至约5％体积的过氧化氢。这一水溶液还包括约1％至约10％体积的氢氧化铵。
如果第一层102包括硅而第二层103包括锗，则可通过将层102和103暴露于包括氢氧化物源(例如，氢氧化铵或氢氧化四甲基铵(″TMAH″))的水溶液中来形成牺牲结构104和114。在一个较佳实施例中，这一水溶液包括约2％至约5％体积的氢氧化铵或TMAH。去除第一层102的部分直到第一层102的宽度比第二层103的宽度小至少约100埃。在一个特别优选的实施例中，第一层102在去除该层的部分后具有小于约300埃的宽度。在形成牺牲结构104和114后，可通过常规的蚀刻工艺去除第一介电层101的未覆盖部分，以生成图1A的结构。
如以下所示，应用本发明的方法来形成包括比下面的第一牺牲层宽的第二牺牲层的牺牲结构可使本领域的技术人员能够利用替代栅工艺来形成包含金属栅电极的很小的晶体管。图1B-1I示出可在将本发明的方法结合到这一工艺时形成的结构。
在形成图1A的结构后，可将第二介电层105沉积在器件上。第二介电层105可包括例如二氧化硅或低k材料。通过该工艺的这一阶段，已形成源区和漏区。正如本领域的技术人员所清楚的，可采用常规的处理步骤、材料和设备来生成这些结构。在这一点上，可应用常规的化学机械抛光(″CMP″)操作来去除最初沉积时形成于牺牲结构104和114上的第二介电层105的任何部分。
随后，去除牺牲结构104以生成嵌于第二介电层105内的沟槽106-从而产生图1B的结构。在一个较佳实施例中，应用湿法蚀刻工艺以去除牺牲结构104。这一湿法蚀刻工艺可包括将牺牲结构104在足够的温度下暴露于适当的水溶液或溶液中足够长的时间以去除基本上全部的牺牲结构104。
例如，如果第一层102包括锗而第二层103包括硅，则可采用两部分湿法蚀刻工艺以去除牺牲结构104。为了去除上面的硅层，可将该层暴露于含有约2％至约15％体积的氢氧化铵或TMAH的水溶液中。在去除上层后，为了去除下面的锗层，可将该层暴露于含有约2％至约5％体积的过氧化氢和约1％至约10％体积的氢氧化铵的水溶液中。
相反，如果第一层102包括硅而第二层103包括锗，则牺牲结构104可利用同样的两个湿法蚀刻步骤但以颠倒的顺序来去除。为了去除上面的锗层，可将该层暴露于含有约2％至约5％体积的过氧化氢和约1％至约10％体积的氢氧化铵的水溶液中。在去除上层后，为了去除下面的硅层，可将该层暴露于含有约2％至约15％体积的氢氧化铵或TMAH的水溶液中。当去除牺牲结构104时，可能有必要保留第一介电层101以保护下面的衬底100。
如图1B所示，在去除牺牲结构104前在牺牲结构114上形成掩模115，以防止在去除牺牲结构104时取出牺牲结构114。可利用常规的工艺和掩模材料来形成掩模115。在去除牺牲结构104后，可去除掩模115。
当去除牺牲结构104以形成沟槽106时，所得的沟槽的顶部比底部宽，因为牺牲结构104的第二层103比下面的第一层102宽。可以比涂覆底部和顶部一样宽的沟槽的侧面更均匀地涂覆这一沟槽的侧面。此外，用金属地填充这一沟槽比填充底部和顶部一样宽的沟槽更容易，且在沟槽中心没有空隙形成。
在该实施例中，在去除牺牲结构104之后，去除第一介电层101的下面的部分。当第一介电层101包括二氧化硅时，它可利用对于二氧化硅有选择性的蚀刻工艺来去除以生成图1C的结构。这一蚀刻工艺可包括将层101暴露于在去离子水中包括约1％的HF的溶液中。应将层101暴露有限的时间，例如小于60秒，因为用于去除第一介电层101的蚀刻过程也可去除部分的第二介电层105。
在去除第一介电层101之后，在该实施例中，在沟槽106内的衬底100上形成高k栅介电层107，从而生成图1D的结构。可用于形成高k栅介电层107的材料中的某一些包括：氧化铪、氧化硅铪、氧化镧、氧化铝镧、氧化锆、氧化硅锆、氧化钽、氧化钛、氧化钛锶钡、氧化钛钡、氧化钛锶、氧化钇、氧化铝、氧化钽钪铅以及铌酸铅锌。特别优选的是氧化铪、氧化锆和氧化铝。虽然这里描述了可用于形成高k栅介电层107的材料的几个例子，但该层可由其它材料形成。
可利用常规的沉积方法，例如常规的化学气相沉积(“CVD”)、低压CVD或物理气相沉积(“PVD”)工艺，在衬底200上形成高k栅介电层107。较佳的是，采用常规的原子层CVD工艺。在这种工艺中，可将金属氧化物前体(例如，金属氯化物)和蒸汽以选定的流速供给CVD反应器，该CVD反应器然后在选定的温度和压力下工作以生成衬底100和高k栅介电层170之间的原子级光滑界面。CVD反应器应工作足够长的时间以形成具有期望厚度的层。在大部分应用中，高k栅介电层107的厚度应小于约60埃，更佳地介于约5埃至40埃之间。
如图1D所示，当使用原子层CVD工艺来形成高k栅介电层107时，该层除形成于沟槽的底部外还形成于沟槽106的侧面。(图1D表示其中去除了最初沉积时形成于第二介电层105上的高k栅介电层107的结构。)如果高k栅介电层107包括氧化物，则它可显示出任意表面位置处的氧空穴和不可接受的杂质级别，这取决于用于形成它的工艺。期望在沉积层107之后从层107中去除杂质，并使其氧化以生成具有接近理想的金属：氧化学计量的层。
为了从该层中去除杂质并增加该层的氧含量，可将湿法化学处理应用于高k栅电介质层107。这种湿法化学处理可包括将高k栅介电层107在足够的温度下暴露于含有过氧化氢的溶液中足够长的时间以从高k栅介电层107中去除杂质并增加高k栅介电层107的氧含量。暴露高k栅介电层107的适当时间和温度可取决于对于高k栅介电层107的期望的厚度和其它特性。
当将高k介电层107曝露于基于过氧化氢的溶液中时，可采用含有约2％至约30％体积的过氧化氢的水溶液。该暴露步骤应在约15℃至约40℃之间进行至少一分钟。在一个特别优选的实施例中，高k栅介电层107在约25℃的温度下暴露于含有约6.7％体积的H202的水溶液中约10分钟。在该暴露步骤期间，期望以约10KHz至约2000KHz之间频率施加声能，同时以约1至10瓦/cm2之间耗散。在一个较佳实施例中，可以用约100KHz频率施加声能，同时以约5瓦/cm2来耗散。
在某些实施例中，可能期望在这一湿法化学处理期间掩盖牺牲结构114(例如，通过保留掩模115)来确保该处理步骤不会显著地蚀刻牺牲结构114。如果在将这一湿法化学处理应用于高k栅介电层107的同时掩盖牺牲结构114，则可在该处理步骤后去除该掩模。
虽然在图1D中未示出，但期望在高k栅介电层107上形成不大于约5层单分子层厚度的覆盖层。这一覆盖层可通过将1层至5层的硅或其它材料的单分子层溅射到高k栅介电层107的表面上来形成。然后例如利用等离子体增强的化学气相沉积工艺或含有氧化剂的溶液将该覆盖层氧化，以形成覆盖的电介质氧化物。
尽管在某些实施例中期望在栅介电层107上形成覆盖层，但在所示的实施例中，n-型金属层108直接形成于层107上以填充沟槽106并生成图1E的结构。n-型金属层108可包括可用其获得金属NMOS栅电极的任何n-型导电材料。可用于形成n-型金属层108的材料包括：铪、锆、钛、钽、铝及其合金，例如包括这些元素的金属碳化物，即，碳化铪、碳化锆、碳化钛、碳化钽和碳化铝。n-型金属层108或者可包括铝化物，例如，包括铪、锆、钛、钽或钨的铝化物。
可利用公知的PVD或CVD工艺，例如，常规的溅射或原子层CVD工艺，在高k栅介电层107上形成n-型金属层108。如图1F所示，去除除其填充沟槽106的部分外的n-金属层108。可通过适当的CMP操作从器件的其它部分去除层108。当从第二介电层105的表面去除层108时，第二介电层105可用作抛光停止。
n-型金属层108可用作具有约3.9eV至约4.3eV的功函的金属NMOS栅电极。虽然图1E和1F表示其中n-型金属层108填充所有的沟槽106的结构，但在替换实施例中，n-型金属层108可以仅填充部分沟槽106，而其余的沟槽用例如钨、铝、钛或氮化钛等易于抛光的材料来填充。
在所示的实施例中，在沟槽106内形成n-型金属层108之后，去除牺牲结构114以生成嵌于第二介电层105内的沟槽109-从而产生图1G的结构。在一个较佳实施例中，可采用用于去除牺牲结构104的同一湿法蚀刻工艺来去除牺牲结构114。在某些实施例中，用于形成牺牲结构114和n-型金属层108的材料以及用于去除牺牲结构114的工艺可使牺牲结构114相对于n-型金属层108选择性地去除。然而，如果牺牲结构114不能相对于n-型金属层108选择性地去除，则期望在去除牺牲结构114之前掩盖n-型金属层108。
在去除牺牲结构114之后，利用类似于以上指出的处理步骤来去除第一介电层下面的部分并用高k栅介电层110来替代。可任选地，如上所述，在用p-型金属填充沟槽109之前可在高k栅介电层110上形成覆盖层(可在其沉积后被氧化)。然而，在该实施例中，在用高k栅介电层110替代第一介电层101之后，在高k栅介电层110上直接形成p-型金属层111以填充沟槽109并生成图1H的结构。
p-型金属层111可包括可用其获得金属PMOS栅电极的任何p-型导电材料。可用于形成p-型金属层111的材料包括：钌、钯、铂、钴、镍和导电金属氧化物，例如氧化钌。p-型金属层111可利用例如常规的溅射或原子层CVD工艺等公知的PVD或CVD工艺形成于栅介电层110上。如图1I所示，去除除其填充沟槽109的部分之外的p-金属层111。层111可经由适当的CMP操作来从器件的其它部分去除，同时第二介电层105用作抛光停止。p-型金属层111可用作具有约4.9eV至约5.2eV的功函的金属PMOS栅电极。
虽然图1H和1I表示其中p-型金属层111填充所有沟槽109的结构，但在替换实施例中，p-型金属层111可以仅填充部分沟槽109。如同金属NMOS栅电极一样，可用例如，钨、铝、钛或氮化钛等易于抛光的材料来填充其余的沟槽。虽然这里指出了用于形成层108和111的材料的几个示例，但正如本领域的技术人员所清楚的，这些金属层可由许多其它的材料形成。虽然该实施例示出在形成金属PMOS栅电极之前形成金属NMOS栅电极，但替换实施例可在形成金属NMOS栅电极之前形成金属PMOS栅电极。
在所示的实施例中，在去除牺牲结构104和114之后用高k栅介电层替代第一栅介电层101。在替换实施例中，第一介电层101可包括在去除牺牲结构104和114之后被保留的高k栅介电层。在该替换实施例中，金属层108和111直接形成于第一介电层101上，而不用高k栅介电层替代第一介电层101。
在所示的实施例中，掩模115可防止在去除牺牲结构104时去除牺牲结构114。在替换实施例中，不在牺牲结构114上形成掩模115。相反，例如，通过应用适当的湿法蚀刻工艺同时去除牺牲结构104和牺牲结构114两者。在同时去除牺牲结构104和114之后，以各种方式形成NMOS和PMOS金属栅电极。
在同时去除牺牲结构104和114之后可形成NMOS和PMOS金属栅电极的一种方式以仅在沟槽106或沟槽109中形成第一金属层开始。第一金属层可通过将金属沉积在两个沟槽中、掩盖形成于沟槽中的一个处的金属层、从另一个沟槽去除暴露的金属、然后去除掩模来形成于仅一个沟槽中。在仅在一个沟槽中形成第一金属层之后，可将第二金属层沉积在两个沟槽中，从而覆盖沟槽之一中的第一金属层并覆盖另一个沟槽中高k栅介电层。在该替换实施例中，第一金属层可设置用于器件之一(即，NMOS或PMOS)的功函，而第二金属层可设置用于另一个器件的功函。
在同时去除牺牲结构104和114之后形成NMOS和PMOS金属栅电极的另一种方式同样以在两个沟槽中沉积单一金属层开始。并非掩盖并去除部分该金属层，而是将部分(或几部分)金属层进行改性处理以设置用于NMOS和PMOS两种器件的理想功函。虽然所示的实施例提供了如何将本发明的方法用于替代金属栅工艺的示例，但本领域的技术人员将意识到该方法可以用很多种方式结合到这一工艺中。
在去除除其填充沟槽109的部分以外的金属层111后，利用任何常规的沉积工艺将覆盖介电层(未示出)沉积在第二介电层105、金属NMOS栅电极108和金属PMOS栅电极111上。在沉积这一覆盖的介电层之后用于完成该器件的处理步骤，例如形成器件的触点、金属互连和钝化层等是本领域的技术人员所公知的，所以本文不再描述。
上述方法允许形成具有其栅长度比常规的光刻技术所促进的栅长度更短的金属栅电极的晶体管。此外，上述方法可允许形成其侧面可用选择的材料均匀地涂覆并可用金属完全地填充而不在其中心形成空穴的窄沟槽。虽然上述实施例提供用于形成包括这种沟槽的器件的工艺的示例，但本发明不限于这些特定的实施例。
虽然以上描述指定了某些步骤和可用于本发明的材料，但本领域的技术人员将意识到可进行很多修改和替换。因此，旨在认为所有这些修改、改变、替换和增加都落入由所附权利要求书限定的本发明的精神和范围内。

Claims (20)

1.一种半导体器件的制造方法，包括：
在衬底上形成第一介电层；
在所述第一介电层上形成包括第一层和第二层的牺牲结构，所述第二层形成于所述第一层上，且所述第二层比所述第一层宽；
在所述第一介电层上形成第二介电层，其中所述第二介电层包围所述牺牲结构；
平面化所述第二介电层，以暴露牺牲层的上表面；
去除所述牺牲结构以生成沟槽，所述沟槽具有位于所述第二介电层内的侧面和底部；
在所述沟槽的侧面和底部上形成共形的高k栅介电层；然后
在所述沟槽中的高k栅介电层上形成锥形的金属栅电极，对应于被去除的牺牲结构的第二层的所述锥形的金属栅电极的上方部分比对应于被去除的牺牲结构的第一层的所述锥形的金属栅电极的下方部分要宽。
2.如权利要求1所述的方法，其特征在于，还包括：
在去除所述牺牲结构后去除所述第一介电层的一部分。
3.如权利要求1所述的方法，其特征在于，所述第一层包括锗而所述第二层包括硅。
4.如权利要求3所述的方法，其特征在于，所述牺牲结构是通过在含锗的层上形成含硅的层、然后将所述含硅的层和所述含锗的层曝露于包括过氧化氢的水溶液中来形成的。
5.如权利要求1所述的方法，其特征在于，所述第一层包括硅而所述第二层包括锗。
6.如权利要求5所述的方法，其特征在于，所述牺牲结构是通过在含硅的层上形成含锗的层、然后将所述含锗的层和所述含硅的层曝露于包括氢氧化物源的水溶液中来形成的。
7.如权利要求6所述的方法，其特征在于，所述氢氧化物源包括氢氧化铵或氢氧化四甲基铵。
8.如权利要求1所述的方法，其特征在于，所述第一介电层是高k栅介电层。
9.如权利要求1所述的方法，其特征在于，第一层的宽度比第二层的宽度至少要小100埃。
10.如权利要求1所述的方法，其特征在于，所述高k栅介电层的厚度小于40埃，且包括选自由氧化铪、氧化硅铪、氧化镧、氧化铝镧、氧化锆、氧化硅锆、氧化钛、氧化钽、氧化钛锶钡、氧化钛钡、氧化钛锶、氧化钇、氧化铝、氧化钽钪铅以及铌酸铅锌组成的组的材料。
11.如权利要求1所述的方法，其特征在于，所述锥形的金属栅电极包括选自由铪、锆、钛、钽、铝、金属碳化物、铝化物、钌、钯、铂、钴、镍以及导电金属氧化物组成的组的金属。
12.一种半导体器件的制造方法，包括：
在衬底上形成第一介电层；
在所述第一介电层上形成第一层；
在所述第一层上形成第二层；
使用水溶液来去除部分的第一介电层、第一层和第二层，以形成牺牲结构，其中所述水溶液去除第一层和第一介电层比去除第二层显著要多；
在所述衬底上形成第二介电层；
去除所述牺牲结构以在所述第二介电层内生成沟槽；
在所述衬底上和所述沟槽内形成共形的高k栅介电层；然后
在所述沟槽内和在所述高k栅介电层上形成锥形的金属栅电极，对应于所述第二层的所述锥形的金属栅电极的上方部分比对应于所述第一层的所述锥形的金属栅电极的下方部分要宽。
13.如权利要求12所述的方法，其特征在于，所述第一层包括锗且厚度在100埃至500埃之间，所述第二层包括硅且厚度在400埃至800埃之间。
14.如权利要求10所述的方法，其特征在于，将所述第一层和所述第二层曝露于包括2％至5％体积的过氧化氢的水溶液中。
15.如权利要求12所述的方法，其特征在于，所述第一层包括硅且厚度在100埃至500埃之间，所述第二层包括锗且厚度在400埃至800埃之间。
16.如权利要求15所述的方法，其特征在于，将所述第一层和所述第二层曝露于包括2％至15％体积的氢氧化铵或氢氧化四甲基铵的水溶液中。
17.如权利要求12所述的方法，其特征在于：
所述第一层包括锗且厚度在100埃至500埃之间；
所述第二层包括硅且厚度在400埃至800埃之间；以及
在去除部分第一层之后所述第一层具有小于300埃的宽度。
18.如权利要求17所述的方法，其特征在于，所述水溶液包括2％至5％体积的过氧化氢。
19.如权利要求12所述的方法，其特征在于：
所述第一层包括硅且厚度在100埃至500埃之间；
所述第二层包括锗且厚度在400埃至800埃之间；以及
在去除部分第一层之后所述第一牺牲层具有小于300埃的宽度。
20.如权利要求19所述的方法，其特征在于，所述水溶液包括2％至15％体积的氢氧化铵或氢氧化四甲基铵。
CNB2005800297962A 2004-09-07 2005-09-02 包括金属栅电极的半导体器件的制造方法 Expired - Fee Related CN100565842C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/936,114 US7176090B2 (en) 2004-09-07 2004-09-07 Method for making a semiconductor device that includes a metal gate electrode
US10/936,114 2004-09-07

Publications (2)

Publication Number Publication Date
CN101010798A CN101010798A (zh) 2007-08-01
CN100565842C true CN100565842C (zh) 2009-12-02

Family

ID=35583492

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005800297962A Expired - Fee Related CN100565842C (zh) 2004-09-07 2005-09-02 包括金属栅电极的半导体器件的制造方法

Country Status (5)

Country Link
US (1) US7176090B2 (zh)
KR (1) KR100880038B1 (zh)
CN (1) CN100565842C (zh)
TW (1) TWI292181B (zh)
WO (1) WO2006029061A1 (zh)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007041207B4 (de) * 2007-08-31 2015-05-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS-Bauelement mit Gateisolationsschichten mit unterschiedlicher Art und Dicke und Verfahren zur Herstellung
US7763943B2 (en) * 2007-12-26 2010-07-27 Intel Corporation Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
US8030163B2 (en) * 2007-12-26 2011-10-04 Intel Corporation Reducing external resistance of a multi-gate device using spacer processing techniques
US8264048B2 (en) * 2008-02-15 2012-09-11 Intel Corporation Multi-gate device having a T-shaped gate structure
US20090206404A1 (en) * 2008-02-15 2009-08-20 Ravi Pillarisetty Reducing external resistance of a multi-gate device by silicidation
JP4548521B2 (ja) * 2008-07-09 2010-09-22 ソニー株式会社 半導体装置の製造方法及び半導体装置
US8735235B2 (en) * 2008-08-20 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit metal gate structure and method of fabrication
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
US7915127B2 (en) * 2009-07-27 2011-03-29 United Microelectronics Corp. Manufacturing method of semiconductor device
US8076735B2 (en) * 2009-10-02 2011-12-13 United Microelectronics Corp. Semiconductor device with trench of various widths
KR101634748B1 (ko) * 2009-12-08 2016-07-11 삼성전자주식회사 트랜지스터의 제조방법 및 그를 이용한 집적 회로의 형성방법
CN102468146B (zh) * 2010-11-01 2013-12-04 中芯国际集成电路制造(上海)有限公司 金属栅极的形成方法
CN102468145A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 金属栅极的形成方法
CN102479692B (zh) * 2010-11-30 2014-06-04 中芯国际集成电路制造(北京)有限公司 形成栅极的方法
US8564063B2 (en) 2010-12-07 2013-10-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
US20120319198A1 (en) 2011-06-16 2012-12-20 Chin-Cheng Chien Semiconductor device and fabrication method thereof
US8674452B2 (en) 2011-06-24 2014-03-18 United Microelectronics Corp. Semiconductor device with lower metal layer thickness in PMOS region
US8486790B2 (en) 2011-07-18 2013-07-16 United Microelectronics Corp. Manufacturing method for metal gate
US8580625B2 (en) 2011-07-22 2013-11-12 Tsuo-Wen Lu Metal oxide semiconductor transistor and method of manufacturing the same
US20130043556A1 (en) 2011-08-17 2013-02-21 International Business Machines Corporation Size-filtered multimetal structures
US10134631B2 (en) 2011-08-17 2018-11-20 International Business Machines Corporation Size-filtered multimetal structures
US8658487B2 (en) * 2011-11-17 2014-02-25 United Microelectronics Corp. Semiconductor device and fabrication method thereof
US8860135B2 (en) 2012-02-21 2014-10-14 United Microelectronics Corp. Semiconductor structure having aluminum layer with high reflectivity
US8860181B2 (en) 2012-03-07 2014-10-14 United Microelectronics Corp. Thin film resistor structure
US8951855B2 (en) * 2012-04-24 2015-02-10 United Microelectronics Corp. Manufacturing method for semiconductor device having metal gate
KR101929185B1 (ko) 2012-05-02 2018-12-17 삼성전자 주식회사 반도체 장치의 제조 방법
US8836049B2 (en) 2012-06-13 2014-09-16 United Microelectronics Corp. Semiconductor structure and process thereof
US9054172B2 (en) 2012-12-05 2015-06-09 United Microelectrnics Corp. Semiconductor structure having contact plug and method of making the same
US8735269B1 (en) 2013-01-15 2014-05-27 United Microelectronics Corp. Method for forming semiconductor structure having TiN layer
US9054220B2 (en) 2013-02-08 2015-06-09 Freescale Semiconductor, Inc. Embedded NVM in a HKMG process
US9023708B2 (en) 2013-04-19 2015-05-05 United Microelectronics Corp. Method of forming semiconductor device
US9159798B2 (en) 2013-05-03 2015-10-13 United Microelectronics Corp. Replacement gate process and device manufactured using the same
US9196542B2 (en) 2013-05-22 2015-11-24 United Microelectronics Corp. Method for manufacturing semiconductor devices
US8921947B1 (en) 2013-06-10 2014-12-30 United Microelectronics Corp. Multi-metal gate semiconductor device having triple diameter metal opening
US9064814B2 (en) 2013-06-19 2015-06-23 United Microelectronics Corp. Semiconductor structure having metal gate and manufacturing method thereof
US20150021772A1 (en) * 2013-07-16 2015-01-22 Intermolecular Inc. Mixed-metal barrier films optimized by high-productivity combinatorial PVD
US9245972B2 (en) 2013-09-03 2016-01-26 United Microelectronics Corp. Method for manufacturing semiconductor device
US9384984B2 (en) 2013-09-03 2016-07-05 United Microelectronics Corp. Semiconductor structure and method of forming the same
US20150069534A1 (en) 2013-09-11 2015-03-12 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US9281201B2 (en) 2013-09-18 2016-03-08 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US9318490B2 (en) 2014-01-13 2016-04-19 United Microelectronics Corp. Semiconductor structure and manufacturing method thereof
US9231071B2 (en) 2014-02-24 2016-01-05 United Microelectronics Corp. Semiconductor structure and manufacturing method of the same
US10388576B2 (en) * 2016-06-30 2019-08-20 International Business Machines Corporation Semiconductor device including dual trench epitaxial dual-liner contacts
US10029908B1 (en) * 2016-12-30 2018-07-24 Texas Instruments Incorporated Dielectric cladding of microelectromechanical systems (MEMS) elements for improved reliability

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US660713A (en) * 1899-10-04 1900-10-30 Browning Mfg Company Electric motor.
KR100207472B1 (ko) * 1996-06-07 1999-07-15 윤종용 티타늄 질화막 적층 구조의 게이트 전극을 갖춘 반도체장치 및 그 제조 방법
US6063698A (en) * 1997-06-30 2000-05-16 Motorola, Inc. Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits
US6261887B1 (en) 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
US20020197790A1 (en) * 1997-12-22 2002-12-26 Kizilyalli Isik C. Method of making a compound, high-K, gate and capacitor insulator layer
KR100540477B1 (ko) * 1998-06-30 2006-03-17 주식회사 하이닉스반도체 반도체 소자의 게이트 전극 형성방법
GB2358737A (en) 1999-03-01 2001-08-01 Nec Corp Methods for manufacturing a complimentary integrated circuit
FR2791177A1 (fr) 1999-03-19 2000-09-22 France Telecom Procede de realisation d'une grille en forme de champignon ou grille en "t"
US6255698B1 (en) * 1999-04-28 2001-07-03 Advanced Micro Devices, Inc. Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
US6297109B1 (en) * 1999-08-19 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Method to form shallow junction transistors while eliminating shorts due to junction spiking
JP2001257344A (ja) * 2000-03-10 2001-09-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
US6184072B1 (en) * 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US6475841B1 (en) * 2000-06-02 2002-11-05 Motorola, Inc. Transistor with shaped gate electrode and method therefor
KR100372643B1 (ko) * 2000-06-30 2003-02-17 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 제조방법
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
US6475874B2 (en) * 2000-12-07 2002-11-05 Advanced Micro Devices, Inc. Damascene NiSi metal gate high-k transistor
US6544906B2 (en) * 2000-12-21 2003-04-08 Texas Instruments Incorporated Annealing of high-k dielectric materials
KR100387259B1 (ko) * 2000-12-29 2003-06-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6410376B1 (en) * 2001-03-02 2002-06-25 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration
US6365450B1 (en) * 2001-03-15 2002-04-02 Advanced Micro Devices, Inc. Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US20020155665A1 (en) * 2001-04-24 2002-10-24 International Business Machines Corporation, Formation of notched gate using a multi-layer stack
US6596597B2 (en) * 2001-06-12 2003-07-22 International Business Machines Corporation Method of manufacturing dual gate logic devices
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
US6420279B1 (en) * 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US6596599B1 (en) * 2001-07-16 2003-07-22 Taiwan Semiconductor Manufacturing Company Gate stack for high performance sub-micron CMOS devices
US6573193B2 (en) * 2001-08-13 2003-06-03 Taiwan Semiconductor Manufacturing Co., Ltd Ozone-enhanced oxidation for high-k dielectric semiconductor devices
US6797599B2 (en) * 2001-08-31 2004-09-28 Texas Instruments Incorporated Gate structure and method
EP1315200B1 (en) * 2001-11-26 2008-07-09 Interuniversitair Microelektronica Centrum Vzw Methods for CMOS semiconductor devices with selectable gate thicknesses
US6667246B2 (en) * 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
US6620713B2 (en) * 2002-01-02 2003-09-16 Intel Corporation Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication
US6696345B2 (en) * 2002-01-07 2004-02-24 Intel Corporation Metal-gate electrode for CMOS transistor applications
US6617213B2 (en) * 2002-01-25 2003-09-09 Infineon Technologies Ag Method for achieving high self-aligning vertical gate studs relative to the support isolation level
US6620664B2 (en) * 2002-02-07 2003-09-16 Sharp Laboratories Of America, Inc. Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
US6617209B1 (en) * 2002-02-22 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP2004006819A (ja) * 2002-04-26 2004-01-08 Nec Electronics Corp 半導体装置の製造方法
US6617210B1 (en) * 2002-05-31 2003-09-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
JP4537646B2 (ja) * 2002-06-14 2010-09-01 株式会社東芝 半導体装置
US7078284B2 (en) * 2002-06-20 2006-07-18 Micron Technology, Inc. Method for forming a notched gate
US6770568B2 (en) * 2002-09-12 2004-08-03 Intel Corporation Selective etching using sonication
US6746967B2 (en) * 2002-09-30 2004-06-08 Intel Corporation Etching metal using sonication
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6689675B1 (en) * 2002-10-31 2004-02-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6709911B1 (en) * 2003-01-07 2004-03-23 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6716707B1 (en) * 2003-03-11 2004-04-06 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6696327B1 (en) * 2003-03-18 2004-02-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric

Also Published As

Publication number Publication date
US7176090B2 (en) 2007-02-13
CN101010798A (zh) 2007-08-01
US20060051957A1 (en) 2006-03-09
TWI292181B (en) 2008-01-01
TW200616053A (en) 2006-05-16
WO2006029061A1 (en) 2006-03-16
KR100880038B1 (ko) 2009-01-22
KR20070088614A (ko) 2007-08-29

Similar Documents

Publication Publication Date Title
CN100565842C (zh) 包括金属栅电极的半导体器件的制造方法
CN1947242B (zh) 用于制造具有高k栅极电介质层和金属栅电极的半导体器件的方法
CN100524660C (zh) 用于制作具有高k栅介电层和金属栅电极的半导体器件的方法
CN100585832C (zh) 形成具有替代金属栅电极的集成电路
CN101027761B (zh) 使半导体结构平坦化以形成替代金属栅
US7208361B2 (en) Replacement gate process for making a semiconductor device that includes a metal gate electrode
CN100550350C (zh) 具有金属和硅化物栅电极的cmos器件及其制作方法
CN102867850A (zh) 具有高k栅电介质和金属栅电极的半导体器件
CN101099241B (zh) 具有高k栅电介质和金属栅电极的半导体器件的制造方法
US7126199B2 (en) Multilayer metal gate electrode
TWI242262B (en) Integrating n-type and p-type metal gate transistors
CN100413087C (zh) 制造具有高介电常数栅极电介质的半导体器件的方法
TWI297926B (en) Forming dual metal complementary metal oxide semiconductor integrated circuits
US20070141798A1 (en) Silicide layers in contacts for high-k/metal gate transistors
US20050272270A1 (en) Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction
CN1873922B (zh) 一种具有高k栅介质层和硅化物栅电极的半导体器件的制造方法
TW200531159A (en) A method for making a semiconductor device that includes a metal gate electrode
CN1591786B (zh) 制造有高介电常数栅极电介质半导体器件的选择刻蚀工艺
WO2005112110A1 (en) A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
KR20070050494A (ko) 반도체 디바이스 및 그 제조 방법
JP5669752B2 (ja) チャネル半導体合金を備えたトランジスタにおける堆積不均一性の低減によるスレッショルド電圧ばらつきの低減
TW200525705A (en) Low power flash memory cell and method
US20050266694A1 (en) Controlling bubble formation during etching
JP4589765B2 (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091202

Termination date: 20190902

CF01 Termination of patent right due to non-payment of annual fee