CN100413087C - 制造具有高介电常数栅极电介质的半导体器件的方法 - Google Patents

制造具有高介电常数栅极电介质的半导体器件的方法 Download PDF

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CN100413087C
CN100413087C CNB2003801005816A CN200380100581A CN100413087C CN 100413087 C CN100413087 C CN 100413087C CN B2003801005816 A CNB2003801005816 A CN B2003801005816A CN 200380100581 A CN200380100581 A CN 200380100581A CN 100413087 C CN100413087 C CN 100413087C
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贾斯廷·布拉斯克
马克·多齐
约翰·巴纳科
罗伯特·周
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Abstract

本发明描述了一种用于制造半导体器件的方法。该方法包括在衬底(100)上形成高k栅极电介质层(110)，然后在高k栅极电介质层上形成覆盖层(115)。在氧化覆盖层以在高k栅极电介质层上形成覆盖电介质氧化物(125)之后，在覆盖电介质氧化物上形成栅电极(120)。

Description

制造具有高介电常数栅极电介质的半导体器件的方法
技术领域
本发明涉及用于制造半导体器件的方法，具体地说，涉及用于制造包括高介电常数(k)栅极电介质层的半导体器件的方法。
背景技术
具有非常薄的基于二氧化硅的栅极电介质的MOS场效应晶体管可能遇到不可接受的栅极漏电流。由某种高k电介质材料而不是二氧化硅形成栅极电介质可以减小栅极漏电流。然而，这样的电介质可能与作为用于制造器件栅电极的优选材料的多晶硅不相容。
如果这样的高k膜包含氧化物，则其可能在随机的表面位置出现氧空位。当器件的栅电极包含多晶硅时，硅化物可能形成在发生这样的空位的地方。硅化物的出现可以改变电极的功函数或者导致器件穿过电介质而短路。
因此，需要一种用于制造包括高k栅极电介质的半导体器件的改进工艺。需要这样的工艺，即当在高k膜上形成多晶硅栅电极时，该工艺消除(或者至少最小化)了硅化物的形成。本发明的方法提供了这种工艺。
附图说明
图1A到图1D表示当实施本发明方法的实施例时可以形成的结构的横截面。
在这些图中所示出的特征没有按比例画出。
具体实施方式
描述了一种用于制造半导体器件的方法。该方法包括在衬底上形成高k栅极电介质层，然后在高k栅极电介质层上形成覆盖层。在氧化覆盖层以在高k栅极电介质层上形成覆盖电介质氧化物之后，栅电极被形成在覆盖电介质氧化物上。在下面的描述中，阐述了大量细节以提供对本发明的充分理解。但是，对于本领域的技术人员来说很明显，除了这里清楚描述的那些方式外，还可以以很多方式来实施本发明。因此，本发明不限于下面描述的具体细节。
在本发明的方法的一个实施例中，如图1A所示，高k栅极电介质层110被形成在衬底100上。衬底100可以包括体硅或绝缘体上硅结构。或者，衬底100可以包括其他材料——其可以与硅组合也可以不与硅组合——例如：锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或者锑化镓。虽然这里描述了可以形成衬底100的材料的几个示例，但是可以作为基础而在其上制造半导体器件的任何材料都落在本发明的精神和范围内。
当衬底100包括硅晶片时，晶片可以在将高k栅极电介质层110形成于其表面上之前被清洗。为了清洗晶片，首先可以将其暴露于稀氢氟酸(“HF”)溶液，例如水比HF为50∶1的溶液。然后可以将晶片置于兆频超声波(megasonic)箱中，并首先暴露于水/H2O2/NH4OH溶液，然后暴露于水/H2O2/HCl溶液。水/H2O2/NH4OH溶液可以去除微粒和有机污染物，而水/H2O2/HCl溶液可以去除金属污染物。
在该清洗处理之后，高k栅极电介质层110可以被形成在衬底100上，产生图1A的结构。高k栅极电介质层110包括其介电常数比二氧化硅的介电常数高的材料。电介质层110优选具有至少是二氧化硅的介电常数两倍的介电常数，即大于约8的介电常数。可以用于制造高k栅极电介质的材料包括：氧化铪、氧化硅铪、氧化镧、氧化锆、氧化硅锆、氧化钛、氧化钽、氧化钛锶钡、氧化钛钡、氧化钛锶、氧化钇、氧化铝，氧化钽钪铅以及铌酸铅锌。尤其优选的是氧化铪、氧化锆、氧化钛和氧化铝。虽然这里描述了可以用于形成高k栅极电介质层110的材料的一些例子，但是该层也可以由其他用于减小栅极漏泄漏的材料制成。
可以使用诸如传统化学气相沉积(“CVD”)、低压CVD或物理气相沉积(“PVD”)工艺之类的传统沉积方法在衬底100上形成高k栅极电介质层110。优选地，使用传统的原子层CVD工艺。在这种工艺中，可以以选定的流速向CVD反应器中供给金属氧化物前驱体(例如金属氯化物)和蒸气，然后该反应器在选定的温度和压力下工作，以在衬底100和高k栅极电介质层110之间生成原子级的平滑界面。CVD反应器应该工作足够长的时间，以形成具有期望厚度的层。在大部分应用中，电介质层110的厚度应该小于约60埃，并且更优选在约5埃到约40埃之间。
由于存在可以形成硅化物的氧空位，这样沉积的高k栅极电介质层110可能与多晶硅不相容。在本发明的方法中，覆盖电介质氧化物被形成在高k栅极电介质层110上，以使得该层与多晶硅相容，或者与可以被用来形成栅电极的其他材料相容。
可以通过在层110上形成覆盖层，然后氧化该覆盖层来在高k栅极电介质层110上形成覆盖电介质氧化物。图1B反映了一种结构的横截面，其中覆盖层115已经被形成在高k栅极电介质层110上。在优选实施例中，覆盖层115包括硅，但是也可以改为使用例如铝的其他材料。覆盖层115的厚度优选地小于约5个单原子层的厚度，更优选由仅仅一个或者两个单原子层构成。可以利用传统的物理气相沉积工艺(例如，通过将硅或者另一种材料的1到5单原子层溅射到高k栅极电介质层110的表面上)形成覆盖层115。
当高k栅极电介质层110包括金属氧化物时，可能存在氧空位——即羟基封端已经被耗尽的表面位置。通过将一薄层的硅溅射到层110的表面上来在层110上形成覆盖层115，这样可以利用硅使这样的表面位置饱和，这可能导致在所有(至少大部分的)这些表面位置上形成硅化物。例如，如果层110包含氧化铪，则在该氧化物上形成一薄层的硅，这样将导致在氧化铪膜中出现氧空位的地方形成铪-硅键。
在高k栅极电介质层110上形成覆盖层115之后，覆盖层115被氧化以在高k栅极电介质层110上形成覆盖电介质氧化物125。当在覆盖电介质氧化物125上形成多晶硅层时，覆盖电介质氧化物125将充当防止硅化物形成的超薄覆盖氧化物层。当覆盖层115包括硅时，覆盖电介质氧化物125可以包括二氧化硅的超薄层。
可以利用等离子体增强化学气相沉积工艺或者通过将覆盖层暴露于包含氧化剂的溶液，来氧化覆盖层115。当使用等离子体增强化学气相沉积工艺来氧化覆盖层115时，可以使用直接等离子体增强化学气相沉积(“PECVD”)工艺或者远程等离子体增强化学气相沉积(“RPECVD”)工艺。在这样的PECVD或者RPECVD工艺中，通过将覆盖层115暴露于由等离子体源产生的离子化的氧物质，可以氧化覆盖层115。当使用PECVD工艺时，可以例如通过将氧、含氮氧化物或者氧与含氮氧化物的混合物输入到反应器中，然后在反应器中激发等离子体，来产生这样的离子化氧物质。当使用RPECVD工艺时，可以远程激发等离子体，然后可以将得到的离子化氧物质输入到反应器中。或者，可以通过远程激发等离子体、利用诸如氩或氦之类的载气将所得到的离子化组分输入到反应器，然后将氧、含氮氧化物或者氧与含氮氧化物的混合物输入到反应器——等离子体源的下游，这样来产生离子化氧物质。
反应器应该在合适的条件(例如压力、射频以及功率)下工作足够长的时间，来至少氧化覆盖层115的已经键合到高k栅极电介质层110的多个部分上的那些部分。例如，当覆盖层115包括硅时，则氧化步骤应该氧化所有的硅化物。该氧化步骤也可以氧化覆盖层115的没有键合到层110中存在的金属原子上的任何部分。在已经形成硅化物的每一个表面位置上，这样的氧化步骤可以在(形成硅化物的)硅原子和来自高k膜的硅原子已经键合到其上的金属原子之间桥连氧原子。
在优选实施例中，该氧化步骤发生在相对低的温度，例如低于约500℃的温度。通过在相对低的温度下氧化覆盖层115，高k栅极电介质可以保持其非晶态，并且可以减小扩散到衬底100与层110之间的界面中的氧的量。而这又可以限制在该界面处额外的氧化物的生长量。
作为利用等离子体增强化学气相沉积工艺氧化覆盖层115的另一种选择，可以通过将该层暴露于包含氧化剂的溶液来氧化覆盖层115。在优选实施例中，氧化剂包含过氧化氢。当覆盖层115被暴露于基于过氧化氢的溶液时，可以使用含体积百分比约2％到约30％之间的过氧化氢的水溶液。该暴露步骤应该在约15℃到约40℃之间进行至少约1分钟。在特别优选的实施例中，覆盖层115在约25℃的温度下被暴露于含体积百分比约6.7％的H2O2的水溶液约10分钟。
当通过将覆盖层115暴露于包含过氧化氢的溶液来氧化覆盖层115时，可能理想的是同时施加频率在约10KHz到约2,000KHz之间而功耗在约1到约10W/cm2之间的声能。在优选实施例中，可以施加频率在约1,000KHz而功耗在约5W/cm2的声能。
在氧化覆盖层115以形成覆盖电介质氧化物125后，栅电极被形成在氧化物125上。在优选实施例中，可以通过首先在覆盖电介质氧化物125上沉积多晶硅层120——产生图1C的结构，来形成栅电极。多晶硅层120可以利用传统的方法来沉积，并且厚度优选在约500埃到约4,000埃之间。在利用传统的技术刻蚀层120、125和110以形成图1D的结构之后，可以进行通常被用于完成栅电极的另外的步骤(例如，在已刻蚀的多晶硅结构130的上部上形成硅化物(没有示出))。因为这样的步骤对于本领域技术人员是公知的，所以在此不对其进行更加详细的描述。
在高k栅极电介质层110上形成覆盖层115之前，可能理想的是对层110进行湿法化学处理，以从该层去除杂质并增大该层的氧含量。这样的湿法化学处理可以包括将高k栅极电介质层110暴露于包含氢氧化物源的溶液。该溶液优选地具有至少约7的pH值，更优选地具有约11到约13之间的pH值。氢氧化物源可以包括例如去离子水、过氧化氢、氢氧化铵和/或氢氧化四烷基铵，例如氢氧化四甲基铵(“TMAH”)。
当高k栅极电介质层110被暴露于主要由去离子水组成的溶液时，高k栅极电介质层110应该在至少约35℃的温度下暴露于这样的溶液至少约1分钟。在特别优选的实施例中，高k栅极电介质层110可以在至少约40℃的温度下暴露于这样的溶液约20分钟。
当高k栅极电介质层110被暴露于基于过氧化氢的溶液时，可以使用含体积百分比约2％到约30％之间的过氧化氢的水溶液。该暴露步骤应该在约15℃到约40℃之间进行至少约1分钟。在特别优选的实施例中，高k栅极电介质层110在约25℃的温度下被暴露于含体积百分比约6.7％的H2O2的水溶液约10分钟。
当高k栅极电介质层110被暴露于基于氢氧化铵的溶液时，可以使用含体积百分比约2％到约30％之间的氢氧化铵的水溶液。该暴露步骤应该在约15℃到约90℃之间进行至少约1分钟。在特别优选的实施例中，高k栅极电介质层110在约25℃的温度下被暴露于含体积百分比约15％的NH4OH的水溶液约30分钟。
当高k栅极电介质层110被暴露于基于过氧化氢/氢氧化铵的溶液时，可以使用含体积百分比约1％到约10％之间的过氧化氢以及体积百分比约1％到约10％之间的氢氧化铵的水溶液。该暴露步骤应该在约15℃到约40℃之间进行至少约1分钟。在特别优选的实施例中，高k栅极电介质层110在约25℃的温度下被暴露于含体积百分比约4.2％的H2O2以及体积百分比约4.2％的NH4OH的水溶液约10分钟。
当高k栅极电介质层110被暴露于基于TMAH的溶液时，可以使用含体积百分比约2％到约30％之间的TMAH的水溶液。该暴露步骤应该在约15℃到约90℃之间进行至少约1分钟。在特别优选的实施例中，高k栅极电介质层110在约80℃的温度下被暴露于含体积百分比约25％的TMAH的水溶液约2分钟。
当高k栅极电介质层110暴露于包含氢氧化物源的溶液时，可能理想的是施加频率在约10KHz到约2,000KHz之间而功耗在约1到约10
W/cm2之间的声能。在优选实施例中，可以施加频率在约1,000KHz而功耗在约5W/cm2之间的声能。
虽然在此描述了可以用于从高k栅极电介质层110去除杂质并增大该层的氧含量的湿法化学处理的一些示例，但是可以改为使用用于以那样的方式改性高k栅极电介质层110的其他处理，这对于本领域的技术人员来说将是明显的。示例包括将高k栅极电介质层110暴露于含臭氧的水溶液，或者暴露于含其他类型的氧化剂和/或水解剂的其他溶液。当在形成覆盖层115之前对高k栅极电介质层110进行湿法化学处理时，可能理想的是使用与用于处理层110的工艺相同的工艺来氧化覆盖层。
本发明的方法使得高k栅极电介质能够用于基于多晶硅的栅电极。通过促使在高k栅极电介质层110的出现氧空位的表面位置上的硅化物的形成，然后在形成基于多晶硅的栅电极之前将所得到的硅化物转化成氧化物，可以提高所得到的器件的电性能。
虽然上面的描述已经指明了可以在本发明的方法中使用的某些特定步骤和材料，但是本领域的技术人员将认识到可以做出许多修改和替换。因此，所有这种修改、改变、替换和补充都应该被认为落在由所附权利要求限定的本发明的精神和范围内。

Claims (2)

1. 一种用于制造半导体器件的方法，包括：
在衬底上形成高介电常数栅极电介质层；
对所述高介电常数栅极电介质层进行湿法化学处理，以从所述层去除杂质并增大所述层的氧含量；
在所述高介电常数栅极电介质层上形成覆盖层，所述覆盖层包含硅并且厚度小于5个单原子层的厚度；
通过将所述覆盖层暴露于包含过氧化氢的溶液，氧化所述覆盖层，以在所述高介电常数栅极电介质层上形成覆盖电介质氧化物；然后
在所述覆盖电介质氧化物上形成包含多晶硅的栅电极。
2. 一种用于制造半导体器件的方法，包括：
在衬底上形成高介电常数栅极电介质层，所述高介电常数栅极电介质层的厚度小于60埃，并包括从由氧化铪、氧化锆、氧化钛和氧化铝所组成的组中选择的材料；
对所述高介电常数栅极电介质层进行湿法化学处理，以从所述层去除杂质并增大所述层的氧含量；
在所述高介电常数栅极电介质层上形成含硅层，所述含硅层的厚度小于5个单原子层的厚度；
氧化所述含硅层，以在所述高介电常数栅极电介质层上形成二氧化硅层；
在所述二氧化硅层上形成包含多晶硅的层；以及
刻蚀所述含多晶硅的层、所述二氧化硅层和所述高介电常数栅极电介质层。
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Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132336B1 (en) 2002-02-12 2006-11-07 Lsi Logic Corporation Method and apparatus for forming a memory structure having an electron affinity region
US6989565B1 (en) * 2002-04-15 2006-01-24 Lsi Logic Corporation Memory device having an electron trapping layer in a high-K dielectric gate stack
DE10218799A1 (de) * 2002-04-23 2003-11-13 Ihp Gmbh Halbleiterkondensator mit Praseodymoxid als Dielektrikum
US7056780B2 (en) * 2003-07-18 2006-06-06 Intel Corporation Etching metal silicides and germanides
US7037845B2 (en) * 2003-08-28 2006-05-02 Intel Corporation Selective etch process for making a semiconductor device having a high-k gate dielectric
KR100618815B1 (ko) * 2003-11-12 2006-08-31 삼성전자주식회사 이종의 게이트 절연막을 가지는 반도체 소자 및 그 제조방법
TWI258811B (en) * 2003-11-12 2006-07-21 Samsung Electronics Co Ltd Semiconductor devices having different gate dielectrics and methods for manufacturing the same
US20070023842A1 (en) * 2003-11-12 2007-02-01 Hyung-Suk Jung Semiconductor devices having different gate dielectric layers and methods of manufacturing the same
US7153734B2 (en) 2003-12-29 2006-12-26 Intel Corporation CMOS device with metal and silicide gate electrodes and a method for making it
CN1312738C (zh) * 2004-02-16 2007-04-25 南京大学 制备稳定的稀土氧化物栅介电薄膜的方法
US6893927B1 (en) 2004-03-22 2005-05-17 Intel Corporation Method for making a semiconductor device with a metal gate electrode
US7208361B2 (en) * 2004-03-24 2007-04-24 Intel Corporation Replacement gate process for making a semiconductor device that includes a metal gate electrode
US7153784B2 (en) * 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US20050250258A1 (en) * 2004-05-04 2005-11-10 Metz Matthew V Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7045428B2 (en) * 2004-05-26 2006-05-16 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and a conductor that facilitates current flow across a P/N junction
US20050272191A1 (en) * 2004-06-03 2005-12-08 Uday Shah Replacement gate process for making a semiconductor device that includes a metal gate electrode
US6887800B1 (en) 2004-06-04 2005-05-03 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction
US7323423B2 (en) * 2004-06-30 2008-01-29 Intel Corporation Forming high-k dielectric layers on smooth substrates
US7157378B2 (en) * 2004-07-06 2007-01-02 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7148548B2 (en) * 2004-07-20 2006-12-12 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
KR100597642B1 (ko) * 2004-07-30 2006-07-05 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조방법
US7074680B2 (en) 2004-09-07 2006-07-11 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7176090B2 (en) * 2004-09-07 2007-02-13 Intel Corporation Method for making a semiconductor device that includes a metal gate electrode
US7390709B2 (en) 2004-09-08 2008-06-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7507629B2 (en) * 2004-09-10 2009-03-24 Gerald Lucovsky Semiconductor devices having an interfacial dielectric layer and related methods
US7235847B2 (en) * 2004-09-17 2007-06-26 Freescale Semiconductor, Inc. Semiconductor device having a gate with a thin conductive layer
US20060065627A1 (en) * 2004-09-29 2006-03-30 James Clarke Processing electronic devices using a combination of supercritical fluid and sonic energy
US7361608B2 (en) * 2004-09-30 2008-04-22 Tokyo Electron Limited Method and system for forming a feature in a high-k layer
US7384880B2 (en) * 2004-10-12 2008-06-10 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20060094180A1 (en) * 2004-11-02 2006-05-04 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
US20060091483A1 (en) * 2004-11-02 2006-05-04 Doczy Mark L Method for making a semiconductor device with a high-k gate dielectric layer and a silicide gate electrode
US7381608B2 (en) * 2004-12-07 2008-06-03 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
US7064066B1 (en) * 2004-12-07 2006-06-20 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode
US20060121742A1 (en) * 2004-12-07 2006-06-08 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7160779B2 (en) * 2005-02-23 2007-01-09 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US20060220090A1 (en) * 2005-03-23 2006-10-05 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
US7449756B2 (en) * 2005-06-13 2008-11-11 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
US7501336B2 (en) * 2005-06-21 2009-03-10 Intel Corporation Metal gate device with reduced oxidation of a high-k gate dielectric
JP5072209B2 (ja) * 2005-09-28 2012-11-14 株式会社東芝 半導体装置及びその製造方法
US7226831B1 (en) 2005-12-27 2007-06-05 Intel Corporation Device with scavenging spacer layer
US7994590B2 (en) * 2006-01-30 2011-08-09 Georgia Tech Research Corporation High dielectric constant insulators and associated fabrication methods
US20070262399A1 (en) * 2006-05-10 2007-11-15 Gilbert Dewey Sealing spacer to reduce or eliminate lateral oxidation of a high-k gate dielectric
US7582549B2 (en) 2006-08-25 2009-09-01 Micron Technology, Inc. Atomic layer deposited barium strontium titanium oxide films
KR20080110366A (ko) * 2007-06-15 2008-12-18 주식회사 동부하이텍 반도체 소자의 게이트 형성 방법
US8030163B2 (en) * 2007-12-26 2011-10-04 Intel Corporation Reducing external resistance of a multi-gate device using spacer processing techniques
US7763943B2 (en) * 2007-12-26 2010-07-27 Intel Corporation Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin
US20090206404A1 (en) * 2008-02-15 2009-08-20 Ravi Pillarisetty Reducing external resistance of a multi-gate device by silicidation
US8349739B2 (en) * 2008-08-29 2013-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Conformal etch material and process
US20100052076A1 (en) * 2008-09-04 2010-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating high-k poly gate device
EP2446465A4 (en) 2009-06-25 2012-07-25 Lam Res Ag PROCESS FOR TREATING A SEMICONDUCTOR WAFER
WO2010150134A2 (en) * 2009-06-25 2010-12-29 Lam Research Ag Method for treating a semiconductor wafer
KR101345390B1 (ko) * 2009-12-01 2013-12-24 도쿠리츠교세이호징 붓시쯔 자이료 겐큐키코 계면층 삭감 방법, 고유전율 게이트 절연막의 형성 방법, 고유전율 게이트 절연막, 고유전율 게이트 산화막,및 고유전율 게이트 산화막을 구비하는 트랜지스터
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
KR101686498B1 (ko) * 2011-11-24 2016-12-14 유니버시티 오브 매니토바 금속성 막의 산화
US9876083B2 (en) * 2016-01-29 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, FinFET devices and methods of forming the same
US10439071B2 (en) * 2017-04-05 2019-10-08 Shenzhen China Star Optoelectronics Technology Co., Ltd Thin film transistors and the manufacturing methods thereof, and array substrates
US11791167B2 (en) * 2020-03-31 2023-10-17 Tokyo Electron Limited Cyclic self-limiting etch process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963810A (en) * 1997-12-18 1999-10-05 Advanced Micro Devices Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof
US6027976A (en) * 1997-12-18 2000-02-22 Advanced Micro Devices, Inc. Process for making semiconductor device having nitride at silicon and polysilicon interfaces
US20020195643A1 (en) * 2001-06-21 2002-12-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same
US20020197790A1 (en) * 1997-12-22 2002-12-26 Kizilyalli Isik C. Method of making a compound, high-K, gate and capacitor insulator layer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05315608A (ja) * 1992-05-13 1993-11-26 Tadahiro Omi 半導体装置
WO1994014198A1 (en) 1992-12-11 1994-06-23 Intel Corporation A mos transistor having a composite gate electrode and method of fabrication
US5891798A (en) 1996-12-20 1999-04-06 Intel Corporation Method for forming a High dielectric constant insulator in the fabrication of an integrated circuit
US6121094A (en) * 1998-07-21 2000-09-19 Advanced Micro Devices, Inc. Method of making a semiconductor device with a multi-level gate structure
JP2000243953A (ja) * 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
US6625217B1 (en) * 1999-10-15 2003-09-23 Lucent Technologies Inc. Constrained wavelet packet for tree-structured video coders
US6541367B1 (en) * 2000-01-18 2003-04-01 Applied Materials, Inc. Very low dielectric constant plasma-enhanced CVD films
US6184072B1 (en) 2000-05-17 2001-02-06 Motorola, Inc. Process for forming a high-K gate dielectric
US6444592B1 (en) * 2000-06-20 2002-09-03 International Business Machines Corporation Interfacial oxidation process for high-k gate dielectric process integration
JP2002134739A (ja) * 2000-10-19 2002-05-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6544906B2 (en) 2000-12-21 2003-04-08 Texas Instruments Incorporated Annealing of high-k dielectric materials
US6514828B2 (en) * 2001-04-20 2003-02-04 Micron Technology, Inc. Method of fabricating a highly reliable gate oxide
US6420279B1 (en) 2001-06-28 2002-07-16 Sharp Laboratories Of America, Inc. Methods of using atomic layer deposition to deposit a high dielectric constant material on a substrate
US6573193B2 (en) 2001-08-13 2003-06-03 Taiwan Semiconductor Manufacturing Co., Ltd Ozone-enhanced oxidation for high-k dielectric semiconductor devices
US6797599B2 (en) * 2001-08-31 2004-09-28 Texas Instruments Incorporated Gate structure and method
US6815297B1 (en) * 2002-02-21 2004-11-09 Advanced Micro Devices, Inc. Ultra-thin fully depleted SOI device and method of fabrication
US6646307B1 (en) * 2002-02-21 2003-11-11 Advanced Micro Devices, Inc. MOSFET having a double gate
US6891227B2 (en) * 2002-03-20 2005-05-10 International Business Machines Corporation Self-aligned nanotube field effect transistor and method of fabricating same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963810A (en) * 1997-12-18 1999-10-05 Advanced Micro Devices Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof
US6027976A (en) * 1997-12-18 2000-02-22 Advanced Micro Devices, Inc. Process for making semiconductor device having nitride at silicon and polysilicon interfaces
US20020197790A1 (en) * 1997-12-22 2002-12-26 Kizilyalli Isik C. Method of making a compound, high-K, gate and capacitor insulator layer
US20020195643A1 (en) * 2001-06-21 2002-12-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for producing the same

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