CN100524660C - 用于制作具有高k栅介电层和金属栅电极的半导体器件的方法 - Google Patents

用于制作具有高k栅介电层和金属栅电极的半导体器件的方法 Download PDF

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CN100524660C
CN100524660C CNB2005800296654A CN200580029665A CN100524660C CN 100524660 C CN100524660 C CN 100524660C CN B2005800296654 A CNB2005800296654 A CN B2005800296654A CN 200580029665 A CN200580029665 A CN 200580029665A CN 100524660 C CN100524660 C CN 100524660C
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dielectric layer
oxide
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titanium
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CN101010788A (zh
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J·布拉斯克
C·巴恩斯
M·多茨
U·夏
J·卡瓦利罗斯
M·梅茨
S·达塔
A·米勒
R·曹
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Intel Corp
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Abstract

描述了一种制造半导体器件的方法。该方法包括在衬底上形成介电层、在介电层内形成沟槽、和在沟槽内形成高k栅介电层。在高k栅介电层上形成第一金属层之后，在该第一金属层上形成第二金属层。利用抛光步骤从该介电层上除去第二金属层的至少一部分，并且利用刻蚀步骤从该介电层上除去另外的材料。

Description

用于制作具有高k栅介电层和金属栅电极的半导体器件的方法
技术领域
本发明涉及用于制作半导体器件、尤其是包括金属栅电极的半导体器件的方法。
背景技术
具有由二氧化硅制成的非常薄的栅电介质的MOS场效应晶体管可能会经历不能接受的栅极漏电流。由特定高k介电材料替代二氧化硅形成栅电介质可以减小栅极泄漏。然而，由于这种电介质可能与多晶硅不兼容，因此期望在包括高k栅电介质的器件中使用金属栅电极。
在制作包括金属栅电极的CMOS器件时，可以使用取代栅工艺来由不同金属形成栅电极。在该工艺中，被一对隔离物托架的第一多晶硅层被除去以形成在这些隔离物之间的第一沟槽。在沟槽内沉积第一功函数金属。然后第二多晶硅层被除去以形成第二沟槽，并且被不同于第一功函数金属的第二功函数金属所取代。
当应用这种取代栅工艺时，仅将沟槽的一部分填充功函数金属然后用填充金属填充沟槽的剩余部分可能是有利的。在所得到的结构中，在其上形成了金属层的高k栅介电层可以溢出到分开这些沟槽的氧化物层上。类似地，功函数和填充金属的一部分可以形成在该氧化物层之上。在当前的工艺中，抛光操作，例如化学机械抛光(“CMP”)步骤，可以用来从氧化物层上除去高k栅介电层、功函数金属、和填充金属。
如果绶慢地抛光功函数金属，可能需要相对长的过抛光(overpolish)步骤来完全除去它们。当这种过抛光步骤对下面的高k栅介电层没有选择性时，可能在下面的氧化物层的厚度方面产生显著的批次之间或晶片之间的变化。在一些情况下，到完成抛光操作时可能在晶片的一些部分上出现了氧化物厚度的严重减小。
因此，需要一种改善的工艺来制造包括高k栅介电层和金属栅电极的半导体器件。存在对这种工艺的需要，其可以从下面的介电层(例如氧化物层)上除去填充和功函数金属而不除去该下面层的显著部分并且没有引起介电层表现出在厚度方面的显著变化。本发明的方法提供这种工艺。
发明内容
根据本发明的一个方面，提供了一种用于制造半导体器件的方法，包括：在衬底上形成介电层；在介电层内形成沟槽；在沟槽内形成高k栅介电层；在高k栅介电层上形成第一金属层；在第一金属层上形成第二金属层；利用化学机械抛光步骤从该介电层上除去第二金属层的至少一部分；以及利用等离子体干法刻蚀步骤从该介电层上除去第一金属层和高k栅介电层的至少一部分。
根据本发明的另一个方面，提供了一种用于制造半导体器件的方法，包括：在衬底上形成介电层；在介电层内形成沟槽；在沟槽内形成高k栅介电层；在高k栅介电层上形成第一金属层；在第一金属层上形成密封层；以及在金属碳化物密封层上形成第二金属层；使用化学机械抛光步骤从介电层上除去密封层的至少一部分和第二金属层；以及使用等离子体干法刻蚀步骤从介电层上除去高k栅介电层和第一金属层的至少一部分。
根据本发明的又一个方面，提供了一种用于制造半导体器件的方法，包括：在衬底上形成介电层；在介电层内形成沟槽；在沟槽内形成高k栅介电层；在高k栅介电层上形成第一金属层；在第一金属层上形成密封层；在密封层上形成第二金属层；利用化学机械抛光步骤从该介电层上除去第二金属层的至少一部分；以及利用等离子体干法刻蚀步骤从该介电层上除去高k栅介电层、第一金属层和密封层的至少一部分。
附图说明
图1a-1j表示当实施本发明的方法的实施例时可以形成的结构的截面。
图2a-2b表示当实施本发明的方法的第二实施例时可以形成的结构的截面。
并没有打算按比例绘制在这些图中示出的特征。
具体实施方式
描述用来制造半导体器件的方法。该方法包括在衬底上形成介电层、在介电层内形成沟槽、和在沟槽内形成高k栅介电层。在高k栅介电层上形成第一金属层之后，在该第一金属层上形成第二金属层。利用抛光步骤从该介电层上除去第二金属层的至少一部分，并且利用刻蚀步骤从该介电层上除去另外的材料。
在以下描述中，许多细节被陈述以提供对本发明的完整理解。然而，对本领域的技术人员来说显而易见的是，可以以除了在这里明确描述的那些之外的多种方式来实施本发明。因此本发明并不被以下所公开的特定细节所限制。
图1a-1j示出当实施本发明的方法的实施例时可以形成的结构。图1a表示在制作CMOS器件时可以形成的中间结构。该结构包括衬底100的第一部分101和第二部分102。隔离区103将第一部分101和第二部分102分开。第一多晶硅层104形成在介电层105之上，并且第二多晶硅层106形成在介电层107之上。第一多晶硅层104用侧壁隔离物108和109来托架，并且第二多晶硅层106用侧壁隔离物110和111来托架。电介质112分开层104和106。
衬底100可以包括体硅或绝缘体上硅衬底。可替换地，衬底100可以包括其它材料-其可以或可以不与硅结合-例如：锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓。尽管在此描述了可以形成衬底100的材料的几个实例，但是任何可以用作其上能够构造半导体器件的基础的材料都落入本发明的精神和范围内。
隔离区103可以包括二氧化硅、或其它可以分开晶体管的有源区的材料。介电层105和107均可以包括二氧化硅、或其它可以使衬底与其它物质绝缘的材料。第一和第二多晶硅层104和106优选均为在大约100埃和大约2,000埃之间厚，并且更优选为在大约500埃和大约1,600埃之间厚。在一个实施例中，一层可以是n型掺杂(例如利用砷、磷或另外的n型材料)，而另一层是p型掺杂(例如利用硼或另外的p型材料)。隔离物108、109、110和111优选包括氮化硅，而电介质112可以包括二氧化硅或低k材料。
可以利用常规工艺步骤、材料以及设备形成图1a的结构，其对本领域的技术人员来说是显而易见的。如所示，可以例如通过常规的CMP步骤向后抛光电介质112以暴露第一和第二多晶硅层104和106。尽管没有示出，但是图1a的结构可以包括许多其它的可以利用常规工艺形成的结构(例如，氮化硅刻蚀停止层、源区和漏区、以及一个或多个缓冲层)。
当利用常规的离子注入和退火工艺形成源区和漏区时，可以期望在多晶硅层104和106上形成硬掩模-以及在该硬掩模上形成刻蚀停止层-以在利用硅化物覆盖源区和漏区时保护层104和106。这种硬掩模可以包括氮化硅。这种刻蚀停止层可以包括硅、氧化物(例如，二氧化硅或二氧化铪)、或碳化物(例如碳化硅)。
当抛光介电层112时，可以从层104和106的表面抛光这种刻蚀停止层和氮化硅硬掩模-因为那些层将通过该工艺中的那个阶段来实现它们的作用。图1a表示这样的结构：其中可以预先形成在层104和106上的任何硬掩模或刻蚀停止层已经从那些层的表面被除去。当利用离子注入工艺形成源区和漏区时，可以在源区和漏区被注入的同时掺杂层104和106。在这种工艺中，第一多晶硅层104可以是n型掺杂，而第二多晶硅层106是p型掺杂-或反之亦然。
在形成图1a的结构之后，第一多晶硅层104被除去。在优选实施例中，通过应用湿法腐蚀工艺除去该层。这种湿法腐蚀工艺可以包括在足够的温度下将层104暴露于包括氢氧化物的源的水溶液中足够的时间以除去基本全部的该层而没有除去相当大量的第二多晶硅层106。该氢氧化物的源可以在去离子水中按体积包括在大约2％和大约30％之间的氢氧化铵或氢氧化四烃基铵，例如氢氧化四甲铵(“TMAH”)。
可以通过将它暴露于溶液中来除去n型多晶硅层，其维持在大约15℃和大约90℃之间(并且优选在大约40℃以下)的温度，其在去离子水中按体积包括在大约2％和大约30％之间的氢氧化铵。在该暴露步骤期间，其优选持续至少一分钟，可以期望施加在大约10KHz和大约2,000KHz之间的频率的声能，同时以在大约1和大约10瓦/cm2之间消耗。例如，可以通过下述来除去大约1,350埃厚的n型多晶硅层：将其在大约25℃暴露于在去离子水中按体积包括大约15％的氢氧化铵的溶液中大约30分钟，同时施加在大约1,000KHz的声能-以大约5瓦/cm2消耗。
作为替换，可以通过下述来除去n型多晶硅层：将其暴露于溶液中至少一分钟，其维持在大约60℃和大约90℃之间的温度，其在去离子水中按体积包括在大约20％和大约30％之间的TMAH，同时施加声能。可以通过下述除去基本全部的大约1,350埃厚的这种n型多晶硅层：将其在大约80℃暴露于在去离子水中按体积包括大约25％的TMAH的溶液中大约2分钟，同时施加在大约1,000KHz的声能-以大约5瓦/cm2消耗。
在除去第一多晶硅层104后，介电层105被暴露。在该实施例中，层105被除去。当介电层105包括二氧化硅时，可以利用对二氧化硅有选择性的刻蚀工艺除去它。这种刻蚀工艺可以包括将层105暴露于在去离子水中包括大约百分之一的HF的溶液中。应当限制层105被暴露的时间，因为用来除去该层的刻蚀工艺也可以除去部分介电层112。考虑到该情况，如果百分之一的HF基溶液被用于除去层105，那么该器件优选应当暴露于该溶液中少于大约60秒，并且更优选为大约30秒或更少。如图1b中所示，去除介电层105在介电层112内形成了位于侧壁隔离物108和109之间的沟槽113。
在除去介电层105之后，在沟槽113内以及衬底100之上形成高k栅介电层115。可用于制造高k栅介电层115的材料的一些包括：氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、以及铌酸铅锌。特别优选的是氧化铪、氧化锆、和氧化铝。尽管这里描述了可用于形成高k栅介电层115的材料的几个实例，但是该层可由其它材料来制造。
高k栅介电层115可以使用常规的原子层化学汽相沉积(“CVD”)工艺形成在衬底100上。在这种工艺中，金属氧化物前体(例如金属氯化物)和蒸汽可以以选择的流速馈送到CVD反应器中，然后其在选择的温度和压力下工作以在衬底100和高k栅介电层115之间产生原子平滑的界面。该CVD反应器应当运转得足够长以形成具有期望厚度的层。在大多数应用中，高k栅介电层115应当为小于大约60埃厚，并且更优选为在大约5埃和大约40埃之间厚。
如图1c中所示，当利用原子层CVD工艺形成高k栅介电层115时，该层除了形成在沟槽113的底部之上外还将形成在该沟槽的侧上，并且将形成在介电层112上。如果高k栅介电层115包括氧化物，那么它可以在任意表面位置显现氧空位以及不可接受的杂质能级，取决于用来制作它的工艺。在沉积层115之后，可以期望从该层除去杂质，并且氧化它以产生具有几乎理想化的金属：氧化学计量关系的层。
为了从该层除去杂质并且增加该层的氧含量，可以对高k栅介电层115施加湿化学处理。这种湿化学处理可以包括在充足的温度下将高k栅介电层115暴露于包括过氧化氢的溶液中充足的时间以从高k栅介电层115除去杂质并且增加高k栅介电层115的氧含量。高k栅介电层115被暴露的适当时间和温度可以取决于高k栅介电层115的期望厚度和其它特性。
当高k栅介电层115暴露于基于过氧化氢的溶液时，可以使用按体积包括在大约2％和大约30％之间的过氧化氢的水溶液。该暴露步骤应当在大约15℃和大约40℃之间进行至少大约一分钟。在特别优选的实施例中，高k栅介电层115在大约25℃的温度下暴露于按体积包含大约6.7％的H2O2的水溶液中大约10分钟。在该暴露步骤期间，可以期望施加在大约10KHz和大约2,000KHz之间的频率的声能，同时以在大约1和大约10瓦/cm2之间消耗。在优选实施例中，可以施加在大约1,000KHz的频率的声能，同时以大约5瓦/cm2消耗。
尽管在图1c中未示出，但是可以期望在高k栅介电层115上形成盖层，其不多于大约五个单层厚。这种盖层可以通过在高k栅介电层115的表面上溅射一到五个单层的硅或另一材料来形成。然后可以例如通过使用等离子体增强化学汽相沉积工艺或包含氧化剂的溶液来氧化该盖层，以形成盖层介电氧化物。
尽管在一些实施例中可以期望在层115上形成盖层，但是在所示的实施例中，直接在高k栅介电层115上形成第一金属层116以产生图1d的结构。第一金属层116可以包括任何导电材料，由该导电材料可以得到金属栅电极，并且可以使用公知的物理汽相沉积(“PVD”)或CVD工艺形成在高k栅介电层115上。类似高k栅介电层115，在该实施例中，第一金属层116的一部分给沟槽113做衬里，同时该层的一部分溢出到介电层112上。
当第一金属层116用作n型功函数金属时，层116优选具有在大约3.9eV和大约4.2eV之间的功函数。可用于形成第一金属层116的N型材料包括铪、锆、钛、钽、铝、和包括这些元素的金属碳化物，即碳化钛、碳化锆、碳化钽、碳化铪和碳化铝。第一金属层116应当足够厚以保证形成在其上的任何材料将不明显地影响其功函数。优选地，第一金属层116为在大约25埃和大约300埃之间厚，并且更优选为在大约25埃和大约200埃之间厚。
在该实施例中，在高k栅介电层115上形成第一金属层116之后，第二金属层121形成在第一金属层116上。第二金属层121填充沟槽113的剩余部分并覆盖介电层112，如图1e所示。第二金属层121优选包括可以易于抛光的材料，并且优选使用常规金属沉积工艺沉积在整个器件上方。这种填充金属可以包括氮化钛、钨、钛、铝、钽、氮化钽、钴、铜、镍、或任何可以被抛光并且可以令人满意地填充沟槽113的其它金属。
在特别优选的实施例中，填充金属121包括氮化钛。氮化钛可以使用适当的CVD或PVD工艺来抛光，其不明显影响下面的第一金属层116或高k栅介电层115。另外，当随后除去第二多晶硅层106(如下所述)时，氮化钛可以比其它金属更能抵抗用于除去该层的刻蚀化学制剂。当填充金属121包括钨时，采用WF6前体的CVD工艺可用于沉积钨层。应当注意保证用于沉积这种钨层的工艺并没有不利地影响下面的功函数和高k栅介电层。此外，当填充金属121包括钨时，可能需要选择刻蚀化学制剂来除去第二多晶硅层106，其并没有除去该填充金属的显著部分。
作为用于使用PVD、CVD、或原子层CVD工艺来在第一金属层116上形成第二金属层121的替换，第二金属层121可以使用电镀或无电极电镀工艺形成在第一金属层116上。电镀技术可以特别适于填充具有高纵横比的沟槽。可以使用沉积和电镀工艺的多种组合来形成第二金属层121。
尽管在该实施例中，第二金属层121直接形成在第一金属层116上，但是在替换实施例中，在形成第二金属层121之前，可以在第一金属层116上形成相对薄的密封层。图2a-2b示出了当执行本发明的方法的这种替换实施例时可以形成的结构的截面。如图2a中所示，密封层130形成在第一金属层116上。密封层130可以是大约100埃厚，并且可以使用常规沉积工艺形成。
密封层130应当包括高度共形的导电层，其在随后的工艺步骤期间保护功函数金属116。在这一点上，密封层130应当包括防止在随后的抛光步骤中使用的化学制剂(例如，浆液和后抛光清洗溶液)使功函数金属116和/或高k栅介电层115的性能退化的材料。适当的材料可以包括金属碳化物、金属碳化物合金、金属氮化物、和金属氮化物合金。在特别优选的实施例中，密封层130包括碳化钛并使用常规原子层CVD工艺形成。可替换地，密封层130可以包括氮化钛或氮化钽层，其使用原子层CVD或其它CVD工艺形成。
在该替换实施例中，第二金属层121形成在密封层130上，如图2b所示-例如通过使用上面结合图1e确定的材料和工艺步骤。
在形成图1e的结构之后，使用抛光步骤从介电层112上除去第二金属层121的至少一部分。在优选实施例中，应用CMP步骤来从介电层112上除去基本全部的第二金属层121以产生图1f的结构-用作抛光停止的功函数金属116。尽管可以应用这种CMP步骤来从介电层112上除去全部的填充层121，同时停止在第一金属层116上，但是在替换实施例中，在CMP操作之后第二金属层121的相对薄的部分可以保留在介电层112上。可替换地，该CMP步骤除了从介电层112上除去填充金属121之外还可以从介电层112上除去部分或全部的功函数金属116。
在该CMP步骤之后，使用刻蚀步骤从介电层112上除去另外的材料。在优选实施例中，使用干法刻蚀步骤从介电层112上除去在化学机械抛光步骤之后保留下来的基本全部的第一金属层116。在优选实施例中，这种干法刻蚀步骤对高k栅介电层115有高度选择性，使得层115能够用作刻蚀停止。该刻蚀步骤可以包括等离子体干法刻蚀工艺，例如使用氯基等离子体的一种。这种等离子体干法刻蚀工艺的持续时间可以被控制以防止在该工艺期间除去下面的高k栅介电层115的显著部分。可替换地，在除去功函数金属116的剩余部分时，这种等离子体干法刻蚀工艺可以从介电层112上除去基本全部的高k栅介电层115。
如果先前填充金属抛光步骤除去了全部的功函数金属116，则可以应用随后的干法刻蚀工艺来从介电层112上除去在抛光步骤之后保留下来的基本全部的高k栅介电层115。可替换地，层115的任何剩余部分可以使用湿法腐蚀工艺除去。这种湿法腐蚀工艺可以使用相对强的酸，例如基于卤化物的酸(例如氢溴酸或盐酸)或磷酸。类似地，如果前面的干法刻蚀工艺从介电层112上除去了功函数金属116，而没有除去全部的下面层115，那么可以采用这种湿法腐蚀工艺来除去层115的剩余部分。在从介电层112上除去高k栅介电层115之后，这种湿法腐蚀工艺还可以用于清洗所得到的结构的表面。
在使用一种或多种刻蚀工艺来从介电层112上除去基本全部的功函数金属116和/或高k栅介电层115以产生图1g的结构之后，除去第二多晶硅层106。如果层106包括p型多晶硅层，则可以通过在足够的温度(例如在大约60℃和大约90℃之间)将层106暴露于在去离子水中按体积包括在大约20％和大约30％之间的TMAH的溶液中足够的时间，同时施加声能来对第二金属层121选择性地除去该层。
在除去第二多晶硅层106之后，例如通过利用被用来除去介电层105的相同工艺除去介电层107。除去介电层107产生沟槽114，如图1h所示。在除去该介电层之后，在沟槽114内以及在介电层112上形成高k栅介电层117。用来形成高k栅介电层115的同样的工艺步骤和材料可以被用来形成高k栅介电层117。
在该实施例中，然后在高k栅介电层117上沉积第三金属层120。如果第一金属层116包括n型金属，则第三金属层120优选包括p型金属。可以使用的p型金属的实例包括：钌、钯、铂、钴、镍、和导电的金属氧化物，例如氧化钌。尽管在这里描述了可以被用来形成第三金属层120的材料的几个实例，但是该层可以由许多其它材料制成。
第三金属层120可以包括利用常规的PVD或CVD工艺形成在高k栅介电层117上的第二功函数金属。第三金属层120优选为在大约25埃和大约300埃之间厚，并且更优选为在大约25埃和大约200埃之间厚。如果第三金属层120包括p型金属，则层120优选具有在大约4.9eV和大约5.2eV之间的功函数。
在高k栅介电层117上形成第三金属层120之后，可以在第三金属层120上形成第四金属层118，例如第二填充金属，以产生图1i的结构。用来形成第二金属层121的同样的工艺步骤和材料可以被用来形成第四金属层118。然后可以除去第二填充金属118、第二功函数金属120和高k栅介电层117的覆盖介电层112的部分以产生图1j的结构。被用来从介电层112上除去第一填充金属121、第一功函数金属116和高k栅介电层115的抛光和刻蚀步骤的相同组合可以被用来从介电层112上除去第二填充金属118、第二功函数金属120和高k栅介电层117。
在从介电层112上除去第二填充金属118、第二功函数金属120和高k栅介电层117之后，可以使用常规沉积工艺在所得到的结构上沉积覆盖介电层(未示出)。在沉积这种覆盖介电层之后用于完成该器件的工艺步骤，例如形成该器件的接触、金属互连、和钝化层，对于本领域技术人员来说是公知的，并且这里将不再描述。
如上所述，本发明的方法能够制造包括高k栅介电层和金属栅电极的CMOS器件。该方法能够从下面的介电层上除去填充和功函数金属而没有除去该下面层的显著部分并且没有引起该介电层表现出厚度方面的显著变化。该方法通过应用高选择性干法刻蚀工艺来除去难以抛光的功函数金属，而不是使用抛光工艺除去它们，可以促进这种结果。尽管上述实施例提供了用于形成具有高k栅介电层和金属栅电极的CMOS器件的工艺的实例，但是本发明并不限于这些具体实施例。
尽管前述的描述已经说明了可以用在本发明中的特定步骤和材料，但是本领域的技术人员将理解的是可以进行多种修改和替代。因此，所有这些修改、变型、替代以及添加落入由所附权利要求所限定的本发明的精神和范围之内。

Claims (20)

1.一种用于制造半导体器件的方法，包括：
在衬底上形成介电层；
在介电层内形成沟槽；
在沟槽内形成高k栅介电层；
在高k栅介电层上形成第一金属层；
在第一金属层上形成第二金属层；
利用化学机械抛光步骤从该介电层上除去第二金属层的至少一部分；以及
利用等离子体干法刻蚀步骤从该介电层上除去高k栅介电层和第一金属层的至少一部分。
2.如权利要求1的方法，其中高k栅介电层包括选自由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组的材料。
3.如权利要求1的方法，其中第一金属层包括选自由铪、锆、钛、钽、铝、金属碳化物、钌、钯、铂、钴、镍以及导电的金属氧化物构成的组的功函数金属。
4.如权利要求3的方法，其中第一金属层为在大约25和大约300埃之间厚，并且具有在大约3.9eV和大约4.2eV之间的功函数。
5.如权利要求3的方法，其中第一金属层为在大约25和大约300埃之间厚，并且具有在大约4.9eV和大约5.2eV之间的功函数。
6.如权利要求1的方法，其中第二金属层包括选自由氮化钛、钨、钛、铝、钽、氮化钽、钴、铜以及镍构成的组的填充金属。
7.如权利要求1的方法，其中使用化学机械抛光步骤从介电层上除去基本全部的第二金属层。
8.如权利要求7的方法，其中使用等离子体干法刻蚀步骤从介电层上除去在化学机械抛光步骤之后保留下来的基本全部的第一金属层。
9.如权利要求7的方法，其中使用等离子体干法刻蚀步骤从介电层上除去在化学机械抛光步骤之后保留下来的基本全部的高k栅介电层。
10.一种用于制造半导体器件的方法，包括：
在衬底上形成介电层；
在介电层内形成沟槽；
在沟槽内形成高k栅介电层；
在高k栅介电层上形成第一金属层；
在第一金属层上形成密封层；
在金属碳化物密封层上形成第二金属层；
使用化学机械抛光步骤从介电层上除去密封层的至少一部分和第二金属层；以及
使用等离子体干法刻蚀步骤从介电层上除去高k栅介电层和第一金属层的至少一部分。
11.如权利要求10的方法，其中高k栅介电层包括选自由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组的材料。
12.如权利要求10的方法，其中第一金属层包括选自由铪、锆、钛、钽、铝、金属碳化物、钌、钯、铂、钴、镍以及导电的金属氧化物构成的组的功函数金属。
13.如权利要求12的方法，其中第一金属层为在大约25和大约300埃之间厚，并且具有在大约3.9eV和大约4.2eV之间的功函数。
14.如权利要求12的方法，其中第一金属层为在大约25和大约300埃之间厚，并且具有在大约4.9eV和大约5.2eV之间的功函数。
15.如权利要求10的方法，其中第二金属层包括选自由氮化钛、钨、钛、铝、钽、氮化钽、钴、铜以及镍构成的组的填充金属。
16.如权利要求10的方法，其中密封层包括选自由金属碳化物、金属碳化物合金、金属氮化物和金属氮化物合金构成的组的材料。
17.如权利要求16的方法，其中密封层使用原子层化学汽相沉积工艺形成并且包括选自由碳化钛、氮化钛和氮化钽构成的组的材料。
18.一种用于制造半导体器件的方法，包括：
在衬底上形成介电层；
在介电层内形成沟槽；
在沟槽内形成高k栅介电层；
在高k栅介电层上形成第一金属层；
在第一金属层上形成密封层；
在密封层上形成第二金属层；
利用化学机械抛光步骤从该介电层上除去第二金属层的至少一部分；以及
利用等离子体干法刻蚀步骤从该介电层上除去高k栅介电层、第一金属层和密封层的至少一部分。
19.如权利要求18的方法，其中：
高k栅介电层包括选自由氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽以及铌酸铅锌构成的组的材料；
第一金属层包括选自由铪、锆、钛、钽、铝、金属碳化物、钌、钯、铂、钴、镍以及导电的金属氧化物构成的组的功函数金属；
密封层包括选自由金属碳化物、金属碳化物合金、金属氮化物和金属氮化物合金构成的组的材料；以及
第二金属层包括选自由氮化钛、钨、钛、铝、钽、氮化钽、钴、铜以及镍构成的组的填充金属。
20.如权利要求18的方法，其中：
使用化学机械抛光步骤从介电层上除去基本全部的第二金属层；以及
使用干法刻蚀步骤从介电层上除去在化学机械抛光步骤之后保留下来的基本全部的第一金属层和基本全部的高k栅介电层。
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US7157378B2 (en) 2007-01-02
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