CN102856322A - 像素结构及像素结构的制作方法 - Google Patents

像素结构及像素结构的制作方法 Download PDF

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CN102856322A
CN102856322A CN2012103236905A CN201210323690A CN102856322A CN 102856322 A CN102856322 A CN 102856322A CN 2012103236905 A CN2012103236905 A CN 2012103236905A CN 201210323690 A CN201210323690 A CN 201210323690A CN 102856322 A CN102856322 A CN 102856322A
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CN102856322B (zh
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张维仁
罗婉瑜
陈勃学
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AU Optronics Corp
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Abstract

本发明公开了一种像素结构及其制造方法。像素结构包括一主动组件、一栅绝缘层、一介电绝缘层、一电容电极、一保护层以及一像素电极。主动元件包括一栅极、一半导体通道层、一源极以及一汲极。介电绝缘层覆盖住半导体通道层，其中介电绝缘层的介电系数高于栅绝缘层的介电系数。电容电极重迭于漏极以使电容电极、漏极以及夹于两者间的介电绝缘层构成一储存电容结构。保护层配置于介电绝缘层上并且电容电极位于保护层与介电绝缘层之间。像素电极配置于保护层上并连接于主动元件的漏极。本发明的像素结构不需大面积的电容电极就具有足够的储存电容值，而有助于提升像素结构的显示开口率。

Description

像素结构及像素结构的制作方法
技术领域
本发明是有关于一种像素结构及其制作方法，且特别是有关于一种高开口率的像素结构及其制作方法。
背景技术
目前常见的平面显示器都是以像素结构来构成显示画面所需的最小基本单元，其中像素结构大致上包括主动元件与像素电极。一般来说，经由对应的扫描线来开启特定像素结构中的主动元件时，可以让数据线提供的操作电压藉由主动元件输入给像素电极，以显示对应的显示数据。另外，像素结构中还包括储存电容器（storage capacitor），使得像素结构具有电压保持的功能。也就是，储存电容器用来储存借由主动元件输入给像素电极的操作电压，以维持像素结构的显示画面的稳定性。
储存电容器一般会借由在像素结构中以金属图案形成的电容电极来构成。为了增加储存电容器的电容值以达到良好的显示画面稳定性，往往需增加电容电极的面积。不过，这样的设计意味着金属图案的面积必须增加而降低了像素结构的显示开口率。
发明内容
本发明提供一种像素结构，具有理想的显示开口率及足够的储存电容值。
本发明提供一种像素结构的制作方法，利用介电系数高的绝缘层作为储存电容的介电层藉以让储存电容结构可以提供足够的储存电容值而不需占据大的布局面积以利于提升显示开口率。
本发明提出一种像素结构，配置于一基板上。像素结构包括一主动元件、一栅绝缘层、一介电绝缘层、一电容电极、一保护层以及一像素电极。主动元件包括一栅极、一半导体通道层、一源极以及一漏极。源极与漏极在栅极上方相隔一间距使栅极具有至少一部分不重迭于源极以及漏极，而半导体通道层至少位于间距中。栅绝缘层位于栅极与半导体通道层之间，且源极以及漏极位于栅绝缘层与半导体通道层之间。介电绝缘层配置于基板上，覆盖住半导体通道层，其中介电绝缘层的介电系数高于栅绝缘层的介电系数。电容电极配置于介电绝缘层上，且电容电极重迭于漏极以使电容电极、漏极以及夹于两者间的介电绝缘层构成一储存电容结构。保护层配置于介电绝缘层上并且电容电极位于保护层与介电绝缘层之间。像素电极配置于保护层上并连接于主动元件的漏极。
在本发明的一实施例中，上述介电绝缘层的介电系数由5至10。
在本发明的一实施例中，上述介电绝缘层的材质包括氧化铝(Al2O3)或二氧化钛(TiO2)。
在本发明的一实施例中，上述介电绝缘层的膜厚由
Figure BDA00002096493400021
至
Figure BDA00002096493400022
在本发明的一实施例中，上述介电绝缘层具有暴露出该漏极的一第一接触开口而保护层具有连通于第一接触开口的一第二接触开口使得像素电极透过彼此连通的第一接触开口与第二接触开口连接于漏极。
在本发明的一实施例中，上述半导体通道层的材质包括氧化物半导体材料。
本发明另提出一种像素结构的制作方法，包括以下步骤。于一基板上形成一栅极。于基板上形成一栅绝缘层以覆盖住栅极。于栅绝缘层上形成一源极以及一漏极。源极与漏极在栅极上方相隔一间距使栅极具有至少一部分不重迭于源极以及漏极。于源极以及漏极上形成一半导体通道层，且半导体通道层至少位于间距中。于基板上形成一介电绝缘层以覆盖住源极、漏极以及半导体通道层，且介电绝缘层的介电系数高于栅绝缘层的介电系数。于介电绝缘层上形成一电容电极。电容电极重迭于漏极使得电容电极、漏极以及夹于两者间的介电绝缘层构成一储存电容结构。于介电绝缘层上形成一保护层以覆盖住电容电极。于保护层上形成连接于漏极的一像素电极。
在本发明的一实施例中，上述形成源极与漏极的步骤、形成介电绝缘层的步骤以及形成电容电极的步骤系依序进行。
在本发明的一实施例中，上述介电绝缘层的材质包括氧化铝、二氧化钛。
在本发明的一实施例中，上述介电绝缘层的介电系数由5至10。
在本发明的一实施例中，上述形成半导体通道层的步骤系在形成源极与漏极之后进行。
在本发明的一实施例中，上述像素结构的制作方法更包括在介电绝缘层形成暴露出漏极的一第一接触开口而在保护层形成连通于第一接触开口的一第二接触开口使得后续制作的像素电极透过彼此连通的第一接触开口与第二接触开口连接于漏极。
基于上述，本发明将像素结构中漏极设置于栅极与电容电极之间，并且电容电极与漏极之间的介电绝缘层所具有的介电系数大于栅极与漏极之间的栅绝缘层所具有的介电系数。因此，本发明的像素结构不需大面积的电容电极就具有足够的储存电容值，而有助于提升像素结构的显示开口率。
附图说明
图1A至图6A绘示为本发明一实施例的像素结构的制作方法中各步骤所制作出来的构件的上视示意图。
图1B至图6B分别为图1A至图6A沿剖线I-I’的剖面示意图。
其中，附图标记：
10：基板
100：像素结构
102：主动元件
104：储存电容结构
106：像素电极
112：栅极
120：栅绝缘层
134：源极
136：漏极
140：半导体通道层
142、170：保护层
150：介电绝缘层
152：第一接触开口
160：电容电极
172：第二接触开口
D：间距
具体实施方式
图1A至图6A绘示为本发明一实施例的像素结构的制作方法中各步骤所制作出来的构件的上视示意图，而图1B至图6B分别为图1A至图6A沿剖线I-I’的剖面示意图。请先参照图1A与图1B，本发明一实施例的像素结构的制作方法包括于一基板10上制作一图案化导体层110以形成一栅极112以与栅极112所连接的扫描线114。具体而言，图案化导体层110所构成的栅极112与扫描线114由一连续的图案所构成，所以栅极112可以视为是扫描线114的一部分。不过，在其它实施例中，图案化导体层110可以包括有固定线宽的线性图案以及连接于线性图案的分支图案，其中扫描线114可以是由此具有固定线宽的线性图案所构成而栅极112可以由分支图案所构成。
图案化导体层110的材质可以为金属材料或是其它可导电的材料。在此，图案化导体层110的制作方法可以包括于基板10上先形成一导体材料层再将导体材料层图案化以构成图案化导体层110，并且图案化的步骤可以包含有微影及蚀刻。此时，形成图案化导体层110的步骤可以使用一道光掩模。在另一实施例中，图案化导体层110的制作方法可以包括以印刷方式将导体材料形成于基板10的局部面积上以构成图案化导体层110。
接着，请参照图2A与图2B，于基板10上形成覆盖图案化导体层110的栅绝缘层120并且在栅绝缘层120上形成另一图案化导体层130。在此，栅绝缘层120的材质包括氧化硅、氮化硅等绝缘材料，而图案化导体层130的材质可以包括金属材料或是非金属的导电材料，诸如金属氧化物导电材料等。图案化导体层130的制作方法可以包括于基板10上先形成一导体材料层再将导体材料层图案化以构成图案化导体层130，其中图案化的步骤可以包含有微影及蚀刻。也就是说，形成图案化导体层130的步骤可以使用另一道光掩模。
图案化导体层130包括有数据线132、源极134以及漏极136。源极134与漏极136都部分地重迭于栅极112且彼此分离。源极134与漏极136在栅极112上方相隔一间距D使栅极112具有至少一部分不重迭于源极134以及漏极136。也就是说，间距D实质上位于栅极112在厚度方向上的上方，使得栅极112在间距D处不被源极134以及漏极136所遮蔽。以本实施例而言，源极134可以为数据线132的一部分，不过本发明不以此为限。在其它的实施方式中，源极134可以是由连接于数据线132的导体图案所构成。
然后，请同时参照图3A与图3B，于源极134与漏极136上形成一半导体通道层140。形成半导体通道层140的步骤可以包括形成半导体材料层于基板10上再将此半导体材料层图案化成半导体信道层140。此时，图案化的步骤可以包含有微影及蚀刻。也就是说，形成半导体通道层140的步骤可以再使用另一道光掩模。
具体而言，半导体通道层140例如是至少位于源极134与漏极136之间的间距D中，使得半导体通道层140连接于源极134与漏极136之间。并且，半导体通道层140实质上定义出栅极112所在位置，亦即，图案化导体层110重迭于半导体通道层140的部分即为栅极112，其余部分则为扫描线114。如此一来，栅极112、源极134、漏极136以及半导体通道层140共同构成一主动元件102。
另外，栅绝缘层120位于栅极112与半导体通道层140之间，且源极134以及漏极136位于栅绝缘层120与半导体通道层140之间。由这样的堆栈方式可知，主动元件102为一共平面式(co-planar type)薄膜晶体管。也就是说，形成半导体通道层140的步骤是在形成源极134与漏极136之后进行。不过，本发明不以此为限。
半导体通道层140的材质可以是非晶硅、多晶硅、有机半导体材料或是氧化物半导体材料。也就是说，半导体通道层140可选用任何的半导体材料加以制作。若半导体通道层140的材质为氧化物半导体材料，则半导体通道层140的上表面可以选择性地配置一保护层142。也就是说，半导体通道层140的远离栅极112的表面上可以配置有保护层142，使得半导体通道层140位于保护层142与栅绝缘层120之间、位于保护层142与图案化导体层130所构成的源极134以及漏极136之间。
值得一提的是，保护层142的形成方法可以是在氧化物半导体材料的沉积程序结束之前通入氮气于相同的腔体中。因此，通道层140与保护层142包含了相同的金属元素，且保护层142的材质实质上为氧化物半导体氮化物。一般来说，作为通道层140的氧化物半导体材料包括氧化铟镓锌(Indium-Gallium-Zinc Oxide,IGZO)、氧化锌(ZnO)、氧化锡(SnO)、氧化铟锌(Indium-Zinc Oxide,IZO)、氧化镓锌(Gallium-Zinc Oxide,GZO)、氧化锌锡(Zinc-Tin Oxide,ZTO)或氧化铟锡(Indium-Tin Oxide,ITO)。因此，保护层142的材质对应地包括氧化铟镓锌氮化物(IGZON)、氧化锌氮化物(ZnON)、氧化锡氮化物(SnON)、氧化铟锌氮化物(IZON)、氧化镓锌氮化物(GZON)、氧化锌锡氮化物(ZTON)或氧化铟锡氮化物(ITON)。
在本实施例中，氧化物半导体氮化物与氧化物半导体材料可在同一沉积腔室内以原位(in-situ)沉积程序或是连续沉积程序形成。所以，于基板10上形成氧化物半导体氮化物与氧化物半导体材料的过程中，基板10完全没有离开沉积腔室。因此，氧化物半导体材料会一直被氧化物半导体氮化物覆盖而不会被暴露于大气环境之中。如此一来，氧化物半导体氮化物所构成的保护层142可以提供适当的保护，使得氧化物半导体材料所构成的半导体通道层140不会受到大气环境中的水气以及氧气的影响，而保有较佳的电性表现。不过，保护层142的配置及制作仅是举例说明之用，并非用以限定本发明。在其它实施例中，半导体通道层140的材质为多晶硅或非晶硅等较不容易受到水气影响的材质时，半导体通道层140可不需被保护层142所覆盖。
之后，请参照图4A与图4B，于基板10上形成一介电绝缘层150以及于介电绝缘层150上形成一电容电极160。介电绝缘层150配置于基板10上，并覆盖住主动元件102，而电容电极160配置于介电绝缘层150上。此外，电容电极160重迭于漏极136以使电容电极160、漏极136以及夹于两者间的介电绝缘层150构成一储存电容结构104。本实施例中，形成源极134与漏极136的步骤、形成介电绝缘层150的步骤以及形成电容电极160的步骤是依序进行而构成储存电容结构104。也就是说，储存电容结构104是漏极136、介电绝缘层150以及电容电极160由基板10向外依序堆栈而构成。
在此，电容电极160的制作方法可以包括于基板10上先形成一导体材料层再将导体材料层图案化以构成电容电极160，其中图案化的步骤可以包含有微影及蚀刻。也就是说，形成电容电极160的步骤可以再使用另一道光掩模。电容电极160例如是由金属等导体材料制作而成并且电容电极160可以横越于数据线132，例如与扫描线114平行配置。整体而言，本实施例例如采用了三层导体层来构成主动元件102与电容电极160。
另外，形成介电绝缘层150的步骤例如是物理气相沉积法，且介电绝缘层150可以采用介电系数高的绝缘材料所制作而成。举例而言，介电绝缘层150的材质包括氧化铝、氧化钛或是其它可以利用物理气相沉积法、溅镀法制作的金属氧化物材料，其中氧化铝包括三氧化二铝而氧化钛包括二氧化钛。
以本实施例而言，栅绝缘层120的材质例如为氧化硅或是氮化硅，而介电绝缘层150的材质包括氧化铝或氧化钛。所以，介电绝缘层150的介电系数高于栅绝缘层120，其中介电绝缘层150的介电系数例如由5至10。由于介电绝缘层150的介电系数高于栅绝缘层120的介电系数，所以介电绝缘层150的膜厚约为至
Figure BDA00002096493400072
即可以提供足够的介电性质。相较的下，栅绝缘层120可能需要
Figure BDA00002096493400073
至
Figure BDA00002096493400074
才可以提供足够的介电性质。因此，本实施例的介电绝缘层150的膜厚可以小于栅绝缘层120的膜厚。
值得一提的是，本实施例的介电绝缘层150的材质为氧化铝或氧化钛，这样的材料的沉积速率较低，而不利于应用在栅绝缘层120的制作。因此，本实施例采用不同介电性质的材质分别制作栅绝缘层120与介电绝缘层150可以避免栅绝缘层120的制作时程拉长而不利于主动元件102的整体制作，也可以利用介电绝缘层150提供理想的介电特性来实现所需要的储存电容结构104。举例而言，介电绝缘层150具有高介电系数及小膜层厚度，这有助于提高储存电容结构104的单位面积电容并有助于缩减储存电容结构的面积大小。
接着，请参照图5A与图5B，于介电绝缘层150上形成一保护层170，使得电容电极160夹于介电绝缘层150与保护层170之间。另外，本实施例还进一步在介电绝缘层150上形成一第一接触开口152以及在保护层170上形成一第二接触开口172。第一接触开口152暴露出漏极136，而第二接触开口172连通于第一接触开口152。因此，漏极136可以由第一接触开口152与第二接触开口172共同暴露出来。
之后，请参照图6A与图6B，于基板10上形成一像素电极106，像素电极106借由第一接触开口152以及第二接触开口172而连接至漏极136，借此形成配置于基板10上的像素结构100。
详言的，像素结构100包括主动元件102、一栅绝缘层120、介电绝缘层150、电容电极160、保护层170以及像素电极106。主动元件102包括栅极112、半导体通道层140、源极134以及漏极136。像素电极106配置于保护层170上并连接于主动元件102的漏极136。电容电极160配置于介电绝缘层150上，且电容电极160重迭于漏极136以使电容电极160、漏极136以及夹于两者间的介电绝缘层150构成储存电容结构104。保护层170配置于介电绝缘层150上并且电容电极160位于保护层170与介电绝缘层150之间。另外，介电绝缘层150配置于基板10上，覆盖住半导体通道层140、源极134与漏极136。
以主动元件102而言，源极134与漏极136在栅极112上方相隔一间距D，使栅极112具有至少一部分不重迭于源极134以及漏极136。并且，半导体通道层140至少位于间距D中以连接于源极134与漏极136之间。栅绝缘层120位于栅极112与半导体通道层140之间，且源极134以及漏极136位于栅绝缘层120与半导体通道层140之间。因此，主动元件102可以为共平面式薄膜晶体管。
在本实施例中，介电绝缘层150的介电系数高于栅绝缘层120的介电系数，其中介电绝缘层150的介电系数可以由5至10。并且，介电绝缘层150的膜厚由10
Figure BDA00002096493400081
至800
Figure BDA00002096493400082
。因此，本实施例的设计有助于使储存电容结构104具有理想的电容值而不需很大的布局面积，进而有助于提高像素结构100的显示开口率。
一般而言，一个电容结构由两电极与夹于两电极之间的中间层所构成。电容结构的电容值会与两电极的重迭面积成正比，并且与中间层的膜厚(两电极之间的距离)成反比。另外，中间层的膜厚又与其材质的介电系数有关。举例而言，为了达到相同的介电性质，高介电系数材质构成的中间层所需膜厚较小，而低介电系数材质构成的中间层所需膜厚较大。因此，以不同介电系数的材料作为两电极之间的中间层时除了影响着电容结构的电容值大小，也影响两电极的重迭面积所需大小。
根据本实施例的设计，使用介电系数较高的材料(例如氧化铝)作为电容电极160与漏极136两电极之间的中间层(也就是介电绝缘层150)时，氧化铝的介电系数约为7。因此，介电绝缘层150具有的膜厚约为
Figure BDA00002096493400083
至
Figure BDA00002096493400084
即可以提供足够的介电特性。此时，借由电容电极160与漏极136重迭所构成的储存电容结构104具有的单位面积电容约为1.239fF/μm2。
在一比较例中，使用介电系数较低的材料(例如氧化硅)作为储存电容结构的两电极之间的中间层时，氧化硅的介电系数约为3.8。因此，中间层具有的膜厚约为
Figure BDA00002096493400085
才可以提供足够的介电性质。此时，借由两电极重迭所构成的电容结构具有的单位面积电容约为0.374fF/μm2。
根据上述单位面积电容，要实现相同电容值的设计时，比较例的电容结构中两电极重迭面积约需要为本实施例的电容电极160与漏极136两电极重迭面积的3.313倍。也就是说，本实施例使用高介电系数的材质制作储存电容结构104中的介电绝缘层150有助于使储存电容结构104在有限的布局面积中即具有理想的电容值或是有助于以更小的布局面积达到相同的电容值。当电容电极160由不透光的材料制作(也就是储存电容结构104为不透光的构件)时，本实施例的设计可以因为储存电容结构104所需面积较小而不致对显示开口率有负面的影响。
另外，本实施例的介电绝缘层150由致密度高的氧化铝等材料制作，所以除了高介电性质外，还可以进一步保护半导体通道层140以避免外界物质(诸如水气等)对半导体通道层140造成的损坏。因此，本实施例的像素结构100使用氧化物半导体材料作为配置于主动元件102中的半导体通道层140时，半导体通道层140可以提供理想的电性特性而且不容易损坏。
综上所述，本发明以介电系数较高的材料当作储存电容结构的介电绝缘层，有助于缩减储存电容结构所需要的配置面积，进而提升显示开口率。因此，本发明实施例的像素结构可以具有高显示开口率以及足够的储存电容值。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

1.一种像素结构，配置于一基板上，其特征在于，该像素结构包括：
一主动元件，包括一栅极、一半导体通道层、一源极以及一漏极，该源极与该漏极在该栅极上方相隔一间距使该栅极具有至少一部分不重迭于该源极以及该漏极，该半导体信道层至少配置于该间距中；
一栅绝缘层，位于该栅极与该半导体通道层之间，且该源极以及该漏极位于该栅绝缘层与该半导体通道层之间；
一介电绝缘层，配置于该基板上，覆盖住该半导体通道层，其中该介电绝缘层的介电系数高于该栅绝缘层的介电系数；
一电容电极，配置于该介电绝缘层上，且该电容电极重迭于该漏极以使该电容电极、该漏极以及夹于两者间的该介电绝缘层构成一储存电容结构；
一保护层，配置于该介电绝缘层上并且该电容电极位于该保护层与该介电绝缘层中；以及
一像素电极，配置于该保护层上并连接于该主动元件的该漏极。
2.根据权利要求1所述的像素结构，其特征在于，该介电绝缘层的介电系数由5至10。
3.根据权利要求1所述的像素结构，其特征在于，该介电绝缘层的材质包括氧化铝或二氧化钛。
4.根据权利要求1所述的像素结构，其特征在于，该介电绝缘层的膜厚由至
5.根据权利要求1所述的像素结构，其特征在于，该介电绝缘层具有暴露出该漏极的一第一接触开口而该保护层具有连通于该第一接触开口的一第二接触开口使得该像素电极通过彼此连通的该第一接触开口与该第二接触开口连接于该漏极。
6.根据权利要求1所述的像素结构，其特征在于，该半导体通道层的材质包括氧化物半导体材料。
7.一种像素结构的制作方法，其特征在于，包括：
于一基板上形成一栅极；
于该基板上形成一栅绝缘层以覆盖住该栅极；
于该栅绝缘层上形成一源极以及一漏极，该源极与该漏极在该栅极上方相隔一间距使该栅极具有至少一部分不重迭于该源极以及该漏极；
于该源极以及该漏极上形成一半导体通道层，该半导体通道层至少位于该间距中；
于该基板上形成一介电绝缘层以覆盖住该源极、该漏极以及该半导体通道层，且该介电绝缘层的介电系数高于该栅绝缘层的介电系数；
于该介电绝缘层上形成一电容电极，该电容电极重迭于该漏极使得该电容电极、该漏极以及夹于两者间的该介电绝缘层构成一储存电容结构；
于该介电绝缘层上形成一保护层以覆盖住该电容电极；以及
于该保护层上形成连接于该漏极的一像素电极。
8.根据权利要求7所述的像素结构的制作方法，其特征在于，形成该源极与该漏极的步骤、形成该介电绝缘层的步骤以及形成该电容电极的步骤为依序进行。
9.根据权利要求7所述的像素结构的制作方法，其特征在于，该介电绝缘层的材质包括氧化铝或二氧化钛。
10.根据权利要求7所述的像素结构的制作方法，其特征在于，该介电绝缘层的介电系数由5至10。
11.根据权利要求7所述的像素结构的制作方法，其特征在于，形成该半导体通道层的步骤是在形成该源极与该漏极之后进行。
12.根据权利要求7所述的像素结构的制作方法，其特征在于，更包括在该介电绝缘层形成暴露出该漏极的一第一接触开口以及在该保护层形成连通于该第一接触开口的一第二接触开口使得后续制作的该像素电极通过彼此连通的该第一接触开口与该第二接触开口连接于该漏极。
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