CN102804370B - 具有穿透衬底互连的微电子装置及相关制造方法 - Google Patents
具有穿透衬底互连的微电子装置及相关制造方法 Download PDFInfo
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- CN102804370B CN102804370B CN201180014446.4A CN201180014446A CN102804370B CN 102804370 B CN102804370 B CN 102804370B CN 201180014446 A CN201180014446 A CN 201180014446A CN 102804370 B CN102804370 B CN 102804370B
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- metal layer
- interconnected pores
- semiconductor substrate
- dielectric
- electric conducting
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Classifications
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Abstract
本文揭示具有穿透衬底互连的微电子装置和相关制造方法。在一个实施例中,半导体装置包括携载第一金属化层和第二金属化层的半导体衬底。所述第二金属化层与所述半导体衬底间隔开,其中所述第一金属化层位于其间。所述半导体装置还包括至少部分延伸穿透所述半导体衬底的导电互连。所述第一金属化层经由所述第二金属化层与所述导电互连电接触。
Description
技术领域
本发明技术概括来说涉及具有穿透衬底互连的微电子装置和相关制造方法。
背景技术
半导体晶粒通常包括多个集成电路、耦合到集成电路的接合垫和用于使电信号在接合垫与外部触点之间路由的金属路由层。制作和封装所述半导体晶粒包括形成互连以使接合垫和/或金属路由层电耦合到外部装置(例如,引线框、印刷电路板等)。
在一些应用中,互连延伸完全穿透半导体晶粒或穿透半导体晶粒的大部分(通常称为“穿透衬底互连”)。用于形成穿透衬底互连的一种常规工艺可包括在晶粒的前侧和/或后侧上形成与相应接合垫对准的深导通孔。然后用导电材料(例如,铜)填充所述导通孔。随后将焊料球和/或其它外部电触点附接到穿透衬底互连。
穿透衬底互连可(1)在整合处理之前形成(通常称为“先钻孔”工艺),或(2)在整合处理已实质上完成后,形成(通常称为“后钻孔”工艺)。然而,先钻孔和后钻孔工艺二者均具有某些缺点,如下文所更详细论述。因此,可期望穿透衬底形成工艺的一些改良。
发明内容
本发明的一个实施例公开了一种制作半导体装置的方法,其包含:在半导体衬底上形成第一、第二、……和第N个金属化层,N是不小于3的正整数;至少在形成第一金属化层后,形成至少部分位于半导体衬底中的互连孔;和用导电材料填充互连孔,导电材料与金属化层中的至少一者电接触。
进一步地,形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于半导体衬底中的互连孔。
进一步地,形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于半导体衬底中的互连孔;且形成第一、第二、……和第N个金属化层包括在用导电材料填充互连孔后,形成第N-1个金属化层。
进一步地,形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于半导体衬底中的互连孔;形成第一、第二、……和第N个金属化层包括在用导电材料填充互连孔后,形成第N-1个金属化层;且方法进一步包括使第N-1个金属化层与互连孔中的导电材料直接接触。
进一步地,形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于半导体衬底中的互连孔;形成第一、第二、……和第N个金属化层包括在用导电材料填充互连孔后,形成第N-1个金属化层;且方法进一步包括直接在第N-1个金属化层与互连孔中的导电材料之间形成导电导通孔。
进一步地,形成互连孔包括在形成第N-1个金属化层后,形成至少部分位于半导体衬底中的互连孔;且填充互连孔包括用导电材料填充互连孔,其中第一部分与第N-1个金属化层直接接触且第二部分位于互连孔中。
进一步地,形成互连孔包括在形成第N-1个金属化层后,形成至少部分位于半导体衬底中的互连孔;方法进一步包括暴露第N-1个金属化层的至少一部分;且填充互连孔包括将互连孔引入互连孔中和第N-1个金属化层的暴露部分上。
附图说明
图1为本技术实施例的具有堆叠晶粒的微电子封装的示意性剖面图。
图2A-2N为本技术实施例的经历可用于形成图1中所显示半导体晶粒的一些实施例的工艺的半导体衬底的一部分的示意性剖面图。
图3A-3F为本技术其它实施例的经历可用于形成图1中所显示半导体晶粒的一些实施例的工艺的半导体衬底的一部分的示意性剖面图。
图4A-4F为本技术其它实施例的经历可用于形成图1中所显示半导体晶粒的一些实施例的工艺的半导体衬底的一部分的示意性剖面图。
具体实施方式
下文参照用于在半导体衬底中形成通孔和导电路由层的工艺阐述本发明技术的一些实施例。下文参照半导体晶粒阐述某些实施例的许多细节。全文使用术语“半导体衬底”以包括各种制品,举例来说,包括个别集成电路晶粒、成像器晶粒、传感器晶粒和/或具有其它半导体特征的晶粒。
下文所述工艺中的一些可用于在晶片或一部分晶片上在个别晶粒中或在多个晶粒中形成通孔和导电路由层。晶片或晶片部分(例如,晶片形式)可包括未经单个化的晶片或晶片部分、或经重新组装的载体晶片。经重新组装的载体晶片可包括周边形状与未经单个化的晶片的形状相当的大体刚性框围绕的粘合剂材料(例如,柔性粘合剂),且可包括由所述粘合剂围绕的经单个化的元件(例如,晶粒)。
图1-4F中阐述某些实施例的许多具体细节且以下文字用以提供对这些实施例的透彻理解。一些其它实施例可具有与那些下文所述者不同的配置、组件和/或工艺。因此,相关领域技术人员应了解,在图1-4F中未给出所述实施例的一些细节的情况下可实施其它实施例。
图1是本技术实施例的微电子封装100的一部分的示意性剖面图。如图1中所显示,微电子封装100可包括与多个半导体晶粒102串联堆叠的多个导电耦合器104(例如,焊料球)。出于图解说明目的,图1中显示四个半导体晶粒102(分别个别地识别为第一、第二、第三和第四半导体晶粒102a-102d)。在其它实施例中,微电子封装100可包括任一其它期望数量的半导体晶粒102,其经由线接合、焊料球、导电带和/或其它适宜电连接器而彼此耦合。
半导体晶粒102可个别地包括半导体衬底106,其在靠近半导体衬底106的第一侧106a携载信号路由结构108;位于信号路由结构108上的多个接合垫112(分别个别地识别为第一到第五接合垫112a-112e);和于半导体衬底106的第一侧106a与第二侧106b之间延伸的多个穿透衬底互连110(分别个别地识别为第一到第四互连110a-110d)。半导体晶粒102还可包括与第一穿透衬底互连110a相连的输入/输出(“I/O”)缓冲器114和与第二、第三和第四穿透衬底互连110b-110d相连的芯片选择(“C/S”)缓冲器116。
将穿透衬底互连110可选择性地连接到信号路由结构108中的某些金属化层(图1中未显示)用以在半导体晶粒102的第一侧106a与第二侧106b之间携载电信号。下文参照图2A-4F更详细地论述用于形成信号路由结构108和穿透衬底互连110的工艺的一些实施例的细节。
可基于期望信号路由方案使导电耦合器104与相应接合垫112介接。如图1中所显示,并非所有接合垫112均电耦合到导电耦合器104中的一者。举例来说,第一半导体晶粒102a的第一穿透衬底互连110a经由导电耦合器104和第一半导体晶粒102a的第一接合垫112a电耦合。相反,所有半导体晶粒102的第二接合垫112b、第三半导体晶粒102c的第三接合垫112c和第四半导体晶粒102d的第三和第四接合垫112c和112d未电耦合到导电耦合器104中的任一者。取而代之,信号路由结构108将于第一半导体晶粒102a的第二接合垫112b处接收的芯片选择信号(和/或其它适宜信号)经由第一半导体晶粒102a的第二穿透衬底互连110b、第二半导体晶粒102b的第三穿透衬底互连110c和第三半导体晶粒102c的第四穿透衬底互连110d路由到第四半导体晶粒102d的C/S缓冲器116。
在操作期间,经电耦合的半导体晶粒102的第一穿透衬底互连110a形成电路径用以将输入/输出信号携载到所有半导体晶粒102。个别半导体晶粒102的信号路由结构108将输入/输出信号从电路径路由到半导体晶粒102的个别I/O缓冲器114。信号路由结构108还可将芯片选择信号(和/或其它适宜信号)路由到所选半导体晶粒102以便能够在所选半导体晶粒102处理于I/O缓冲器114处接收的输入/输出信号。举例来说,信号路由结构108将于第五接合垫112e处接收的芯片选择信号路由到第一半导体晶粒102a的C/S缓冲器116以便第一半导体晶粒102a能够处理接收的输入/输出信号。在另一实例中,信号路由结构108还可将于第四接合垫112d处接收的芯片选择信号经由第一半导体晶粒102a的第四穿透衬底互连110d路由到第二半导体晶粒102b。
根据常规技术,可基于先钻孔工艺或后钻孔工艺形成穿透衬底互连110。然而,本发明者已认识到,先钻孔和后钻孔工艺二者均具有某些缺点。举例来说,后钻孔工艺可能无法充分适应芯片选择信号的路由,这是因为所述修改可显著增加制造工艺的成本和/或复杂性。举例来说,可用于在最后金属化层路由信号的技术可包括(1)控制毗邻半导体晶粒102形成(或避免形成)导电凸块;(2)将信号路由返回到下部金属化层;(3)向信号路由结构108添加控制栅极(例如,MOSFET);(4)以不同方式对半导体晶粒102的每一者实施图案化;和(5)在半导体晶粒102上添加再分布层(未显示)。
本发明者还认识到,先钻孔工艺可对半导体晶粒102的电可靠性造成不利影响,此乃因在信号路由结构108形成期间半导体晶粒102中信号路由结构108与集成电路(未显示)之间的电触点可能受到损坏。下文参照图2A-2N论述用于解决先钻孔和后钻孔工艺的至少一些上述缺点的工艺的一些实施例。
图2A-2N是本技术实施例的经历用于形成图1中所显示半导体晶粒102的一些实施例的工艺的半导体衬底106的一部分的示意性剖面图。在下列说明中,类似处理操作可利用大致类似的处理技术。因此,为简便起见,用于实施处理操作(例如,对所沉积材料实施图案化、去除部分电介材料、沉积导电材料等)的适宜技术仅描述一次。
如图2A中所显示,所述工艺可包括在半导体衬底106的第一侧106a中和/或在其上形成集成电路118。在所图解说明实施例中,出于图解说明目的,集成电路118是作为具有源极120a、漏极120b和栅极122的场效晶体管示意性地显示。在其它实施例中,集成电路118还可包括垂直晶体管、三维晶体管、电容器和/或其它可形成动态随机存取存储器(DRAM)和/或其它适宜电子装置的适宜电组件。
所述工艺可包括在半导体衬底106上形成绝缘体124。在所图解说明实施例中,绝缘体124包括四个氧化硅、氮化硅和/或其它适宜电介质的层(分别个别地识别为第一到第四绝缘材料124a-124d)。在其它实施例中,绝缘体124还可包括另一期望数量的电介质和/或其它适宜绝缘材料。用于形成绝缘体124的技术可包括热氧化、化学气相沉积(“CVD”)、原子层沉积(“ALD”)、旋涂玻璃和/或其它适宜技术。
所述工艺还可包括在绝缘体124中形成导电链路126,其电连接到集成电路118。在一个实施例中,形成导电链路126包括使用光刻和/或其它适宜技术对绝缘体124实施图案化,和经由湿蚀刻、干蚀刻、反应性离子蚀刻和/或其它适宜技术去除一部分图案化绝缘体124以形成孔127。然后可使用导电材料129(例如,铜、铝、金和/或其它适宜导电材料)经由物理气相沉积(PVD)、CVD、ALD、电镀和/或其它适宜技术来填充孔127。在其它实施例中,除上述操作以外或替代所述操作,形成导电链路126可包括其它处理操作。
所述工艺可包括形成第一金属化层128a,其通过以下方式实施:在绝缘体124上形成第一电介质130,根据期望金属路由轮廓对第一电介质130实施图案化,去除一部分第一电介质130以在第一电介质130中形成沟槽、通道和/或其它开口135,和在开口135中沉积导电材料137(例如,铜、铝、金和/或其它适宜导电材料)。所述工艺然后可包括在第一金属化层128a上形成第一障壁132(例如,由应用材料(AppliedMaterials)公司,圣塔克拉拉(SantaClara),加利福尼亚(California)提供的BLOK)和在第一障壁132上沉积第二电介质134(例如,氧化硅)。第二电介质134包括靠近第一障壁132的第一表面134a和与第一表面134a相对的第二表面134b。
在形成第一金属化层128a后,图2B-2H图解说明用于在半导体衬底106中形成穿透衬底互连110(图1)的穿透衬底互连形成工艺模块(下文称为“TSV模块”)。如图2B中所显示,TSV模块可包括经由旋涂和/或其它适宜技术在第二电介质134上沉积第一光致抗蚀剂136。然后可对第一光致抗蚀剂136实施图案化以形成第一开口138。本文所用术语“光致抗蚀剂”通常是指当暴露于电磁辐射时可发生化学改质的材料。所述术语涵盖经构造以使当通过电磁辐射活化时可溶的正性光致抗蚀剂和经构造以使当通过光活化时可溶的负性光致抗蚀剂。
如图2C中所显示,TSV模块可包括在半导体衬底106中形成互连孔140。互连孔140可通过以连续操作方式经由开口138从第一电介质130、第一障壁132、第二电介质134、绝缘体124和至少一部分半导体衬底106去除材料来形成。在其它实施例中,形成互连孔140可包括第一材料去除操作(例如,使用湿蚀刻)以去除一部分第一电介质130、第一障壁132、第二电介质134和绝缘体124;和第二材料去除操作(例如,使用反应性离子蚀刻)以去除一部分半导体衬底106。
如图2D中所显示,TSV模块可进一步包括去除第一光致抗蚀剂136和在互连孔140中依次形成孔绝缘体142、孔障壁144和晶种材料146。孔绝缘体142可包括经由热氧化、CVD、ALD和/或其它适宜技术形成的氧化硅、氮化硅和/或其它适宜绝缘材料。孔障壁144可包括经由脉冲化学气相沉积(“pCVD”)、离子物理气相沉积(“iPVD”)、ALD和/或其它适宜技术形成的钽(Ta)、钨(W)、氮化钛(TiN)和/或其它适宜障壁材料。晶种材料144可包括经由pCVD、iPVD、ALD和/或其它适宜技术沉积得到的铜、钨和/或其它适宜导电材料。
如图2E中所显示,TSV模块还可包括在晶种材料146上沉积第二光致抗蚀剂148。然后可对第二光致抗蚀剂148实施图案化以形成第二开口150。如图2F中所显示,TSV模块可包括经由第二开口150用第一导电材料152填充互连孔140以形成穿透衬底互连110。第一导电材料152包括位于互连孔140中的第一部分152a和延伸超过第二电介质134的第二部分152b。第一导电材料152可包括铜、铝、钨、金和/或具有上述成份的合金。在具体实施例中,第一导电材料152包括引入到互连孔140中的电解铜。电解铜与无电沉积的材料相比且与焊料相比具有提高的纯度。举例来说,第一导电材料152可为至少90%铜且在某些情形下为99%铜。然后可去除第二光致抗蚀剂148。
如图2G中所显示,随后可去除第一导电材料152的第二部分152b(图2F)以使第一导电材料152的第一部分152a与第二电介质134的第二表面134b大致处于平面。用于去除第一导电材料152的第二部分152b的技术可包括化学-机械抛光(“CMP”)、电化学-机械抛光(“ECMP”)和/或其它适宜技术。如图2H中所显示,TSV模块可任选地包括在第二电介质134的第二表面134b和第一导电材料152的第一部分152a上沉积第二障壁154(例如,由应用材料(AppliedMaterials)公司,圣塔克拉拉(SantaClara),加利福尼亚(California)提供的BLOK)。在其它实施例中,可省略第二障壁154的沉积。
尽管上文所论述的TSV模块包括对第二光致抗蚀剂148实施沉积和图案化,但在某些实施例中,可省略第二光致抗蚀剂148。取而代之,TSV模块可包括沉积第一导电材料152,其中第一部分152a在互连孔140中且第二部分152b实质上覆盖第二电介质134的第二表面134b。随后,可去除第二部分152b的至少一部分以产生如图2G中所显示的穿透衬底互连110。
在TSV模块后,所述工艺可包括形成第二金属化层。如图2I中所显示,所述工艺可包括在可选第二障壁154上形成第三电介质156。第三电介质156包括靠近可选第二障壁154的第一表面156a和与第一表面156a相对的第二表面156b。然后,可形成穿透第三电介质156、可选第二障壁154和第二电介质134通往第一金属化层128a的多个第一导通孔159。
所述工艺然后可包括在第三电介质156上沉积第三光致抗蚀剂158和对第三光致抗蚀剂158实施图案化以形成对应于第二金属化层128b(未显示)的期望路由轮廓的第三开口160。如图2J中所显示,所述工艺可包括去除一部分第三电介质156和任选地去除一部分第二障壁154以形成开口162。开口162暴露第二电介质134的第二表面134b的至少一部分和第一导电材料152的第一部分152a的上表面。
如中图2K所显示,所述工艺可包括用第二导电材料164填充开口162和第一导通孔159且随后去除开口162外部过多的第二导电材料164以使第二导电材料164与第三电介质156的第二表面156b大致处于平面。在所图解说明实施例中,第二导电材料164包括第一部分164a、横向延伸远离第一部分164a的第二部分164b和位于第一导通孔159中的第三部分164c。第二导电材料164的第一部分164a与穿透衬底互连110的第一导电材料152的第一部分152a直接实体接触。第二导电材料164的第三部分164c电连接到第二部分164b和第一金属化层128a。
在一个实施例中,第二导电材料164包括与第一导电材料152相同的组成(例如,铜)。因此,第一导电材料152和第二导电材料164可大致相同(在图2K中使用虚线来显示第一导电材料152与第二导电材料164之间的人为分界线)。在其它实施例中,第二导电材料164可包括至少部分不同于第一导电材料152a的组成。因此,第一金属化层128a经由第二导电材料164电连接到穿透衬底互连110。
在形成第二金属化层128b后,所述工艺可包括在半导体衬底106上形成其它金属化层。举例来说,图2L和2M图解说明形成第三金属化层128c的操作。如图2L中所显示,所述工艺可包括在第三电介质156的第二表面156b和第二金属化层128b上沉积第四电介质166。所沉积第四电介质166具有靠近第三电介质156的第一表面166a和与第一表面166a相对的第二表面166b。所述工艺然后可包括实施图案化和去除一部分第四电介质166以形成多个从第四电介质166的第二表面166b延伸到第二金属化层128b的第二导通孔168。
然后可根据与那些参照图2I和2J所阐述者大致类似的操作形成第三金属化层128c。如图2M中所显示,第三金属化层128c包括第三导电材料170,其经由第二导通孔168电连接到第二金属化层128b。在所图解说明实施例中,第三导电材料170具有与第一导电材料152和第二导电材料164相同的组成(例如,铜)。在其它实施例中,第三电介材料170可具有不同于第一电介材料152和/或第二电介材料164的组成。
在某些实施例中,所述工艺还可包括对半导体衬底106实施处理以在半导体衬底106中和/或在其上形成其它特征。举例来说,如图2N中所显示,可使用机械或化学-机械技术从第二侧106b去除一部分半导体衬底106以暴露穿透衬底互连110。然后可将导电组件172(例如,导电柱、焊料球、焊料凸块、再分布层、穿透硅导通孔螺柱和/或其它适宜的互连装置)附接到穿透衬底互连110用以与外部组件(未显示)互连。
尽管图2A-2M中仅图解说明第一金属化层128a、第二金属化层128b和第三金属化层128c,但在某些实施例中,所述工艺可包括通过重复至少上文参照图2L和2M所论述的一些操作来形成四个、五个或任一期望数量的金属化层。在这些实施例中,穿透衬底互连110可电连接到第二金属化层128b、第三金属化层128c或N-1金属化层(未显示)。
上述工艺的一些实施例可降低损坏第一金属化层128a与导电链路126之间的电连接的风险。本发明者已观察到在形成第一金属化层128a之前形成穿透衬底互连110会在第一金属化层128a与导电链路126之间产生有缺陷的电连接。不欲受理论限制,我们认为在形成第一金属化层128a期间的一些操作(例如,沉积导电材料、去除多余的导电材料等)可实质上减弱和/或损坏第一金属化层128a与导电链路126之间的电连接。因此,通过在形成第一金属化层128a后形成穿透衬底互连110可降低产生有缺陷的电连接的风险。
上述工艺的一些实施例与常规技术相比还会更成本有效且更灵活。举例来说,穿透衬底互连110与金属化层之间电连接的选择可推迟到晚于先钻孔工艺的处理阶段进行。因此,可增加通用中间产品(即,部分形成金属化层的半导体晶粒)的数量以便在对半导体晶粒102的最终连接配置作出决定前生产管理人员能够连续生产半导体晶粒102。
尽管上文参照图2A-2N论述形成第二金属化层128b并将其连接到穿透衬底互连110的特定操作,但在其它实施例中,可使用其它和/或不同工艺操作形成第二金属化层128b并将其连接到穿透衬底互连110。举例来说,图3A-3F是本技术其它实施例的经历用于形成图1中所显示半导体晶粒102的一些实施例的工艺的半导体衬底的一部分的示意性剖面图。如图3A中所显示,所述工艺可包括在半导体衬底106中和/或在其上形成集成电路118,形成导电链路126、第一金属化层128a并在第一金属化层128a上形成第一障壁132,如上文参照图2A所述。
与图2A中所显示实施例不同,图3B中所显示工艺可包括在第一障壁132上沉积第二电介质134之前利用TSV模块,如上文参照图2B-2H所论述。随后,可在第一障壁132和穿透衬底互连110上形成第二电介质134。因此,穿透衬底互连110与第一障壁132可大致处于平面且可直接接触第二电介质134的第一表面134a。
如图3C中所显示,所述工艺可包括在第二电介质134上沉积第三电介质156。因此,第三电介质156的第一表面156a可直接接触第二电介质134的第二表面134b。所述工艺可包括在第二电介质134和第三电介质156中形成穿透第三电介质156、第二电介质134和障壁132的多个存取导通孔180。存取导通孔180包括(1)大致对应于穿透衬底互连110的存取导通孔180的第一组180a;和(2)大致对应于第一金属化层128a的存取导通孔180的第二组180b。
所述工艺然后可包括在第三电介质156上沉积光致抗蚀剂182和对光致抗蚀剂182实施图案化以形成对应于第二金属化层128b期望路由轮廓的开口184。如图3E中所显示,所述工艺可包括去除一部分第三电介质156以形成开口186。开口186暴露第二电介质134的第二表面134b的至少一部分并与存取导通孔180中的至少一些连通。
如图3F中所显示,所述工艺可包括用第二导电材料164填充开口186和存取导通孔180。然后可去除开口186外多余的第二导电材料164以使第二导电材料164与第三电介质156的第二表面156b大致处于平面。第二导电材料164包括第一部分164a、横向延伸远离第一部分164a的第二部分164b、位于存取导通孔180的第一组180a中的第三部分164c和位于存取导通孔180的第二组180b中的第四部分164d。第二导电材料164的第三部分164c使第二导电材料164的第一部分164a电连接到穿透衬底互连110。第二导电材料164的第四部分164d使第二导电材料164的第二部分164b电连接到第一金属化层128a。如参照图2L-2N所论述,所述工艺然后可包括形成其它金属化层和实施后续处理。
图4A-4F为本技术其它实施例的经历用于形成图1中所显示半导体晶粒102的一些实施例的工艺的半导体衬底100的一部分的示意性剖面图。如图4A中所显示,所述工艺可包括在半导体衬底106中和/或在其上形成集成电路118,形成导电链路126、第一金属化层128a并在第一金属化层128a上形成第一障壁132,如上文参照图2A所论述。所述工艺还可包括形成第二金属化层128b,如上文参照图2H-2K所论述。所述工艺然后可任选地包括在第二金属化层128b上沉积第二障壁154。
如图4B中所显示,所述工艺可包括在第二障壁154上形成第四电介质166和在第四电介质166上沉积光致抗蚀剂190。然后可对光致抗蚀剂190实施图案化以形成对应于一部分第二金属化层128b和穿透衬底互连110(未显示)的开口192。因此,使一部分第四电介质166和下伏第二障壁154暴露于开口192(下文称为暴露部分194)中。
如中图4C所显示,所述工艺可包括在半导体衬底106中形成互连孔140和去除暴露部分194(图4B)。在一个实施例中,可形成互连孔140并可在一个连续操作中使用相移掩模、漏铬掩模(leaky-chromemask)和/或其它适宜技术去除暴露部分194。在另一实施例中,可利用大致对应于互连孔140的第一掩模(未显示)进行蚀刻以形成互连孔140。可利用大致对应于暴露部分194的第二掩模(未显示)去除暴露部分194。在其它实施例中,可经由其它适宜技术去除暴露部分194。
如图4D中所显示,所述工艺可包括在互连孔140中形成孔绝缘体142。在所图解说明实施例中,孔绝缘体142包括位于互连孔140中的第一部分142a和位于互连孔140外的第二部分142b。第二部分142b至少部分重叠并直接接触第二金属化层128b。在其它实施例中,通过使用(例如)在形成孔绝缘体142时所用大致对应于互连孔140的光罩,孔绝缘体142可仅包括第一部分142a。
如图4E中所显示,所述工艺可包括至少部分去除孔绝缘体142的第二部分142b和暴露第二金属化层128b。在一个实施例中,可经由间隔物蚀刻部分去除第二部分142b。因此,第二部分142b的一部分142c仍位于第二金属化层128b上。在其它实施例中,可经由激光烧蚀和/或其它适宜技术部分去除第二部分142b。在其它实施例中,可完全去除第二部分142b。
所述工艺然后可包括在互连孔140中沉积孔障壁144和晶种材料146,如上文参照图2C所论述。然后,所述工艺可包括用第一导电材料152填充互连孔140,和从第四电介质166去除多余的第一导电材料152。
如图4F中所显示,穿透衬底互连110包括位于互连孔140中的垂直区段110a和位于互连孔140外的水平区段110b。水平区段110b向第二金属化层128b横向延伸以使至少一部分水平区段110b直接接触第二金属化层128b的上表面。所述工艺可任选地包括在第四电介质166和穿透衬底互连110上形成第三障壁196。所述工艺然后可包括如参照图2L-2N所论述形成其它金属化层和实施后续处理以产生图4E中所显示的半导体晶粒102。
依据前文所述,应了解,本文已出于图解说明目的阐述了本技术的特定实施例,但可在不背离本技术的情况下作出各种修改。除其它实施例的元件以外或替代所述元件,一个实施例的许多元件可与其它实施例组合。因此,本技术仅受随附权利要求限制。
Claims (29)
1.一种半导体装置,其包含:
半导体衬底;
第一金属化层和第二金属化层,所述第二金属化层与所述半导体衬底间隔开,其中所述第一金属化层位于其间;和
导电互连,其至少部分延伸穿透所述半导体衬底,其中所述第二金属化层包括对应于所述导电互连的第一部分以及从所述第一部分横向延伸的第二部分,且其中所述导电互连包括第一端及与所述第一端相对的第二端,且其中所述导电互连的所述第一端包括横向延伸到所述第二金属化层的所述第一部分的横向部分,且其中所述导电互连的所述第一端电耦合到所述第二金属化层的所述第一部分且与所述第二金属化层的所述第一部分直接接触;且
其中所述第一金属化层经由所述第二金属化层与所述导电互连电接触。
2.根据权利要求1所述的半导体装置,其中:
所述半导体衬底包括第一侧和第二侧;
所述半导体装置还包括:
绝缘体,其位于所述半导体衬底的所述第一侧与所述第一金属化层之间;
集成电路,其位于所述半导体衬底之上或其中;
导电链路,其至少部分位于所述绝缘体中,所述导电链路位于所述集成电路与所述第一金属化层之间;
电介质,其位于所述第一金属化层与所述第二金属化层之间;且
所述电介质包括直接位于所述第一金属化层与所述第二金属化层的所述第二部分之间的导电导通孔;和
焊料球,其在所述半导体衬底的所述第二侧附接到所述导电互连的所述第二端。
3.根据权利要求1所述的半导体装置,其中:
所述半导体衬底包括第一侧和第二侧;
所述半导体装置还包括:
绝缘体,其位于所述半导体衬底的所述第一侧与所述第一金属化层之间;
集成电路,其位于所述半导体衬底之上或其中;
导电链路,其至少部分位于所述绝缘体中,所述导电链路于所述集成电路与所述第一金属化层之间延伸;和
电介质,其位于所述第一金属化层与所述第二金属化层之间;
所述电介质包括第一导电导通孔和与所述第一导电导通孔间隔开的第二导电导通孔,所述第一导电导通孔直接位于所述第一金属化层与所述第二金属化层的所述第二部分之间,所述第二导电导通孔直接位于所述第二金属化层的所述第一部分与所述导电互连的所述第一端之间;和
焊料球,其在所述半导体衬底的所述第二侧附接到所述导电互连的所述第二端。
4.根据权利要求1所述的半导体装置,其中:
所述半导体衬底包括第一侧和第二侧;
所述第二金属化层包括第一金属化表面和与其相对的第二金属化表面;且
所述半导体装置还包括:
绝缘体,其位于所述半导体衬底的所述第一侧与所述第一金属化层之间;
集成电路,其位于所述半导体衬底之上或其中;
导电链路,其至少部分位于所述绝缘体中,所述导电链路位于所述集成电路与所述第一金属化层之间;
电介质,其位于所述第一金属化层与所述第二金属化层之间;且
所述电介质包括直接位于所述第一金属化层与所述第二金属化层之间的导电导通孔;
所述导电互连包括:
孔,其至少部分于所述半导体衬底的所述第一侧与所述第二侧之间延伸;
位于所述孔中的导电材料的第一区段;
位于所述孔外部的所述导电材料的第二区段;
所述导电材料的所述第二区段在所述第一区段上横向延伸;且
所述第二区段与所述第二金属化层的所述第二金属化表面的至少一部分直接接触;和
焊料球,其在所述半导体衬底的所述第二侧附接到所述导电互连的所述第二端。
5.根据权利要求1所述的半导体装置,其中:
所述半导体装置还包括在所述第一金属化层与所述第二金属化层之间的电介质,所述电介质具有至少靠近所述第一金属化层的第一表面以及至少靠近所述第二金属化层的第二表面;且
所述导电互连的所述第一端与所述电介质的所述第二表面成平面,所述第二端与所述第一端相对。
6.根据权利要求1所述的半导体装置,其中:
所述半导体装置还包括在所述第一金属化层与所述第二金属化层之间的电介质,所述电介质具有与所述第一金属化层直接接触的第一表面和与所述第二金属化层的所述第二部分直接接触的第二表面。
7.根据权利要求1所述的半导体装置,其中:
所述第一金属化层包括靠近所述半导体衬底的第一金属化表面和与所述第一金属化表面相对的第二金属化表面;且
所述导电互连包括第一端和第二端,所述导电互连的所述第一端与所述第一金属化层的所述第二金属化表面齐平,所述第二端与所述第一端相对。
8.根据权利要求1所述的半导体装置,其中:
所述半导体装置还包括在所述第一金属化层与所述第二金属化层之间的电介质,所述电介质具有与所述第一金属化层直接接触的第一表面和与所述第一表面相对的第二表面,所述第二表面与所述第二金属化层直接接触;
所述电介质包括第一导电导通孔和与所述第一导电导通孔间隔开的第二导电导通孔;
所述第一导电导通孔直接位于所述第一金属化层与所述第二金属化层之间;且
所述第二导电导通孔直接位于所述第二金属化层与所述导电互连之间。
9.根据权利要求1所述的半导体装置,其中所述导电互连包括:
孔,其至少部分于所述半导体衬底中延伸;
在所述孔中的导电材料的第一区段;
在所述孔外部的所述导电材料的第二区段;且
所述导电材料的所述第二区段从所述孔横向延伸且与所述第二金属化层直接接触。
10.一种半导体装置,其包含:
半导体衬底;
所述半导体衬底所携载的多个金属路由层,所述多个金属路由层包括N个金属路由层,其中N为大于3的正整数,其中所述多个金属路由层包括第一金属路由层和第二金属路由层;和
导电互连,其至少部分延伸穿透所述半导体衬底,其中所述第二金属路由层包括对应于所述导电互连的第一部分以及从所述第一部分横向延伸的第二部分,且其中所述导电互连包括第一端及与所述第一端相对的第二端,且其中所述导电互连的所述第一端包括横向延伸到所述第二金属路由层的所述第一部分的横向部分,且其中所述导电互连的所述第一端电耦合到所述第二金属路由层的所述第一部分且与所述第二金属路由层的所述第一部分直接接触;
其中所述导电互连的所述第一端延伸超过至少所述第一金属路由层。
11.根据权利要求10所述的半导体装置,其中所述导电互连的所述第一端延伸超过第二金属路由层。
12.根据权利要求10所述的半导体装置,其中:
所述第二金属路由层将所述第一金属路由层电连接到所述导电互连。
13.根据权利要求10所述的半导体装置,其中
所述半导体装置包括在所述第一金属化层与所述第二金属化层之间的电介质,所述电介质具有与所述第一金属化层直接接触的第一表面和与所述第二金属化层的所述第二部分直接接触的第二表面。
14.根据权利要求10所述的半导体装置,其中所述半导体衬底包括第一侧、第二侧以及开口,所述开口至少部分地在所述第一侧和所述第二侧之间延伸。
15.根据权利要求14所述的半导体装置,其中所述导电互连包括在所述开口内部的垂直部分,且其中所述导电互连的横向部分在所述开口的外部。
16.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一金属化层;
在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔,以形成至少部分地穿透所述半导体衬底而延伸的导电互连,其中所述导电互连包括第一端及与所述第一端相对的第二端,其中所述导电互连的所述第一端包括横向部分;和
在所述第一金属化层上形成第二金属化层,所述第二金属化层与所述互连孔中的所述导电材料电接触,其中所述第二金属化层包括对应于所述导电互连的第一部分以及从所述第一部分横向延伸的第二部分,且其中所述导电互连的所述横向部分横向延伸到所述第二金属化层的所述第一部分,且其中所述导电互连的所述第一端电耦合到所述第二金属化层的所述第一部分且与所述第二金属化层的所述第一部分直接接触。
17.根据权利要求16所述的方法,其中:
所述导电材料是第一导电材料;且
形成第二金属化层包括:
在所述互连孔中的所述导电材料上沉积电介质;
在所述电介质中形成凹陷,所述凹陷暴露所述互连孔中的所述导电材料的至少一部分;和
用第二导电材料填充所述凹陷,所述第二导电材料具有与所述互连孔中的所述第一导电材料直接接触的第一部分和从所述第一部分横向延伸的第二部分。
18.根据权利要求16所述的方法,其中:
所述导电材料是第一导电材料;且
形成第二金属化层包括:
在所述第一金属化层和所述互连孔中的所述第一导电材料上沉积电介质;
在所述电介质中形成第一导通孔和第二导通孔,所述第一导通孔暴露所述第一金属化层的至少一部分,所述第二导通孔暴露所述互连孔中的所述第一导电材料的至少一部分;和
用第二导电材料填充所述第一导通孔和所述第二导通孔。
19.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一金属化层;
在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔;及
在所述第一金属化层上形成第二金属化层,所述第二金属化层与所述互连孔中的所述导电材料电接触;其中
形成互连孔包括:
在所述第一金属化层上沉积第一电介质;
对所述第一电介质实施图案化并形成对应于所述互连孔的开口;和
经由所述开口蚀刻所述第一电介质和所述半导体衬底;
填充所述互连孔包括:
将第一导电材料引入所述互连孔中;和
去除所述互连孔外部过多的第一导电材料;且
形成第二金属化层包括:
在所述第一电介质和所述互连孔中的所述导电材料上沉积第二电介质;
基于所述第二金属化层的期望轮廓对所述经沉积第二电介质实施图案化;和
在所述图案化第二电介质中形成导通孔和凹陷,所述导通孔暴露所述第一金属化层的至少一部分,所述凹陷暴露所述互连孔中的所述第一导电材料的至少一部分;和
用第二导电材料填充所述导通孔和所述凹陷,所述第二导电材料具有与所述互连孔中的所述第一导电材料直接接触的第一部分和所述导通孔中与所述第一金属化层直接接触的第二部分。
20.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一金属化层;
在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔;及
在所述第一金属化层上形成第二金属化层,所述第二金属化层与所述互连孔中的所述导电材料电接触;其中
形成互连孔包括:
对具有所述第一金属化层的所述半导体衬底实施图案化并形成对应于所述互连孔的开口;和
经由所述开口蚀刻所述半导体衬底;
填充所述互连孔包括:
将第一导电材料引入所述互连孔中;和
去除所述互连孔外部过多的第一导电材料;且
形成第二金属化层包括:
在所述第一金属化层和所述互连孔中的所述第一导电材料上沉积第一电介质;
在所述第一电介质中形成第一导通孔和第二导通孔,所述第一导通孔暴露所述第一金属化层的至少一部分,所述第二导通孔暴露所述互连孔中的所述第一导电材料的至少一部分;
在所述第一电介质上沉积第二电介质;
基于所述第二金属化层的期望轮廓对所述经沉积第二电介质实施图案化;
在所述图案化第二电介质中形成凹陷,所述凹陷对应于所述第二金属化层的所述期望轮廓;和
用第二导电材料填充所述第一导通孔和所述第二导通孔和所述凹陷。
21.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一金属化层;
在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔;及
在所述第一金属化层上形成第二金属化层,所述第二金属化层与所述互连孔中的所述导电材料电接触;其中:
形成第二金属化层包括:
在所述第一金属化层上沉积第一电介质;
基于所述第二金属化层的期望轮廓对所述第一电介质实施图案化;
在所述第一电介质中形成导通孔和凹陷,所述凹陷对应于所述第二金属化层的所述期望轮廓;和
用第一导电材料填充所述导通孔和所述凹陷;且
形成互连孔包括:
在所述第二金属化层和所述第一电介质上沉积第二电介质;
对所述第二电介质实施图案化并形成对应于所述互连孔和所述第二金属化层的至少一部分的开口;
经由所述开口蚀刻所述第一电介质和所述第二电介质和所述半导体衬底;
在所述互连孔中和在所述第二金属化层上沉积绝缘材料;
去除所述第二金属化层上的所述绝缘材料的至少一部分;和
经由所述开口用第二导电材料填充所述互连孔,所述第二导电材料的至少一部分与所述第二金属化层直接接触。
22.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一金属化层;
在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔;及
在所述第一金属化层上形成第二金属化层,所述第二金属化层与所述互连孔中的所述导电材料电接触;其中:
所述导电材料是第一导电材料;且
形成互连孔包括:
在所述第二金属化层上沉积电介质;
形成穿透所述电介质和所述半导体衬底的所述互连孔;
暴露所述第二金属化层的至少一部分;和
在所述互连孔中和在所述第二金属化层的所述暴露部分上沉积第二导电材料。
23.一种制作半导体装置的方法,其包含:
在半导体衬底上形成第一、第二、......和第N个金属化层,N是不小于3的正整数;
至少在形成所述第一金属化层后,形成至少部分位于所述半导体衬底中的互连孔;
用导电材料填充所述互连孔,以形成至少部分地穿透所述半导体衬底而延伸的导电互连,所述导电材料与所述金属化层中的至少一者电接触;和
其中在所述第一金属化层上形成第二金属化层,其中所述第二金属化层包括对应于所述导电互连的第一部分以及从所述第一部分横向延伸的第二部分,且其中所述导电互连包括第一端及与所述第一端相对的第二端,且其中所述导电互连的所述第一端包括横向延伸到所述第二金属化层的所述第一部分的横向部分,且其中所述导电互连的所述第一端电耦合到所述第二金属化层的所述第一部分且与所述第二金属化层的所述第一部分直接接触。
24.根据权利要求23所述的方法,其进一步包含在形成第二金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔。
25.根据权利要求23所述的方法,其中:
形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔;且
形成第一、第二、......和第N个金属化层包括在用所述导电材料填充所述互连孔后,形成第N-1个金属化层。
26.根据权利要求23所述的方法,其中:
形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔;
形成第一、第二、......和第N个金属化层包括在用所述导电材料填充所述互连孔后,形成所述第N-1个金属化层;且
所述方法进一步包括使第N-1个金属化层与所述互连孔中的所述导电材料直接接触。
27.根据权利要求23所述的方法,其中:
形成互连孔包括在形成第N-2个金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔;
形成第一、第二、......和第N个金属化层包括在用所述导电材料填充所述互连孔后,形成所述第N-1个金属化层;且
所述方法进一步包括直接在第N-1个金属化层与所述互连孔中的所述导电材料之间形成导电导通孔。
28.根据权利要求23所述的方法,其中:
形成互连孔包括在形成第N-1个金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔;且
填充所述互连孔包括用所述导电材料填充所述互连孔,其中第一部分与第N-1个金属化层直接接触且第二部分位于所述互连孔中。
29.根据权利要求23所述的方法,其中:
形成互连孔包括在形成第N-1个金属化层后,形成至少部分位于所述半导体衬底中的所述互连孔;
所述方法进一步包括暴露第N-1个金属化层的至少一部分;且
填充所述互连孔包括将所述互连孔引入所述互连孔中和所述第N-1个金属化层的所述暴露部分上。
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WO2011097165A2 (en) | 2011-08-11 |
CN102804370A (zh) | 2012-11-28 |
EP2534682A2 (en) | 2012-12-19 |
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SG183204A1 (en) | 2012-09-27 |
US11527436B2 (en) | 2022-12-13 |
KR101441776B1 (ko) | 2014-09-17 |
US10685878B2 (en) | 2020-06-16 |
US20110193226A1 (en) | 2011-08-11 |
SG10201500898RA (en) | 2015-04-29 |
US20150093892A1 (en) | 2015-04-02 |
WO2011097165A3 (en) | 2011-11-17 |
EP4322215A2 (en) | 2024-02-14 |
SG10201907031QA (en) | 2019-09-27 |
KR20120127487A (ko) | 2012-11-21 |
TW201140783A (en) | 2011-11-16 |
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