SG10201907031QA - Microelectronic devices with through-substrate interconnects and associated methods of manufacturing - Google Patents

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

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Publication number
SG10201907031QA
SG10201907031QA SG10201907031QA SG10201907031QA SG10201907031QA SG 10201907031Q A SG10201907031Q A SG 10201907031QA SG 10201907031Q A SG10201907031Q A SG 10201907031QA SG 10201907031Q A SG10201907031Q A SG 10201907031QA SG 10201907031Q A SG10201907031Q A SG 10201907031QA
Authority
SG
Singapore
Prior art keywords
manufacturing
associated methods
microelectronic devices
metallization layer
substrate interconnects
Prior art date
Application number
SG10201907031QA
Inventor
Kyle Kirby
Kunal Parekh
Sarah Niroumand
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/701,800 priority Critical patent/US8907457B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG10201907031QA publication Critical patent/SG10201907031QA/en

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    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING OF THE TECHNOLOGY Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer. Figure 4F
SG10201907031QA 2010-02-08 2011-01-31 Microelectronic devices with through-substrate interconnects and associated methods of manufacturing SG10201907031QA (en)

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EP2534682A4 (en) 2015-04-08
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KR20120127487A (en) 2012-11-21
SG183204A1 (en) 2012-09-27
KR101441776B1 (en) 2014-09-17
EP2534682A2 (en) 2012-12-19
CN102804370B (en) 2016-02-24
CN102804370A (en) 2012-11-28
US20110193226A1 (en) 2011-08-11
TWI474459B (en) 2015-02-21
US20150093892A1 (en) 2015-04-02
WO2011097165A2 (en) 2011-08-11
WO2011097165A3 (en) 2011-11-17
US8907457B2 (en) 2014-12-09

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