CN102738212B - 边缘端接中产生鞍型结电场的改良型结构及方法 - Google Patents

边缘端接中产生鞍型结电场的改良型结构及方法 Download PDF

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CN102738212B
CN102738212B CN201210086374.0A CN201210086374A CN102738212B CN 102738212 B CN102738212 B CN 102738212B CN 201210086374 A CN201210086374 A CN 201210086374A CN 102738212 B CN102738212 B CN 102738212B
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马督儿·博德
管灵鹏
安荷·叭剌
哈姆扎·耶尔马兹
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明提出了一种设置在半导体衬底中的半导体功率器件，并且具有一个有源晶胞区和一个边缘端接区，其中边缘端接区包括一个具有交替导电类型的掺杂半导体立柱的超级结结构，带有掺杂半导体立柱之间的电荷不平衡，以便在边缘端接中形成一个鞍型结电场。

Description

边缘端接中产生鞍型结电场的改良型结构及方法
技术领域
本发明主要是关于半导体功率器件。更确切的说，本发明是关于半导体功率器件的新型、改良型边缘端接的结构和制备方法，以便产生鞍型结型电场，减少终接区所占的面积，同时保持高击穿电压。
背景技术
进一步提高半导体功率器件在终端区的击穿电压的传统的制备工艺和器件结构，仍然存在端接区所占面积较大等困难。如今制备的半导体功率器件尺寸越来越小，这些困难正变得更加严峻。普遍调查显示，对于较大尺寸的集成电路芯片来说；边缘端接约占总面积的20％。然而，芯片的尺寸越来越小，为了保持高击穿电压，边缘端接所占的百分比逐渐增大，可能会约占总面积的50％左右。由于端接区不用于电流传导，因此它是晶体管的“非有源”区。即使边缘端接所占的大面积，致使有用的有源晶胞区有些浪费，但是在实现减小边缘端接区的同时保持高击穿电压方面，仍然存在很大的困难。
图1A和1B所示的剖面图，表示一个带有平行面击穿电压的理想PN结，以及一个在垂直功率器件的边缘处未端接的PN结，以解释说明为何有必要改进边缘端接。图1A表示在N+衬底上方，P+层和N-层之间的理想PN结。由于掺杂的不同，N-耗尽层103比P+耗尽层101宽得多。忽略边缘效应的话，凭借平行面雪崩击穿，耗尽区中的电场均匀分布。这是在忽略边缘效应时，轻掺杂漂移区特定的掺杂等级和厚度下，击穿电压所能达到的理论极限。然而，在通过植入端接构成P+层的边缘处，由于形成了柱型结，造成电场拥挤，因此反向偏置结实际的击穿电压可以大幅降低，如图1B所示。可见到，耗尽区的形状为凸面，致使结附近的电场拥挤。
为了缓解该问题，提出了许多边缘端接，并且在本行业中广泛应用。其中一些包括图1C所示的浮动保护环90以及图1D所示的电场板92。这些技术通过传导表面处的耗尽区，降低了电场，从而提高了击穿电压。然而，这些技术通常需要很大的植入面积，增加了器件的晶片尺寸。此外，这些技术倾向于来自于钝化薄膜和/或封装成型混料的表面电荷。
因此，仍然需要在功率半导体器件设计和制备领域中，提出边缘端接的新型、改良结构，以解决上述局限和难题。
发明内容
本发明的一个方面在于，提出了一种新型、改良的边缘端接结构，以降低在器件边缘处的阻挡结附近的电场拥挤效应，并且提供带有较小的表面电场的紧凑端接，紧凑端接对表面电荷较不敏感。它的实现，是通过在终接区中制备一个凹型或鞍型结，用N型漂移区代替具有净P型掺杂浓度的半导体区。
具体地说，本发明的一个方面在于，提出了一种新型、改良的半导体功率器件的边缘端接结构，利用P-立柱和N-立柱之间的电荷不平衡的超级结结构，具体来说是P立柱电荷高于N立柱电荷，以便在终接区(Termination region)中产生净P型掺杂，并且产生鞍型结场效应，分布并传导电场的电势线，从而降低电场拥挤，并且不需要很大的终接区，就能大幅提高击穿电压。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件的边缘端接结构，利用超级结结构P-立柱和N-立柱之间的电荷不平衡，通过增大P-立柱的宽度，在终接区中产生净P型掺杂，并且产生鞍型结场效应，分布并传导电场的电势线，从而降低电场拥挤，并且不需要很大的终接区，就能大幅提高击穿电压。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件的边缘端接结构，利用超级结结构P-立柱和N-立柱之间的电荷不平衡，通过改变P-立柱顶部和底部的掺杂浓度，以便使端接更适应立柱电荷的变化，并且产生鞍型结场效应，分布并传导电场的电势线，从而降低电场拥挤，并且不需要很大的终接区，就能大幅提高击穿电压。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件的边缘端接结构，利用超级结结构P-立柱和N-立柱之间的电荷不平衡，通过用P-型外延开始超级结结构，以及一个宽P-型外延带隙设置在P立柱中间，以便产生鞍型结场效应，分布并传导电场的电势线，从而降低电场拥挤，并且不需要很大的终接区，就能大幅提高击穿电压。
本发明的另一个方面在于，提出了一种新型、改良的半导体功率器件的边缘端接结构，利用超级结结构P-立柱和N-立柱之间的电荷不平衡，通过在P-立柱和N-立柱上方，形成可选的表面结端接延伸(JTE)，以降低表面电场，提高它对表面电荷的容限，并且产生鞍型结场效应，分布并传导电场的电势线，从而降低电场拥挤，并且不需要很大的终接区，就能大幅提高击穿电压。
本发明的一个较佳实施例提出了一种设置在半导体衬底中的半导体功率器件，具有一个有源晶胞区(或称为有源单元区)以及一个边缘端接区(Edge termination area)，其中边缘端接区包括一个超级结结构，具有导电类型交替的掺杂半导体立柱，并且掺杂半导体立柱之间的电荷不平衡，以便在边缘端接(Edge termination)中产生鞍型结电场。在一个典型的实施例中，掺杂半导体立柱包括P-立柱和N-立柱，P-立柱的电荷大于N-立柱。在另一个实施例中，P-立柱的掺杂浓度高于N-立柱。在另一个实施例中，P-立柱顶部的电荷浓度高于P-立柱的底部。在另一个实施例中，超级结结构形成在P-型外延层中，P-型外延层具有一个宽P-带隙设置在P立柱之间，从而产生电荷不平衡。在另一个实施例中，超级结还包括一个表面结端接延伸，并且一个掺杂的表面层横向延伸穿过半导体立柱上方，从而在超级结结构中产生电荷不平衡。
阅读以下详细说明并参照附图之后，本发明的这些和其他的特点和优势，对于本领域的技术人员而言，无疑将会是显而易见的。
附图说明
图1A所示的剖面图，表示可以获得最大击穿电压的理想的平行面结结构。
图1B表示在器件边缘处的未端接P-N结的剖面图，在器件边缘处构成一个柱型结，造成电场拥挤，并且端接击穿电压大幅降低。
图1C表示利用浮动场环的边缘端接技术的剖面图，浮动场环是由多个在器件表面的P型区的岛组成的。
图1D表示利用电场板的边缘端接技术的剖面图，电场板是由一个或多个连接到源极/保护环的电极组成的，用于传导电场。
图2所示的剖面图，用于解释说明鞍型结结构，利用具有只掺杂轻掺杂P型的漂移区，产生凹形耗尽区，导致电场的电势线向外发散延伸，从而提高半导体功率器件的终接区中的击穿电压。
图3至6所示的剖面图，表示半导体功率器件的改良型边缘端接结构，利用具有在P-立柱和N-立柱之间的不平衡电荷的超级结结构，以产生鞍型结型电场，从而提高边缘端接的击穿电压。
图7A-7H所示的剖面图，表示用于制备图3和图4所示类型的超级结结构的工艺。
图8A-8E所示的剖面图，表示用于制备图5所示类型的超级结结构的工艺。
图9A-9D所示的剖面图，表示用于制备图3和图4所示类型的超级结结构的一种可选工艺。
具体实施方式
为了更好地理解本发明，图2提出了一种带有鞍型结结构的边缘端接(Edgetermination，或称为边缘终端或边缘终结)结构。根据定义，当P区扩散到N型半导体区域内时，就会产生一个结。鞍型结与柱型结的曲率相反，从而改善了电场拥挤，并提高了击穿电压。与图1B所示的柱型结相比，轻掺杂的N型区用轻掺杂的P型区107代替，在轻掺杂的P型区107和重掺杂的N型边缘区104之间形成一个结，并且衬底105包围着具有耗尽区106的轻掺杂P型区107。重掺杂的P+区115用于避免穿通击穿。该鞍型结结构将峰值电场转移到下方N+衬底，并且产生负电荷柱型结，传导表面附近的电场。如图2所示的鞍型结结构大幅降低了电场拥挤效应，从而提高了终接区中的击穿电压。由于不存在浮动场环等端接中出现的任何零场区，因此这样也会使终接区更加紧凑。
图3所示的剖面图，表示边缘端接结构120，带有在P-立柱和N-立柱之间的电荷不平衡的超级结结构，确切地说依据本发明的一个实施例，P立柱电荷高于N立柱电荷。超级结结构含有位于N-型半导体衬底105上的交替的N和P立柱，P+区115设置在器件的有源区边缘的顶部(图中没有表示出)。超级结结构包括多个掺杂立柱140-N和140-P，它们分别是交替的N-型和P-型。根据定义，电荷与掺杂浓度、宽度或面积成正比。为了在终接区中产生净P型掺杂(Net P-type doping)，即P立柱电荷高于N立柱电荷，要调节掺杂浓度或立柱宽度或两者皆有，才能产生所需的净电荷。对于晶胞间距(或称为单元间距)为8微米的情况，P-立柱140-P具有较宽的间距，例如6微米，N-立柱140-N具有较窄的间距，例如在终接区内仅2微米，而它们都有大致相同的掺杂等级。N-型和P-型导电类型交替的超级结结构，是通过一个充分重掺杂的N-立柱端接的，以构成鞍型结。这使得端接漂移区具有净P型掺杂，并且在端接边缘中产生鞍型结。就其本身而言，可以获得较高的击穿电压，例如600伏以上的击穿电压，并且不需要增加传统的端接结构，例如浮动保护环/场板以及表面结端接延伸(Surface junction terminationextensions，简称JTE)。还可选择，N-立柱和P-立柱的宽度相等，调节掺杂等级，在终接区中产生净P电荷，以便形成鞍型结。
尽管，较高的P立柱电荷会影响器件的垂直击穿电压，也就是说，在垂直击穿电压和端接击穿电压之间存在取舍关系。可以通过改变P立柱中的掺杂浓度，来优化这种取舍关系。图4表示本发明的另一个实施例的剖面图，其中边缘端接的超级结结构与图3所示器件的超级结结构类似，只是P-立柱140-P的掺杂浓度可变，即顶部的掺杂浓度较高，底部的掺杂浓度较低。P-掺杂立柱140-P的上半部分增加10％的掺杂浓度，即比2.4e12/cm2高10％，P-掺杂立柱的下半部分减小10％的掺杂浓度，即比2.4e12/cm2低10％。由于图3所示器件的P-掺杂立柱中的P掺杂浓度为常数，因此可以获得比图3所示器件的击穿电压更高的击穿电压。P-掺杂立柱140-P的可变P-掺杂浓度，增大了11％左右的Q-不平衡窗，从而更加适应工艺的变化。凭借上述终接区处的超级结结构，鞍型结的耗尽宽度扩展至60微米左右，形成一个比保护环或场板端接更加紧凑的边缘端接。P-立柱的掺杂浓度可以根据工艺结构或能级结构调节。
图5表示本发明所述的改良型边缘端接的一个可选实施例的剖面图。边缘端接从P-型外延层110-P开始。超级结结构包括一个宽度大约为50微米的P-型外延带隙140-P’，设置在交替的N-立柱140-N和P立柱140-P中的一个P立柱内。产生40％Q的电荷不平衡窗以及良好的击穿电压，例如可以获得650伏以上的击穿电压。在本实施例中，也可以通过植入P-分级的掺杂结构植入P-外延层110-P，用于UIS设计。通过两个或多个步骤的P型外延层的外延生长，可以实现掺杂分级，即P型掺杂浓度从底部到顶部不断增大。在本实施例中，鞍型结的耗尽宽度延伸至70微米，产生一个比保护环或场板端接更加紧凑的边缘端接。
图6所示的剖面图，表示本发明所述的半导体功率器件的改良型边缘端接的另一个实施例。与图3所示的边缘端接类似，该边缘端接所具有的超级结结构，带有一个交替N-型和P-型活性的掺杂外延立柱140-N和140-P。P-型和N-型表面结端接延伸(JTE)150-P和150-N分别形成在超级结结构的掺杂立柱上方。P-型和N-型JTE 150-P和150-N通过修正电场形状，降低了表面电场。它们还可以用于使端接更加适应钝化薄膜和封装成型混料的变化。作为一个实施例，带有不同立柱宽度的P-型和N-型JTE 150-P和150-N也可以用于获得同样的效果，例如加宽P-型立柱，可提高击穿电压。还可选择，在如图4所示的带有可变P立柱掺杂的超级结结构中，植入P-型和N-型JTE 150-P和150-N，其中JTE 150-P和150-N设置在超级结结构的掺杂立柱上方。此外，在如图5所示的带有P-型外延带隙的超级结结构中，植入P-型和N-型JTE 150-P和150-N，其中JTE 150-P和150-N设置在带隙的上方。
图7A-7H表示一种用于制备图3和图4所示类型的鞍型结边缘端接的方法。如图7A所示，该工艺以重掺杂的N型衬底702开始。如图7B所示，在衬底702上生长一个N型外延层704。光致抗蚀剂掩膜706设置在N-外延层704上方，用于深植入。如图7C所示，在N型外延层的裸露区域处，进行P型掺杂物708的深植入，以便形成掩埋的P型层710。然后如图7D所示，除去光致抗蚀剂掩膜706，生长N型外延层712。重复进行图7C和图7D所示的工艺，生长N型外延层和带掩膜的植入，直到对于鞍型结边缘端接来说，超级结结构的P-立柱达到预设的全长，掩埋的P型层垂直分离一段预设的距离，这段距离很大，足以在掩埋的P型层710扩散之后，形成一个P型立柱。作为示例，如图7E所示，在N型外延层712中，形成六个掩埋的P型层710。然后，对掩埋的P型层进行热扩散，并将其合并，构成一个全长P-立柱714，在N型外延层712内，如图7F所示，仅表示出了P-立柱的一半。
图7G表示一种含有多个P-立柱714形成在N型外延层712内的半导体器件。用相同的掺杂结构或相同的掺杂浓度，掺杂有源区和终接区中的P-立柱714。在整个有源区和终接区，用相同的掺杂结构掺杂N型外延层712。掺杂有源区中的P-立柱并分隔开，使P-立柱中的电荷与P-立柱之间的N型外延层基本平衡。如上所述，为了在终接区上获得净轻P掺杂漂移区，减少终接区上P-立柱之间的空间，使N-立柱的宽度，从有源区(Active area)中的WNcol，A，减少到终接区(Termination area)中的WNcol，T。因此，如图7H所示，N-立柱713在有源区中的宽度大于N-型立柱715在终接区中的宽度。还可选择，为了在终接区上获得净轻P掺杂漂移区，通过增大终接区中用于P-立柱植入的裸露面积的宽度，可以增加P-立柱的宽度。还可选择，采用在终接区中增大P-立柱宽度并减小N-立柱宽度，以便在终接区中获得轻P掺杂漂移区。如图7H所示，终接区中P立柱716的宽度大于有源区中P立柱714的宽度，然而同时减小N-立柱宽度，以保持相同的间距。此外，如图3和图4所示的穿通阻挡P+掺杂区115，可以在后续工艺中单独制备，或者最好是在制备有源区中的P本体区或超级结晶体管晶胞的P+接触植入区(图中没有表示出)的同时制备。理想情况下，有源区中的P-立柱电连接到有源晶体管的P本体区，而终接区中的P-立柱是浮动的。所形成的图6所示的P-型和N-型表面结端接延伸(JTE)150-P和150-N，也可以穿过带掩埋的植入物。
图8A-8E表示的是一种用于制备图5所示类型的鞍型结边缘端接的可选方法。该工艺从重掺杂的N型衬底802开始，在衬底802的顶部有一个不变的或分级的P型外延层804。在衬底上进行深沟槽刻蚀，刻蚀终点在P型外延层底面下方凹陷，构成深沟槽805，图8B表示深沟槽805的一半。沟槽805最好含有倾斜侧壁。在沟槽805的侧壁上带角度地交替植入N型和P型掺杂物806，以构成交替的P立柱808、812以及N立柱810，如图8C所示。然后，如图8D所示，在沟槽805中填充本征或轻掺杂的P型或N型材料814。如上所述，在沟槽805之间设置宽度大约为50微米的带隙，将在终接区中获得净轻P掺杂漂移区，产生40％Q的电荷不平衡窗以及更好的击穿电压，如图8E所示。在本图中，N缓冲层802-1可以选择设置在衬底802和P-外延层804之间。此外，如图5所示的穿通阻挡P+掺杂区115，可以在后续工艺中单独制备，或者最好是在制备有源区中的P本体区或超级结晶体管晶胞的P+接触植入区(图中没有表示出)的同时制备。理想情况下，有源区中的P-立柱电连接到有源晶体管的P本体区，而终接区中的P-立柱是浮动的。所形成的图6所示的P-型和N-型表面结端接延伸(JTE)150-P和150-N，也可以通过掩膜来进行掺杂物的植入而制备。
在另一个实施方式中，参见图9A-9D，展示了图3所体现出的这种类型的鞍型结边缘端接的一种优选制备方法。在该制备工艺中，先行提供一重掺杂的N型衬底902，并在衬底902的顶部生长一个掺杂浓度恒定或掺杂浓度分级的P型外延层904。随之在衬底上进行深沟槽刻蚀工艺，其刻蚀终点可以延伸至位于P型外延层904底面的下方(例如凹陷至下方的衬底902中)，从而形成深沟槽905，图9B的示意图表示深沟槽905的一半。可选的，该深沟槽905最好带有倾斜侧壁。之后如图9C所示，将P型外延材料906填充在沟槽905中。类似于前述的方法，为了在终接区上获得P型重掺杂的漂移区，P-立柱的宽度就必须大于N-立柱的宽度，而减小对N外延层902实施刻蚀而产生的台面结构的台面宽度就可以实现这一点，换言之，也即减小位于终接区的相邻的沟槽905之间的间隔距离。其结果正如图9D所示，位于有源区的台面结构的台面宽度值WMESAA大于位于终接区的台面结构的台面宽度值WMESAT。此外，图3所展示的穿通阻挡P+掺杂区115，既可以在后续工艺中单独制备，也可以在制备有源区中的P本体区或超级结晶体管单元的P+接触植入区(未示意出)时一并同时制备。理想状态下，有源区中的P-立柱可以电连接到有源晶体管的P本体区，而终接区中的P-立柱则可以是浮动的。图6所示的P-型和N-型表面结端接延伸(JTE)结构150-P和150-N，也可以利用图中未示意出的掩膜来植入掺杂物而获得。
尽管本发明已经详细说明了现有的较佳实施例，但应理解这些说明不应作为本发明的局限。本领域的技术人员阅读上述详细说明后，各种变化和修正无疑将显而易见。因此，应认为所附的权利要求书涵盖本发明的真实意图和范围内的全部变化和修正。

Claims (18)

1.一种设置在半导体衬底中，并且具有一个有源晶胞区和一个边缘端接区的半导体器件，其特征在于，边缘端接区包括一个具有掺杂交替导电类型的半导体立柱的超级结结构，带有掺杂的半导体立柱之间的电荷不平衡，以便在终接区中产生净P型掺杂，并且在边缘端接中制成一个鞍型结电场；
掺杂的半导体立柱包括P-立柱和N-立柱，超级结结构形成在P-型外延层中，并且具有一个很宽的P-带隙设置在P-立柱的中心。
2.如权利要求1所述的半导体器件，其特征在于，掺杂的半导体立柱包括P-立柱和N-立柱，并且P-立柱比N-立柱的电荷多。
3.如权利要求1所述的半导体器件，其特征在于，掺杂的半导体立柱包括P-立柱和N-立柱，并且P-立柱比N-立柱的宽度大。
4.如权利要求1所述的半导体器件，其特征在于，掺杂的半导体立柱包括P-立柱和N-立柱，并且P-立柱比N-立柱的掺杂浓度大。
5.如权利要求1所述的半导体器件，其特征在于，掺杂的半导体立柱包括P-立柱和N-立柱，并且其中P-立柱顶部的掺杂浓度高于底部的掺杂浓度。
6.如权利要求1所述的半导体器件，其特征在于，超级结结构还包括一个表面结端接延伸，带有一个掺杂的表面层，横向延伸穿过半导体立柱上方。
7.如权利要求1所述的半导体器件，其特征在于，掺杂的半导体立柱包括P-立柱和N-立柱，P-立柱具有的电荷从1e12至3e12，多于N-立柱从1e12至2e12的电荷。
8.如权利要求3所述的半导体器件，其特征在于，P-立柱、N-立柱的宽度范围均为2um至10um，P-立柱的宽度大于N-立柱的宽度。
9.如权利要求5所述的半导体器件，其特征在于，P-立柱顶部的立柱电荷比P-立柱底部的立柱电荷高0至50％。
10.如权利要求1所述的半导体器件，其特征在于，超级结结构形成在P-型外延层中，加宽的P-带隙范围为20um至80um，从而产生了电荷不平衡。
11.如权利要求1所述的半导体器件，其特征在于，超级结结构还包括一个表面结端接延伸，带有一个掺杂的表面层，横向延伸穿过半导体立柱上方，延伸距离的范围为20um至80um微米，从有源晶胞区的外边缘开始，以便在超级结结构中产生电荷不平衡。
12.如权利要求1所述的半导体器件，其特征在于，边缘端接区的宽度范围为50微米至200微米，带有交替导电类型的掺杂半导体立柱的超级结结构，在边缘端接中延伸并且其宽度范围为50微米至200微米。
13.一种用于在带有一个有源晶胞区和一个边缘端接区的半导体衬底中制备功率器件的方法，其特征在于，包括：在边缘端接区中，制备交替导电类型的掺杂半导体立柱，并且在掺杂半导体立柱中间，制备带有电荷不平衡的掺杂半导体立柱，以便在终接区中产生净P型掺杂，用于在边缘端接中形成鞍型结电场；
制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过在位于所述的半导体衬底上的N-型外延层中打通多个带有稍稍倾斜侧壁的沟槽，并且被打通的所述沟槽之间带有预定义的带隙，然后穿过侧壁，植入交替导电类型的离子，并用本征材料或者轻掺杂材料填充沟槽，以便在终接区中产生净P型掺杂。
14.如权利要求13所述的方法，其特征在于，制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过制备P-立柱的电荷大于N-立柱。
15.如权利要求13所述的方法，其特征在于，制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过制备P-立柱的宽度大于N-立柱。
16.如权利要求13所述的方法，其特征在于，制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过制备P-立柱的掺杂浓度大于N-立柱。
17.如权利要求13所述的方法，其特征在于，制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过制备P-立柱顶部的掺杂浓度大于P-立柱底部的掺杂浓度，并且大于N-立柱。
18.一种用于在带有一个有源晶胞区和一个边缘端接区的半导体衬底中制备功率器件的方法，其特征在于，包括：在边缘端接区中，制备交替导电类型的掺杂半导体立柱，并且在掺杂半导体立柱中间，制备带有电荷不平衡的掺杂半导体立柱，以便在终接区中产生净P型掺杂，用于在边缘端接中形成鞍型结电场；
制备所述的掺杂半导体立柱的步骤，还包括形成P-立柱和N-立柱，通过在位于所述的半导体衬底上的N-型外延层中打通多个带有稍稍倾斜侧壁的沟槽，沟槽凹陷至N-型外延层下方的衬底中，然后用P型外延掺杂材料填充沟槽，以便在终接区中产生净P型掺杂。
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