CN108269734A - 深沟槽外延填充方法 - Google Patents

深沟槽外延填充方法 Download PDF

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CN108269734A
CN108269734A CN201810120741.1A CN201810120741A CN108269734A CN 108269734 A CN108269734 A CN 108269734A CN 201810120741 A CN201810120741 A CN 201810120741A CN 108269734 A CN108269734 A CN 108269734A
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伍洲
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本发明公开了一种深沟槽外延填充方法，在对深沟槽进行外延填充时，在晶圆边缘的留边区域，同样刻蚀与晶圆中心区域相同的深沟槽，所述的留边区域，是在晶圆边缘留出的，具有一定宽度的不制作任何器件及结构的空白区域。本发明所述的深沟槽外延填充方法，通过在晶圆留边区域设置与中心区域相同的深沟槽，协助消耗晶圆边缘的反应气体，降低边缘区域的填充速率，使晶圆获得较好的面内填充均一性。

Description

深沟槽外延填充方法
技术领域
本发明涉及半导体制造领域，特别是指一种超级结器件工艺中的深沟槽外延填充方法。
背景技术
在超级结项目中，四代工艺在三代基础上，深沟槽由原来的88.6度优化至90度，pitch(原胞尺寸)由原来的4:5缩小至2:3，沟槽CD面内范围也明显减小，器件性能因此得到显著提升。但另一方面，沟槽形貌及尺寸的优化将在很大程度上增加了外延填充的难度。
由于受loading effect(载入效应)及EPI chamber(外延工艺腔)结构的影响，晶圆边缘到EE5mm范围内的沟槽填充速率快，中间位置较慢，从而导致边缘位置沟槽填满，而中间位置仍存在较深“V”型口，面内均一性不好。如图1所示。沟槽形貌优化后，该问题表现得更加明显，边缘与中间位置沟槽填充速率的差异更大。若单纯增加填充时间，可将中间位置沟槽填满，但边缘由于硅生长过厚会产生缺陷，而外延缺陷会直接影响器件性能，图2中所示，上面两图是在保证边缘位置刚好填充满时中心区域的沟槽还未填满，存在V型口(图2上左)，而在保证中心区域的沟槽完全填满时，边缘区域的深沟槽填充过厚并引起一些缺陷(图2下右)。在原来的沟槽刻蚀过程中，光刻和刻蚀均会留3mm去边，在这距边3mm位置，没有沟槽。外延填充时，工艺气体充满整个chamber，chamber边缘位置的气体很大一部分参与晶圆wafer边缘位置的沟槽填充，致使边缘位置沟槽填充速率较中间位置更快。
发明内容
本发明所要解决的技术问题在于提供一种深沟槽外延填充方法，提高晶圆的面内外延填充均一性。
为解决上述问题，本发明所述的深沟槽外延填充方法，是在对深沟槽进行外延填充时，在晶圆边缘的留边区域，同样刻蚀与晶圆中心区域器件相同的深沟槽。
进一步地，所述的留边区域，是在晶圆边缘留出的，具有一定宽度的空白区域。
进一步地，所述的留边区域，不形成任何器件。
进一步地，所述的留边区域的深沟槽，在外延填充时，能协助消耗处于晶圆边缘区域的反应气体，降低晶圆边缘正常器件区域的深沟槽填充速率。
进一步地，在外延填充时，晶圆边缘区域的填充速率高于中心区域于晶圆边缘，留边区域的深沟槽能消耗反应气体，平衡整个晶圆各区域的深沟槽填充速率，保证各区域的深沟槽填充效果，提高深沟槽填充的面内均一性。
本发明所述的深沟槽外延填充方法，通过在晶圆留边区域设置与中心区域相同的深沟槽，协助消耗晶圆边缘的反应气体，降低边缘区域的填充速率，使晶圆获得较好的面内填充均一性。
附图说明
图1是晶圆在外延工艺反应腔室内的状态示意图，传统工艺中晶圆边缘留有空白的去边区域。
图2是晶圆上边缘区域与中心区域的深沟槽在不同条件下填充的示意图。
图3是本发明对晶圆的去边区域同样进行深沟槽刻蚀的示意图，图中的最外缘的去边区域具有与中心区域相同的深沟槽。
图4是本发明晶圆的深沟槽外延填充示意图。
具体实施方式
本发明所述的深沟槽外延填充方法，是在对深沟槽进行外延填充时，在晶圆边缘的留边区域，同样刻蚀与晶圆中心区域器件相同的深沟槽。
所述的留边区域的深沟槽，在外延填充时，能协助消耗处于晶圆边缘区域的反应气体，降低晶圆边缘正常器件区域的深沟槽填充速率。在外延填充时，晶圆边缘区域的填充速率高于中心区域于晶圆边缘，留边区域的深沟槽能消耗反应气体，使参与晶圆边缘有效管芯区域沟槽填充的气体减少，降低边缘区域填充速率，平衡整个晶圆各区域的深沟槽填充速率，保证各区域的深沟槽填充效果，提高深沟槽填充的面内均一性。
以上仅为本发明的优选实施例，并不用于限定本发明。对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (5)

1.一种深沟槽外延填充方法，其特征在于：在对深沟槽进行外延填充时，在晶圆边缘的留边区域，同样刻蚀与晶圆中心区域器件相同的深沟槽。
2.如权利要求1所述的深沟槽外延填充方法，其特征在于：所述的留边区域，是在晶圆边缘留出的，具有一定宽度的空白区域。
3.如权利要求2所述的深沟槽外延填充方法，其特征在于：所述的留边区域，不形成任何器件。
4.如权利要求1所述的深沟槽外延填充方法，其特征在于：所述的留边区域的深沟槽，在外延填充时，能协助消耗处于晶圆边缘区域的反应气体，降低晶圆边缘正常器件区域的深沟槽填充速率。
5.如权利要求4所述的深沟槽外延填充方法，其特征在于：在外延填充时，晶圆边缘区域的填充速率高于中心区域，留边区域的深沟槽能消耗反应气体，平衡整个晶圆各区域的深沟槽填充速率，保证各区域的深沟槽填充效果，提高深沟槽填充的面内均一性。
CN201810120741.1A 2018-02-07 2018-02-07 深沟槽外延填充方法 Pending CN108269734A (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420125A (zh) * 2011-06-07 2012-04-18 上海华力微电子有限公司 一种深沟槽氧化物刻蚀改进工艺
CN102738212A (zh) * 2011-03-29 2012-10-17 万国半导体股份有限公司 边缘端接中产生鞍型结电场的改良型结构及方法
CN105702709A (zh) * 2016-01-29 2016-06-22 上海华虹宏力半导体制造有限公司 沟槽型超级结的制造方法
CN105702710A (zh) * 2016-01-29 2016-06-22 上海华虹宏力半导体制造有限公司 深沟槽型超级结器件的制造方法
CN107275389A (zh) * 2017-06-30 2017-10-20 上海华虹宏力半导体制造有限公司 超级结的沟槽填充方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738212A (zh) * 2011-03-29 2012-10-17 万国半导体股份有限公司 边缘端接中产生鞍型结电场的改良型结构及方法
CN102420125A (zh) * 2011-06-07 2012-04-18 上海华力微电子有限公司 一种深沟槽氧化物刻蚀改进工艺
CN105702709A (zh) * 2016-01-29 2016-06-22 上海华虹宏力半导体制造有限公司 沟槽型超级结的制造方法
CN105702710A (zh) * 2016-01-29 2016-06-22 上海华虹宏力半导体制造有限公司 深沟槽型超级结器件的制造方法
CN107275389A (zh) * 2017-06-30 2017-10-20 上海华虹宏力半导体制造有限公司 超级结的沟槽填充方法

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