CN102683331B - 侧装控制器及其制造方法 - Google Patents
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Abstract
公开了一种用于电子设备的具有管芯的垂直堆叠和侧装电路的管芯封装及其制造方法。与安装到所述堆叠的上表面或所述堆叠附近相反,所述侧装电路被安装到所述堆叠的垂直表面,以减小NVM封装的体积。
Description
背景技术
NAND闪存以及其它类型的非易失性存储器(“NVM”)通常用于大容量存储。例如,诸如便携式媒体播放器的消费电子设备通常包括闪存以存储音乐、视频、以及其它媒体。
闪存以硅管芯的形式存在,且在一些实现中,可以使用多于一个的管芯。多管芯实现具有更大存储容量,但是也需要额外的有效面积(realestate)和关联的支持电子电路,例如总线、控制电路、和功率电路。此外,控制电路可被置于多管芯堆叠顶上或管芯附近的印刷电路板上,这两者都会增加系统的总空间需求。
发明内容
公开了具有垂直堆叠管芯和侧装电路的管芯封装及其制造方法。与安装到堆叠的上表面相反,所述侧装电路被安装至该堆叠的侧面区域,例如该堆叠的垂直表面,以减小NVM封装的高度。
附图说明
如下通过结合其中相似参考标记始终表示相似部分的附图的详细说明,本发明的上述和其它特点与优点将变得更加显见,在附图中:
图1示出了根据本发明各个实施例的非易失性存储器封装的说明性透视图;
图2A-D示出了根据本发明各个实施例的各种非易失性存储器封装的说明性截面图;
图3A-F示出了根据本发明各个实施例的堆叠管芯封装的说明性视图;
图4示出了根据本发明各个实施例的NVM封装的说明性侧视图;
图5A和5B示出了根据本发明各个实施例的NVM封装的说明性侧视图;
图6A-B示出了根据本发明各个实施例的管芯封装的说明性视图;
图7A和7B示出了根据本发明各个实施例的NVM封装的说明性侧视图和顶视图;
图8示出了根据本发明各个实施例的用于制造具有侧装控制电路的NVM封装的说明性工艺的流程图;以及
图9示出了根据本发明各个实施例的使用非易失性存储器封装的系统的简化框图。
具体实施方式
提供了具有垂直堆叠管芯和侧装控制电路的管芯封装及其制造方法。管芯的堆叠会产生与堆叠的上下表面垂直和/或非垂直的垂直表面(或壁)。这些垂直表面用作可以在其上安装各种侧装电路的有效面积。如在此定义的,垂直表面可以是垂直堆叠的任何侧面,且垂直表面可以垂直于上下表面,或它相对于上下表面可以是不垂直的。根据本发明的实施例,侧装电路能被安装到一个或多个垂直表面的一部分上。侧装电路能够减小NVM封装的高度和占地面积。这种减小能够有利地满足要求减小电子器件体积的设计准则,同时提供相同或增加的存储容量。
现在参考图1,示出了根据实施例构造的NVM封装100的说明性透视图。NVM封装100可以包括NVM管芯102的垂直堆叠和侧装电路104。侧装电路104可以安装在垂直表面106a-d中的一个表面的一部分上。如图1所示,例如,电路104被安装在垂直表面106a上。在其它实施例中,电路可以安装在垂直表面106a-d中的两个或更多个表面上。
NVM管芯102中的各管芯在形状上可以基本为矩形(例如,矩形或方形),因而可以具有长度、宽度、上表面、下表面、侧表面、和边缘。虽然仅仅在图1中示出了4个管芯,但是本领域技术人员将会理解可以堆叠任何合适数量的NVM管芯102以形成垂直堆叠(例如,8个或16个NVM管芯)。垂直表面106a-d由每个管芯102侧表面的集合形成。因而,随着堆叠中的管芯102数量的增加,垂直表面106a-d的面积相应增加。垂直表面106a-d不同于NVM封装100的上表面107和下表面108。
管芯102可以包括基于浮栅或电荷俘获技术的NAND闪存(例如,各管芯102可以是NAND闪速芯片)、NOR闪存、EPROM、EEPROM、铁电RAM(“FRAM”)、或磁阻RAM(“MRAM”)。管芯102可以是“生(raw)”NAND且同样地包含用于存储数据的单级单元(“SLC”)和/或多级单元(“MLC”)、地址线(例如,字线)、用于访问SLC或MLC的寻址电路、以及诸如电荷泵的其它特定于管芯的电路。
应当明了虽然在此涉及的管芯102为NAND闪存管芯,但是管芯102可以是任何其它合适的硅基产品。例如,管芯102可以是易失性存储器管芯,例如DRAM或SRAM。作为另一实施例,可以堆叠具有不同功能的管芯。例如,堆叠可以包括片上系统(“SOC”)管芯、DRAM管芯、和NAND管芯,并且侧装电路可以安装在该堆叠的侧面。
侧装电路104可以具有任何合适的形状,例如矩形或方形。侧装电路104可以相对于管芯102执行任何合适的功能。即,侧装电路104的功能可以取决于嵌入在管芯102中的产品。在一个实施例中,侧装电路104可以用作NVM封装100的控制电路或控制器。侧装电路104可被构造为访问NVM管芯102中的一个或多个管芯的存储单元。例如,侧装电路104可被构造为执行任意数量的NVM操作并且可以包含与NVM管芯102以及远离NVM封装100布置的电路相通信的接口。NVM操作可以包括用于提供完全管理NAND解决方案的操作,例如保持转换表、和/或执行损耗均衡、刷新事件、错误校正、以及无用单元收集。作为替换,由电路104执行的NVM操作可以包括完全管理NAND操作的子集,且该子集的执行在此可被称为简化的管理NAND解决方案。如下将结合图6讨论各个控制电路功能的额外细节。
在另一实施例中,如果管芯102是易失性存储器管芯,则侧装电路可以用作用于控制易失性存储器的控制电路。在又一实施例中,管芯包括SOC、DRAM、和NVM管芯的混合,并且侧装电路104可以是功率管理电路。在再一实施例中,侧装电路可以包括一个或多个无源部件,例如电阻器或电容器。
侧装电路104可以安装在NVM管芯102的垂直堆叠的垂直表面106a-d中的任一表面上。如图1所示,例如,电路104可以安装在垂直堆叠的垂直表面106a上。根据相对于每个管芯102的高度的电路104的尺寸,这种安装配置可以使得电路104延伸穿过NVM管芯102中的一个或多个管芯。
通过以这种方式将电路104安装到垂直堆叠,NVM封装100的高度规格会因为电路104的安装利用了垂直堆叠的现有高度而减小。因而,与电路104安装在管芯102的垂直堆叠顶上或在堆叠附近的印刷电路板上不同,占地面积和高度得到了减小。
现在参考图2A,示出了沿图1的线A-A得到的NVM封装100的说明性截面图。图2A示出了以垂直方式堆叠且具有安装至垂直表面106a的侧装电路104的管芯102。可以使用任何合适的安装技术将电路104安装至垂直表面106a。例如,设置在电路104和垂直表面106a之间的粘合层110可以将电路104固定到垂直堆叠。作为另一示例,绝缘或介电层(未示出)可以设置在每个管芯102之间以提供管芯102间的电隔离。
每个NVM管芯102可以包括定制焊盘和迹线布置(未示出)以便于将信号交换至管芯102、从管芯102交换信号、和/或在管芯102之间交换信号。焊盘可以经由互连电路(未示出)电耦合到控制电路104以允许在侧装电路104和管芯102之间通信。互连电路例如可以由任何合适的材料构造,例如,导电环氧树脂、引线接合、或其组合。互连电路可以具有任何合适的形状以将电路104电连接至管芯102。
图2B示出了根据本发明实施例的NVM封装120的说明性截面图。在NVM封装120中,以错列配置来排列管芯122。结果是,管芯122的边缘无法形成如图1和2A所示的平整壁,而是阶梯状的壁。可以施加粘合剂126用来填充间隙以提供一个其上可能安装有侧装电路124的基本平整的壁。粘合剂的量可以取决于侧装电路124的安装位置改变。如图2B所示,侧装电路124被安装以使其位于管芯122中的一个管芯之上。
图2C示出了根据本发明实施例的NVM封装130的说明性截面图。NVM封装130在许多方面类似于图2B的NVM封装120,不同之处在于其具有邻近所有管芯132安装的侧装电路134。粘合剂136可以填充管芯132和侧装电路134之间的间隙。
图2D示出了根据本发明实施例的NVM封装140的说明性截面图。NVM140在许多方面类似于NVM封装120和130,不同之处在于其具有与上下表面呈一定角度安装的侧装电路144。粘合剂146可以填充管芯142之间的间隙以提供一其上可以安装有侧装电路144的非垂直表面。
图3A和3B分别示出了根据本发明实施例的具有互连电路的NVM封装的说明性的侧视图和顶视图。互连电路320可以从电路304布线到管芯302垂直堆叠的上表面。在该上表面,互连电路320可以与一个或多个焊盘322和“内部”通孔324相接,其中焊盘322可以与顶管芯相关联,而“内部”通孔324则连接到位于顶管芯之下各管芯的焊盘。内部通孔是存在于管芯内的路径。通孔可以是穿通硅的通孔。例如,图3C示出了根据本发明一个实施例的安装在衬底上的堆叠型管芯封装的说明性侧视图。如所示,互连电路320从堆叠管芯的顶部布线至通孔324之一。
图3D和3E分别示出了根据本发明实施例的具有互连电路的管芯封装的说明性侧视图和顶视图。如所示,互连电路320是沿堆叠管芯的侧部和顶部沉积的、用以将控制电路304互连至管芯302的导电环氧树脂。图3E示出了互连电路320可被沉积为跨管芯堆叠顶部的带。然而,这仅仅是说明性的,并且本领域技术人员将会理解互连电路320可被沉积以使其布线至堆叠管芯的两个、三个、或全部四个侧面。图3F说明了如何沉积互连电路320使得其在堆叠管芯的三个侧面上与接合焊盘相接。
图4示出了根据本发明一个实施例的具有侧装电路404和互连电路420的NVM封装400的说明性侧视图。互连电路420在安装有侧装电路404的NVM封装400的相同侧面上被电耦合到每个管芯402。例如,互连电路420可以连接到焊盘或管芯402上的连接器。
图5A和5B示出了根据本发明一个实施例的具有侧装电路504和互连电路520的NVM封装500的说明性侧视图。互连电路520在NVM封装500的至少两侧上电耦合到管芯502。如所示,互连电路520存在于NVM封装500的相对侧上并且通过总线530连接到一起。
图6A示出了互连电路620的说明性视图,其中互连电路620穿过衬底630布线至NVM封装600的管芯602。衬底630例如可以是印刷电路板。互连电路620从侧装控制器604穿过衬底630的一层或多层布线至NVM封装600。互连电路620可以在NVM封装600邻接衬底630的访问点处(示出了一少部分)与管芯602相接。例如,互连电路620可以连接到通孔(未示出)。
图6B示出了接口电路622的说明性视图,其中接口电路622穿过衬底630布线至被连接到主机(未示出)的接合焊盘640。因而,图6B示出了侧装控制器可被如何连接到主机(例如,图9中的主机处理器910)的示例。
图7A和7B分别示出了根据本发明一个实施例的具有侧装电路704和互连电路720的NVM封装的侧视图和顶视图。互连电路720可以与从一个或多个管芯702的侧面向外突出的导体722连接。这些向外突出的导体722可被电耦合到管芯的焊盘,从而排除了对“内部”通孔的需求。因而,与突出导体的任何电耦合可以在管芯外部实现。在又一实施例中,互连电路可以与内部通孔和突出导体的组合相接。
图8示出了根据本发明一个实施例的用于制造具有侧装电路的封装的说明性工艺800的流程图。从步骤802开始,将多个管芯彼此安装地形成管芯的垂直堆叠。管芯可以是NVM管芯或易失性存储器管芯。在一些实施例中,管芯可以是处理器管芯、NVM管芯、和易失性存储器管芯的混合。管芯堆叠具有上表面、下表面、和若干垂直表面。继续至步骤804,侧装电路可被安装到垂直堆叠的垂直表面中的一个表面上。
在一些实施例中,粘合剂层和/或绝缘材料层可以起到将控制电路安装到垂直堆叠的垂直表面上的粘合剂的作用。因而,在一些情形中,粘合剂层和/或绝缘材料层可以设置在侧装电路和垂直堆叠的垂直表面之间。在其它实施例中,互连电路可以有效地用作将控制电路安装到垂直堆叠的垂直表面上的粘合剂。在一些实施例中,当管芯以错列的阶梯配置堆叠时,粘合剂可以提供其上可以安装侧装电路的基本平整表面。
然后,在步骤806,侧装电路可以电耦合到至少一个管芯或衬底(例如,如上图6所述)。取决于管芯构造(即,是使用内部通孔、偏移管芯还是突出导体),可以使用不同的互连电路来将控制电路电连接到管芯。
应当明了图8的工艺800仅仅是说明性的。可以移除、修改、或合并任意步骤,并且可以增加另外的步骤,而不超出本发明的范围。
图9是系统900的简化框图。系统900可以包括主机系统,主机系统可以包括处理器910、和根据本发明一个实施例构造的至少一个封装920。主机处理器910和封装920可以在任何合适的主机设备和系统中实现,例如便携式煤体播放器、蜂窝电话、超小型个人计算机、个人数字助理(“PDA”)、桌上型计算机、或膝上型计算机。为了简明,含有主机处理器910的主机设备或系统有时可被简称为“主机”。
主机处理器910可以包括一个或多个处理器或微处理器。作为替换或者附加,主机处理器910可以包括能够控制系统900的各种操作的其他任何部件或电路(例如,专用集成电路(“ASIC”)),或者可以结合这些部件或电路一起工作。在一个基于处理器的实现中,主机处理器910可以执行载入在主机上实施的存储器(未示出)的固件和软件程序。存储器可以包括任何合适类型的易失性存储器(例如,高速缓冲存储器或随机存取存储器(“RAM”),诸如双倍速率(“DDR”)RAM或静态RAM(“SRAM”))。主机处理器910可以控制NVM驱动器912,其可以提供特定于供应商和/或特定于技术的指令,使得主机处理器910能够执行用于NVM封装920的各种存储器管理和访问功能。
根据本发明的一个实施例,封装920可以是构造有侧装电路的堆叠型NVM封装。在一个实施例中,封装920可以是易失性存储器封装。在另一实施例中,封装可以是NVM封装。NVM封装920可以是全面的管理NVM封装或简化的管理NVM封装。在任一种管理NVM实现中,NVM封装920可以包括侧装电路922,该侧装电路922被电耦合到被垂直堆叠的任何合适数量的NVM管芯(例如,图1的NVM管芯102)。侧装电路922可以与图1的侧装电路104相同或类似。
侧装电路922可以包括处理器或基于硬件部件(例如,ASIC)的任何合适组合,并且可以包括与主机处理器910相同或不同的部件。在简化的管理NVM封装中,侧装电路922可以共享由NVM驱动器912管理和/或访问NVM管芯924的物理存储单元的职责。例如,NVM驱动器912可以执行除由侧装电路922执行的错误校正之外的所有管理功能。
在全面的管理NVM封装中,侧装电路922可以独立于主机处理器910执行用于NVM管芯924的基本上所有的管理和访问功能。以此途径,电路922可以将从NVM管芯924取回的数据传送到主机处理器910。全面的管理NVM封装例如可以在USB拇指驱动器中找到。
NVM管芯924可以用于存储需要在系统900断电时保留的信息。NVM管芯924可被组织成作为最小擦除单元的“块(block)”,并且可被进一步组织成作为最小可编程可读单元的“页面(pages)”。在一些实施例中,来自不同管芯的块可以形成“超级块(superblock)”。NVM管芯924的每个存储单元(例如,页面或块)可以采用物理地址(例如,物理页面地址或物理块地址)来寻址。
本发明所述实施例仅出于说明而非限制目的而被呈现。
Claims (20)
1.一种包含侧装控制电路的封装,包括:
以垂直堆叠排列的多个管芯,所述堆叠具有上表面、下表面、以及至少一个垂直表面;
安装到所述至少一个垂直表面中的一个垂直表面上的侧装控制电路,其中所述多个管芯包括非易失性存储器管芯,所述侧装控制电路是非易失性存储器控制器,其被配置为针对存入非易失性存储器管芯中的数据和/或从所述非易失性存储器管芯读取的数据进行至少一个非易失性存储器管理操作;以及
将所述侧装控制电路电耦合到所述多个管芯中的至少一个管芯的互连电路。
2.如权利要求1所述的封装,进一步包括布置在所述侧装控制电路和其上要安装所述侧装控制电路的所述垂直表面之间的粘合剂层。
3.如权利要求1所述的封装,其中所述多个管芯具有矩形形状,并且每个管芯具有4个侧面,所述侧面的堆叠集合形成所述至少一个垂直表面。
4.如权利要求1所述的封装,其中所述多个管芯以错列配置堆叠,并且在所述侧装控制电路和所述管芯之间存在有粘合剂。
5.如权利要求1所述的封装,其中堆叠的所述多个管芯包括管芯焊盘和/或通孔,并且其中所述互连电路电耦合到所述管芯焊盘和/或通孔。
6.如权利要求1所述的封装,其中所述多个管芯中的至少一个管芯包括从该至少一个管芯的侧面突出的导体,并且其中所述互连电路电耦合至所述导体。
7.如权利要求6所述的封装,其中所述导体电耦合到与所述多个管芯中的一个管芯相关联的焊盘。
8.如权利要求1所述的封装,其中所述互连电路包括穿通硅的通孔。
9.一种用于制造堆叠式管芯封装的方法,所述方法包括:
提供以垂直堆叠排列的多个管芯,所述管芯的垂直堆叠具有多个垂直表面;
将侧装控制电路安装到所述多个垂直表面中的至少一个垂直表面上,其中所述多个管芯包括非易失性存储器管芯,所述侧装控制电路是非易失性存储器控制器,其被配置为针对存入非易失性存储器管芯中的数据和/或从所述非易失性存储器管芯读取的数据进行至少一个非易失性存储器管理操作;以及
用互连电路将所述侧装控制电路电耦合到所述多个管芯中的至少一个管芯。
10.如权利要求9所述的方法,进一步包括在所述多个管芯的各管芯之间放置介电材料以将所述多个管芯彼此电隔离。
11.如权利要求9所述的方法,其中所述互连电路包括导电环氧树脂或引线接合。
12.一种包括侧装电路的系统,包括:
处理器;
与所述处理器操作通信的非易失性存储器封装,所述非易失性存储器封装包括:
以垂直堆叠排列的多个非易失性存储器管芯,所述堆叠具有上表面、下表面、以及多个垂直表面;
安装在所述多个垂直表面中的一个垂直表面上的侧装电路;以及
互连电路,所述互连电路将所述侧装电路电耦合到所述多个非易失性存储器管芯中的至少一个非易失性存储器管芯,其中所述侧装电路操作用以针对存入所述非易失性存储器封装中和/或从所述非易失性存储器封装读取的数据执行至少一种非易失性存储器管理操作。
13.如权利要求12所述的系统,其中所述至少一种非易失性存储器管理操作包括错误代码校正。
14.如权利要求12所述的系统,其中所述至少一种非易失性存储器管理操作包括将从所述处理器接收的指令转换成能由所述非易失性存储器封装处理的指令。
15.如权利要求12所述的系统,其中所述侧装电路操作用以访问所述多个管芯的存储单元。
16.如权利要求12所述的系统,其中所述侧装电路是安装在第一垂直表面上的第一侧装电路,所述非易失性存储器封装进一步包括:
安装在第二垂直表面上的第二侧装电路。
17.如权利要求16所述的系统,其中所述第一侧装电路操作用以访问所述多个管芯的存储单元,并且其中所述第二侧装电路操作用以对在所述处理器和所述非易失性存储器封装之间传输的数据施加错误代码校正。
18.一种用于制造堆叠式管芯封装的设备,所述设备包括:
以垂直堆叠排列多个管芯的装置,所述管芯的垂直堆叠具有多个垂直表面;
将侧装控制电路安装到所述多个垂直表面中的至少一个垂直表面上的装置,其中所述多个管芯包括非易失性存储器管芯,所述侧装控制电路是非易失性存储器控制器,其被配置为针对存入非易失性存储器管芯中的数据和/或从所述非易失性存储器管芯读取的数据进行至少一个非易失性存储器管理操作;以及
用互连电路将所述侧装控制电路电耦合到所述多个管芯中的至少一个管芯的装置。
19.如权利要求18所述的设备,进一步包括在所述侧装控制电路和其上要安装该侧装控制电路的所述垂直表面之间放置粘合剂层的装置。
20.如权利要求18所述的设备,其中所述多个管芯的各管芯是NAND闪存管芯。
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TW201312725A (zh) | 2013-03-16 |
TWI467730B (zh) | 2015-01-01 |
US20120211867A1 (en) | 2012-08-23 |
EP2490257A2 (en) | 2012-08-22 |
KR101511410B1 (ko) | 2015-04-10 |
KR20120101993A (ko) | 2012-09-17 |
KR101835149B1 (ko) | 2018-03-06 |
TW201248828A (en) | 2012-12-01 |
US8587088B2 (en) | 2013-11-19 |
CN102683331A (zh) | 2012-09-19 |
KR20120101991A (ko) | 2012-09-17 |
TWI484617B (zh) | 2015-05-11 |
EP2490257A3 (en) | 2013-08-14 |
WO2012112912A2 (en) | 2012-08-23 |
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