TW201312725A - 側邊安裝控制器及用於製作其之方法 - Google Patents

側邊安裝控制器及用於製作其之方法 Download PDF

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TW201312725A
TW201312725A TW101136259A TW101136259A TW201312725A TW 201312725 A TW201312725 A TW 201312725A TW 101136259 A TW101136259 A TW 101136259A TW 101136259 A TW101136259 A TW 101136259A TW 201312725 A TW201312725 A TW 201312725A
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Nicholas Seroff
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Abstract

揭示一種具有晶粒之一垂直堆疊及側邊安裝電路的晶粒封裝及用於製作該晶粒封裝之方法，以用於一電子裝置中。該側邊安裝電路安裝至該堆疊之一垂直表面，與一頂表面相對或與該堆疊鄰近以減小非揮發性記憶體(NVM)封裝的體積。

Description

側邊安裝控制器及用於製作其之方法
NAND快閃記憶體以及其他類型之非揮發性記憶體(「NVM」)通常用於大容量儲存。舉例而言，諸如攜帶型媒體播放器之消費型電子設備常常包括快閃記憶體以儲存音樂、視訊及其他媒體。
快閃記憶體以矽晶粒之形式存在，且在一些實施中，可使用一個以上晶粒。多晶粒實施提供較大之大容量儲存容量，但其亦可能需要額外的面積及相關聯之支援電子設備，諸如匯流排、控制電路及電力電路。另外，控制電路可置放於多個晶粒之堆疊的頂部或鄰近於該等晶粒之印刷電路板上，該堆疊及該印刷電路板皆可增大系統的整體空間要求。
揭示一種具有晶粒之一垂直堆疊及側邊安裝電路的晶粒封裝及用於製作該晶粒封裝之方法。該側邊安裝電路安裝至一側面區域，諸如該堆疊之一垂直表面，與該堆疊之一頂表面相對以減小NVM封裝的高度。
本發明之以上及其他態樣及優點將在考慮結合隨附圖式所考慮的以下詳細描述後變得更加顯而易見，其中相似參考字元遍及全文指代相似部分。
提供具有晶粒之垂直堆疊及側邊安裝控制電路的晶粒封裝及用於其製造之方法。晶粒之堆疊可產生垂直表面(或 壁)，該等垂直表面垂直及/或傾斜於堆疊之頂表面及底表面。此等垂直表面充當可安裝有各種側邊安裝電路之面積。如本文所定義，垂直表面可為垂直堆疊之任何側面，且垂直表面可垂直於頂表面及底表面或其可關於頂表面及底表面非垂直。根據本發明之實施例，側邊安裝電路可安裝至垂直表面中之一或多者的一部分。將電路側邊安裝可減小NVM封裝之高度及佔據面積。此等減小可有利地符合需要電子裝置之減小之體積的設計準則，而同時提供相同或增大之儲存容量。
現轉至圖1，展示根據一實施例所建構之NVM封裝100的說明性透視圖。NVM封裝100可包括NVM晶粒102之垂直堆疊及側邊安裝電路104。側邊安裝電路104可安裝於垂直表面106a至106d中之一者的一部分上。如圖1中所示，舉例而言，電路104安裝於垂直表面106a上。在其他實施例中，電路可安裝於垂直表面106a至106d中之兩者或兩者以上上。舉例而言， NVM晶粒102之每一晶粒可在形狀上實質上為矩形(例如，矩形或正方形)，且由此可具有長度、寬度、頂表面、底表面、側表面及邊緣。儘管圖1中僅展示四個晶粒，但熟習此項技術者應瞭解，任何合適數目個NVM晶粒102可經堆疊以形成垂直堆疊(例如，8或16個NVM晶粒)。垂直表面106a至106d係藉由每一晶粒102之側表面的聚集而形成。因此，隨著堆疊中之晶粒102的數目增大，垂直表面106a至106d之面積相應地增大。垂直表面106a至106d 與NVM封裝100之頂表面107及底表面108相異。
晶粒102可包括基於浮閘或電荷截獲技術之NAND快閃記憶體(例如，晶粒102中之每一者可為NAND快閃晶粒)、NOR快閃記憶體、EPROM、EEPROM、鐵電RAM(「FRAM」)或磁阻式RAM(「MRAM」)。晶粒102可為「原始」NAND且因而包括用於儲存資料之單層級胞(「SLC」)及/或多層級胞(「MLC」)、位址線(例如，字線)、用於存取SLC或MLC之定址電路，及諸如電荷泵之其他晶粒特定電路。
應理解，儘管晶粒102在本文中被稱為NAND快閃記憶體晶粒，但晶粒102可為任何其他合適的矽基產品。舉例而言，晶粒102可為諸如DRAM或SRAM之揮發性記憶體晶粒。作為另一實例，具有不同功能性之晶粒可經堆疊。舉例而言，堆疊可包括系統單晶片(「SOC」)晶粒、DRAM晶粒及NAND晶粒，且側邊安裝電路可安裝至堆疊之側面。
側邊安裝電路104可具有諸如矩形形狀或正方形形狀之任何合適的形狀。側邊安裝電路104可關於晶粒102執行任何合適的操作。亦即，側邊安裝電路104之功能性可取決於以晶粒102所體現的產品。在一實施例中，側邊安裝電路104可充當控制電路或用於NVM封裝100之控制器。側邊安裝電路104可經組態以存取NVM晶粒102中之一或多者的記憶體位置。舉例而言，側邊安裝電路104可經組態以執行任何數目個NVM操作且可包括用於與NVM晶粒102及遠 離NVM封裝100定位之電路通信的介面。NVM操作可包括用於提供完整管理NAND解決方案之操作，諸如維護轉譯表及/或執行磨損調平(wear leveling)、再新事件、錯誤校正及廢棄項目收集。替代地，藉由電路104所執行之NVM操作可包括完整管理NAND操作之子集，且此子集的執行可在本文中被稱為簡化管理NAND解決方案。下文結合圖6論述各種控制電路功能之額外細節。
在另一實施例中，若晶粒102為揮發性記憶體晶粒，則側邊安裝電路可充當用於控制揮發性記憶體之控制電路。在又一實施例中，晶粒包括SOC、DRAM及NVM晶粒之混合物，側邊安裝電路104可為電力管理電路。在又一實施例中，側邊安裝電路可包括諸如電阻器或電容器之一或多個被動組件。
側邊安裝電路104可安裝於NVM晶粒102之垂直堆疊之垂直表面106a至106d中的任一者上。如圖1中所示，舉例而言，電路104可安裝於垂直堆疊之垂直表面106a上。取決於電路104相對於晶粒102中之每一者之高度的大小，此安裝組態可使得電路104延伸跨越NVM晶粒102中的一或多者。
藉由以此方式將電路104安裝至垂直堆疊，NVM封裝100之高度規格減小，此係因為電路104之安裝利用垂直堆疊的現存高度。因此，與將電路104安裝於晶粒102之垂直堆疊之頂部或鄰近於堆疊的印刷電路板上對比，佔據面積及高度得以減小。
現參看圖2A，展示沿圖1之線A-A所截取的NVM封裝100之說明性橫截面視圖。圖2A展示以垂直型式堆疊之晶粒102，其中側邊安裝電路104安裝至垂直表面106a。可使用任何合適的安裝技術將電路104安裝至垂直表面106a。舉例而言，安置於電路104與垂直表面106a之間的黏著層110可將電路104緊固至垂直堆疊。作為另一實例，絕緣或介電層(未圖示)可安置於每一晶粒102之間以在晶粒102當中提供電隔離。
NVM晶粒102中之每一者可包括定製襯墊及跡線置放(未圖示)，以便促進至晶粒102、來自晶粒102及/或在晶粒102之間的信號交換。該等襯墊可經由互連電路(未圖示)電耦接至控制電路104，以准許側邊安裝電路104與晶粒102之間的通信。互連電路可由任何合適的材料建構，諸如導電環氧樹脂、線結合或其組合。互連電路可採用任何合適的形式以將電路104電連接至晶粒102。
圖2B展示根據本發明之一實施例之NVM封裝120的說明性橫截面視圖。在NVM封裝120中，晶粒122係以交錯組態配置。結果，晶粒122之邊緣可能不會形成諸如圖1及圖2A中所示之平坦壁的平坦壁，而是階梯狀壁。黏著劑126可經塗覆以填入間隙從而提供實質上平坦之壁，側邊安裝電路124可安裝至該壁上。黏著劑之量可取決於側邊安裝電路124所安裝之處而變化。如圖2B中所示，側邊安裝電路124經安裝，以使得其位於晶粒122中之一者上方。
圖2C展示根據本發明之一實施例之NVM封裝130的說明 性橫截面視圖。NVM封裝130在許多方面與圖2B之NVM封裝120類似，但NVM封裝130具有鄰近於所有晶粒132所安裝之側邊安裝電路134。黏著劑136可填入晶粒132與側邊安裝電路134之間的間隙。
圖2D展示根據本發明之一實施例之NVM封裝140的說明性橫截面視圖。NVM 140在許多方面與NVM封裝120及130類似，但NVM 140具有關於頂表面及底表面成一角度安裝的側邊安裝電路144。黏著劑146可填入晶粒142之間的間隙以提供非垂直表面，側邊安裝電路144可安裝於該非垂直表面上。
圖3A及圖3B分別展示根據本發明之一實施例的具有互連電路之NVM封裝的說明性側視圖及俯視圖。互連電路320可自電路304佈線至晶粒302之垂直堆疊的頂表面。在頂表面上，互連電路320可與一或多個襯墊322及「內部」通孔324介接，該一或多個襯墊322可與頂部晶粒相關聯，該等「內部」通孔324連接至位於頂部晶粒下方之晶粒的襯墊。內部通孔為存在於晶粒內之通路。通孔可為矽穿孔。舉例而言，圖3C展示根據本發明之一實施例的安裝於基板上之堆疊晶粒封裝的說明性側視圖。如圖所示，互連電路320佈線至堆疊晶粒之頂部至通孔324中之一者。
圖3D及圖3E分別展示根據本發明之一實施例的具有互連電路之晶粒封裝的說明性側視圖及俯視圖。如圖所示，互連電路320為導電環氧樹脂，該導電環氧樹脂係沿堆疊晶粒之側面及頂部沈積以將控制電路304互連至晶粒302。 圖3E展示互連電路320可沈積為跨越晶粒堆疊之頂部的條帶。然而，此僅為說明性的，且熟習此項技術者應瞭解，互連電路320可經沈積以使得其佈線至堆疊晶粒之兩個、三個或所有四個側面。圖3F說明互連電路320可經沈積以使得其與堆疊晶粒之三個側面上之結合襯墊介接的方式。
圖4展示根據本發明之一實施例的具有側邊安裝電路404及互連電路420之NVM封裝400的說明性側視圖。互連電路420電耦接至在NVM封裝400之安裝有側邊安裝電路404之同一側面上的晶粒402中之每一者。舉例而言，互連電路420可連接至晶粒402上之襯墊或連接器。
圖5A及圖5B展示根據本發明之一實施例的具有側邊安裝電路504及互連電路520之NVM封裝500的說明性側視圖。互連電路520電耦接至NVM封裝500之至少兩個側面上之晶粒502。如圖所示，互連電路520存在於NVM封裝500之相對側面上且藉由匯流排530連接在一起。
圖6A展示通過基板630佈線至NVM封裝600之晶粒602之介面電路620的說明性視圖。基板630可為(例如)印刷電路板。互連電路620自側邊安裝控制器604通過基板630之一或多個層佈線至NVM封裝600。互連電路620可在存取點(其中幾個被展示)處與晶粒602介接，NVM封裝600在該等存取點處鄰接基板630。舉例而言，介面電路620可連接至通孔(未圖示)。
圖6B展示通過基板630佈線至連接至主機(未圖示)之結合襯墊640之介面電路622的說明性視圖。因此，圖6B展示 側邊安裝控制器可連接至主機(例如，圖9之主機處理器910)之方式的實例。
圖7A及圖7B分別展示根據本發明之一實施例的具有側邊安裝電路704及互連電路720之NVM封裝的說明性側視圖及俯視圖。互連電路720可與遠離一或多個晶粒702之側面向外突出之導體722介接。此等向外突出之導體722可電耦接至晶粒之襯墊，藉此消除對「內部」通孔之需要。因此，與突出之導體的任何電耦接係在晶粒外部進行。在又一實施例中，互連電路可與內部通孔與突出之導體的組合介接。
圖8展示根據本發明之一實施例的用於製作具有側邊安裝控制電路之封裝的說明性處理程序800的流程圖。在步驟802處開始，安裝複數個晶粒至彼此以形成晶粒之垂直堆疊。該等晶粒可為NVM晶粒或揮發性記憶體晶粒。在一些實施例中，該等晶粒可為處理器晶粒、NVM晶粒及揮發性記憶體晶粒之混合物。晶粒之堆疊具有頂表面、底表面及若干垂直表面。繼續至步驟804，可將側邊安裝電路安裝至垂直堆疊之垂直表面中的一者。
在一些實施例中，一層黏著劑及/或絕緣材料可充當用於將控制電路安裝至垂直堆疊之垂直表面的黏著劑。因此，在某一狀況下，該層黏著劑及/或絕緣材料可置放於側邊安裝電路與垂直堆疊之垂直表面之間。在其他實施例中，互連電路可實際上充當用於將控制電路安裝至垂直堆疊之垂直表面的黏著劑。在一些實施例中，當晶粒係以交 錯之階梯組態堆疊時，黏著劑可提供實質上平坦之表面，側邊安裝電路可安裝至該表面上。
接著，在步驟806處，可將側邊安裝電路電耦接至至少一晶粒或基板(例如，如上文結合圖6所論述)。取決於晶粒之構造(亦即，是否使用「內部」通孔、偏置晶粒(offset die)或突出之導體)，不同的互連電路可用以將控制電路電連接至晶粒。
應理解，圖8之處理程序800僅為說明性的。可移除、修改或組合該等步驟中之任一者，且可添加任何額外的步驟，而不脫離本發明的範疇。
圖9為系統900之簡化方塊圖。系統900可包括主機系統及根據本發明之一實施例所建構的至少一封裝920，該主機系統可包括處理器910。主機處理器910及封裝920可實施於任何合適的主機裝置或系統中，諸如攜帶型媒體播放器、蜂巢式電話、口袋型個人電腦、個人數位助理(「PDA」)、桌上型電腦或膝上型電腦。為簡單性起見，可包括主機處理器910之主機裝置或系統有時可簡單地稱為「主機」。
主機處理器910可包括一或多個處理器或微處理器。另外或替代地，主機處理器910可包括能夠控制系統900(例如，特殊應用積體電路(「ASIC」))之各種操作的任何其他組件或電路，或結合該等任何其他組件或電路操作。在基於處理器之實施中，主機處理器910可執行載入至實施於主機上之記憶體(未圖示)中的韌體及軟體程式。該記憶 體可包括任何合適類型之揮發性記憶體(例如，快取記憶體或諸如雙資料速率(「DDR」)RAM或靜態RAM(「SRAM」)之隨機存取記憶體(「RAM」))。主機處理器910可執行NVM驅動程式912，驅動程式912可提供廠商特定及/或技術特定指令，該等指令使得主機處理器910能夠為NVM封裝920執行各種記憶體管理及存取功能。
封裝920可為根據本發明之一實施例之堆疊式NVM封裝，該封裝經建構有側邊安裝電路。在一實施例中，封裝920可為揮發性記憶體封裝。在另一實施例中，封裝可為NVM封裝。NVM封裝920可為綜合管理NVM封裝或簡化管理NVM封裝。在任一管理NVM實施中，NVM封裝920可包括側邊安裝電路922，側邊安裝電路922電耦接至垂直堆疊之任何合適數目個NVM晶粒(例如，圖1之NVM晶粒102)。側邊安裝電路922可與圖1之側邊安裝電路104相同或類似。
側邊安裝電路922可包括處理器或基於硬體之組件(例如，ASIC)之任何合適的組合，且可包括與主機處理器910相同之組件或不同的組件。在簡化管理NVM封裝中，側邊安裝電路922可與NVM驅動程式912分擔管理及/或存取NVM晶粒924之實體記憶體位置的職責。舉例而言，NVM驅動程式912可執行除錯誤校正以外的所有管理功能，錯誤校正係藉由側邊安裝電路922執行。
在綜合管理NVM封裝中，側邊安裝電路922可獨立於主機處理器910而執行NVM晶粒924之實質上所有管理及存取 功能。在此方法中，電路922可將自NVM晶粒924所擷取之資料傳遞至主機處理器910。綜合管理NVM封裝可在(例如)USB隨身碟中找到。
NVM晶粒924可用以儲存在系統900被電源斷開時需要保留之資訊。NVM晶粒924可組織成「區塊」，「區塊」為抹除之最小單位，且該等NVM晶粒進一步組織成「頁」，「頁」為最小的可程式化及可讀單位。在一些實施例中，來自不同晶粒之區塊可形成「超級區塊」。可使用實體位址(例如，實體頁位址或實體區塊位址)來定址NVM晶粒924之每一記憶體位置(例如，頁或區塊)。
本發明之所述實施例係為說明而非限制之目的呈現。
100‧‧‧非揮發性記憶體(NVM)封裝
102‧‧‧NVM晶粒
104‧‧‧側邊安裝電路
106a‧‧‧垂直表面
106b‧‧‧垂直表面
106c‧‧‧垂直表面
106d‧‧‧垂直表面
107‧‧‧頂表面
108‧‧‧底表面
110‧‧‧黏著層
120‧‧‧NVM封裝
122‧‧‧晶粒
124‧‧‧側邊安裝電路
126‧‧‧黏著劑
130‧‧‧NVM封裝
132‧‧‧晶粒
134‧‧‧側邊安裝電路
136‧‧‧黏著劑
140‧‧‧NVM封裝
142‧‧‧晶粒
144‧‧‧側邊安裝電路
146‧‧‧黏著劑
302‧‧‧晶粒
304‧‧‧控制電路
320‧‧‧互連電路
322‧‧‧襯墊
324‧‧‧「內部」通孔
400‧‧‧NVM封裝
402‧‧‧晶粒
404‧‧‧側邊安裝電路
420‧‧‧互連電路
500‧‧‧NVM封裝
502‧‧‧晶粒
504‧‧‧側邊安裝電路
520‧‧‧互連電路
530‧‧‧匯流排
600‧‧‧NVM封裝
602‧‧‧晶粒
604‧‧‧側邊安裝控制器
620‧‧‧介面電路/互連電路
622‧‧‧介面電路
630‧‧‧基板
640‧‧‧結合襯墊
702‧‧‧晶粒
704‧‧‧側邊安裝電路
720‧‧‧互連電路
722‧‧‧導體
900‧‧‧系統
910‧‧‧主機處理器
912‧‧‧NVM驅動程式
920‧‧‧NVM封裝
922‧‧‧側邊安裝電路
924‧‧‧NVM晶粒
圖1展示根據本發明之各種實施例之非揮發性記憶體封裝的說明性透視圖；圖2A至圖2D展示根據本發明之各種實施例之各種非揮發性記憶體封裝的說明性橫截面視圖；圖3A至圖3F展示根據本發明之各種實施例之堆疊晶粒封裝的說明性視圖；圖4展示根據本發明之各種實施例之NVM封裝的說明性側視圖；圖5A及圖5B展示根據本發明之各種實施例之NVM封裝的說明性側視圖；圖6A至圖6B展示根據本發明之各種實施例之晶粒封裝的說明性視圖； 圖7A及圖7B展示根據本發明之各種實施例之NVM封裝的說明性側視圖及俯視圖；圖8展示根據本發明之各種實施例的用於製作具有側邊安裝控制電路之NVM封裝之說明性處理程序的流程圖；及圖9展示根據本發明之各種實施例的使用非揮發性記憶體封裝之系統的簡化方塊圖。
100‧‧‧非揮發性記憶體(NVM)封裝
102‧‧‧NVM晶粒
104‧‧‧側邊安裝電路
106a‧‧‧垂直表面
106b‧‧‧垂直表面
106c‧‧‧垂直表面
106d‧‧‧垂直表面
107‧‧‧頂表面
108‧‧‧底表面

Claims (1)

  1. 一種封裝，其包含：複數個晶粒，其係以一垂直堆疊配置，該堆疊具有一頂表面、一底表面及至少一垂直表面；側邊安裝控制電路，其安裝至該至少一垂直表面中之一者；及互連電路，其將該控制電路電耦接至該等晶粒中之至少一者。
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EP2490257A2 (en) 2012-08-22
WO2012112912A2 (en) 2012-08-23
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KR20120101993A (ko) 2012-09-17
KR20120101991A (ko) 2012-09-17
WO2012112912A3 (en) 2014-04-17
CN102683331A (zh) 2012-09-19
US20120211867A1 (en) 2012-08-23
CN102683331B (zh) 2016-02-03
KR101511410B1 (ko) 2015-04-10
TWI467730B (zh) 2015-01-01
TWI484617B (zh) 2015-05-11
EP2490257A3 (en) 2013-08-14
US8587088B2 (en) 2013-11-19

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