CN102522380A - 一种PoP封装结构 - Google Patents

一种PoP封装结构 Download PDF

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CN102522380A
CN102522380A CN201110432932XA CN201110432932A CN102522380A CN 102522380 A CN102522380 A CN 102522380A CN 201110432932X A CN201110432932X A CN 201110432932XA CN 201110432932 A CN201110432932 A CN 201110432932A CN 102522380 A CN102522380 A CN 102522380A
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support plate
fin
pop
chip
encapsulating structure
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CN102522380B (zh
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刘伟锋
叶裕明
向朝
许智
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Honor Device Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2012/083603 priority patent/WO2013091441A1/zh
Priority to EP12859210.2A priority patent/EP2693477A1/en
Priority to US14/107,808 priority patent/US9318407B2/en
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Abstract

本发明实施例公开了一种PoP封装结构,包括依次堆叠封装的至少两层载板,所述载板的top面设有芯片,除第一层载板外的其它载板的bottom面均设有散热片,所述第一层载板的bottom面设有焊接到系统板上的焊盘,除顶层载板外的其它载板上的芯片贴设于邻近该芯片的散热片上。本发明实施例通过在除第一层载板外的其它载板的bottom面设置散热片来对上一层载板上的芯片(裸硅片或者封装后的芯片)散热。本发明实施例通过散热片增加了芯片的散热面积,可以大幅度的提升PoP堆叠封装的散热能力,突破PoP堆叠封装的高密,小型化的瓶颈,提升PoP堆叠封装的封装密度。

Description

一种PoP封装结构
技术领域
本发明PCB封装散热技术领域,特别涉及一种PoP封装结构。
背景技术
作为目前封装高密集成的主要方式,PoP(package on package,叠层封装)得到越来越多的重视。但是,封装堆叠的增加将会带来散热的问题,成为阻碍PoP应用的瓶颈之一。
芯片的堆叠是提高电子封装高密化的主要途径之一,PoP设计已经在业界得到比较广泛的开发和应用。一个典型的两层PoP设计如图1所示,第二层的封装13通过焊球12的回流过程焊接到第一层的封装11上,更多层的PoP设计可以重复如上过程。为了避免第一层的芯片和第二层的载板产生干扰,第二层周边的焊球12直径一般设计为大于芯片的高度,这样在第一层的芯片和第二层的载板之间会有一定的间隙,借助散热风扇,通过该间隙对芯片进行散热。
PoP设计虽然能够提高封装的密度,但是对于芯片的散热却没有帮助;相反,由于多个芯片叠加在一起,热量在PoP封装内部积累,仅靠芯片与载板之间的缝隙以及散热风扇进行散热以不能满足要求,PoP的散热成为制约PoP高密化的主要瓶颈。
因此,如何在保证PoP封装高密,小型化的基础上,提高散热能力,成为本领域技术人员亟待解决的重要技术问题。
发明内容
本发明提供了一种PoP封装结构,以在保证PoP封装高密,小型化的基础上,提高散热能力。
为实现上述目的,本发明提供如下技术方案:
一种PoP封装结构,包括依次堆叠封装的至少两层载板,所述载板的top面设有芯片,除第一层载板外的其它载板的bottom面均设有散热片,所述第一层载板的bottom面设有焊接到系统板上的焊盘,除顶层载板外的其它载板上的芯片贴设于邻近该芯片的散热片上。
从上述的技术方案可以看出,本发明实施例提供的PoP封装结构,通过在除第一层载板外的其它载板的bottom面设置散热片来对上一层载板上的芯片(裸硅片或者封装后的芯片)散热。本发明实施例通过散热片增加了芯片的散热面积,可以大幅度的提升PoP堆叠封装的散热能力,突破PoP堆叠封装的高密,小型化的瓶颈,提升PoP堆叠封装的封装密度。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中一种两层的PoP封装结构的结构示意图;
图2为本发明实施例提供的PoP封装结构的结构示意图;
图3为本发明实施例提供的一种散热片形状的结构示意图;
图4为本发明实施例提供的第二种散热片形状的结构示意图;
图5为本发明实施例提供的第三种散热片形状的结构示意图;
图6为本发明实施例提供的第四种散热片形状的结构示意图;
图7为本发明实施例提供的第五种散热片形状的结构示意图;
图8为本发明实施例提供的第六种散热片形状的结构示意图;
图9为本发明实施例提供的另一种PoP封装结构的结构示意图;
图10为本发明实施例提供的再一种PoP封装结构的结构示意图;
图11为本发明实施例提供的又一种PoP封装结构的结构示意图;
图12为本发明实施例提供的第一层载板的top面的结构示意图;
图13为本发明实施例提供的第一层载板的bottom面的结构示意图;
图14为本发明实施例提供的第二层载板的top面的结构示意图;
图15为本发明实施例提供的第二层载板的bottom面的结构示意图;
图16为本发明实施例提供的顶层载板的top面的结构示意图;
图17为本发明实施例提供的顶层载板的bottom面的结构示意图;
图18为本发明实施例提供的顶层载板的结构示意图;
图19为本发明实施例提供的第二层载板的结构示意图;
图20为本发明实施例提供的第一层载板的结构示意图;
图21为本发明实施例提供的堆叠回流后的各层载板的结构示意图;
图22为本发明实施例提供的顶层芯片贴有散热片的PoP封装结构的结构示意图;
图23为本发明实施例提供的侧壁镀铜或者散热孔的PoP封装结构的结构示意图。
具体实施方式
本发明实施例公开了一种PoP封装结构,以在保证PoP封装高密,小型化的基础上,提高散热能力。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
请参阅图2,图2为本发明实施例提供的PoP封装结构的结构示意图。
本发明实施例提供的一种PoP封装结构,包括依次堆叠封装的至少两层载板,载板的top面设有芯片。本发明实施例的重点在于,除第一层载板外的其它载板的bottom面均设有散热片,第一层载板的bottom面设有焊接到系统板上的焊盘,除顶层载板外的其它载板上的芯片贴设于邻近该芯片的散热片上。
图2公开的为三层载板结构的PoP封装结构,由图2可见,第一层载板109由于需要焊接到系统板上(第一层载板109的bottom面设有焊盘110),因此第一层载板109的top面不可再设置散热片,也不存在设置散热片的需求。第二层载板106的top面设有芯片105,第二层载板106的bottom面设有散热片107,该散热片107用于为第一层载板109上的芯片108散热。顶层载板103的top面设有芯片102,顶层载板103的bottom面设有散热片104,该散热片104于为第二层载板106上的芯片105散热。
本领域技术人员可以理解的是,本发明实施例公开的PoP封装结构并不局限于三层载板结构的一种形式,只要在两层载板以上即可采用本发明实施例公开的PoP封装结构的散热方式。即在除第一层载板109外的其它各层载板的bottom面均设有散热片,并保证除顶层载板103外的其它各层载板上的芯片贴设于邻近该芯片的散热片上(即第一层载板109上的芯片108贴设于第二层载板106的散热片107上;第二层载板106的芯片105贴设于顶层载板103的散热片104上)。
对于PoP设计,层与层之间需要电气连接(信号或者供电以及接地),这些连接可以采用有铅或者无铅焊球的方式,或者其他方式,如导电胶。散热片应该规避这些电气连接的区域。为了使得散热片能够避开电气连接的区域,图3-图8给出了几种可能的铜箔外形设计,但是不限于如图所示的几种设计。
在本实施例中,散热片202可为图3和图4示出的长方形,可见散热片202避开了位于载板两侧边缘的信号连接点201。散热片202也可为图5和图6示出的十字形结构,可见散热片202避开了位于载板四个边角位置的信号连接点201。散热片202也可为图8示出的工字型,可见散热片202避开了位于载板两侧中间的信号连接点201。散热片202还可为图7示出的异形结构,可见散热片202避开了位于载板两侧呈扇形分布的信号连接点201。散热片202还可为其它结构形式,本发明实施例不再一一赘述。
为了进一步提高散热效果,散热片应尽可能的向周围扩展,即扩展到载板之外。如图9所示,散热片107外伸于第二层载板106之外;散热片104外伸于顶层载板103之外;使得散热片107与散热片104之间有空隙,在强迫风冷的情况下,空气在散热片之间流动,从而带走散热片的热量。
散热片可以如图9所示的单独伸展出PoP封装之外,也可为如图10和图11所示的,散热片可以折成各式各样的形状。如图10所示,散热片107与散热片104外伸于载板的部分向上弯折;如图11所示,散热片107与散热片104外伸于载板的部分向下弯折。
在散热片和芯片之间可以添加导热界面材料层112(TIM:thermal interfacematerial)来减低散热片和芯片之间的热阻,从而使热量有效的从芯片传导到散热片。散热片的厚度可以根据散热的要求进行相应的调整。
PoP封装结构的制备过程简述如下(举例针对BGA(Ball Grid Array,球栅阵列结构的线路板)或者CSP(Chip Scale Package,芯片尺寸封装)封装,其它封装形式也是适用的):
首先是制备PoP封装结构的各层载板,以三层载板的PoP封装结构为例,从第一层,第二层,到顶层的载板。第一层载板109会直接焊接到系统板上,顶层载板103上不会再有其它载板,所以它们的设计和其他各层载板的设计会有不同。
如图12和图13所示,图12为本发明实施例提供的第一层载板的top面的结构示意图;图13为本发明实施例提供的第一层载板的bottom面的结构示意图。
对于第一层载板109的bottom面有连接焊球的焊盘110,这些焊球最终会焊接到系统板上,top面有两种焊盘,中间的焊盘是用于焊接BGA/CSP封装(芯片焊盘1092),边缘的焊盘是用来焊接上层的载板(PoP焊盘1091)。
如图14和图15,图14为本发明实施例提供的第二层载板的top面的结构示意图;图15为本发明实施例提供的第二层载板的bottom面的结构示意图。
对于第二层以及以上(除顶层)的载板,以第二层载板106的top面有两种焊盘,中间的焊盘是用于焊接BGA/CSP封装(芯片焊盘1062);边缘的焊盘是用来焊接上层的载板(PoP焊盘1061),可以有一排或者几排,根据电气连接要求确定。bottom面(底面)有用于散热的散热片107,边缘有用来焊接上层载板的焊盘(PoP焊盘),散热器107和PoP焊盘之间是隔开的。
请参阅图16和图17,图16为本发明实施例提供的顶层载板的top面的结构示意图;图17为本发明实施例提供的顶层载板的bottom面的结构示意图。
顶层载板103的bottom面和第二层载板106的bottom面是一样的,bottom面有用于散热的散热片104,边缘有用来焊接上层载板的焊盘(PoP焊盘),散热片104和PoP焊盘之间是隔开的;顶层载板103的top面可以只有用于焊接芯片的焊盘(芯片焊盘1031)。
本实施例公开的是堆叠同样的封装,但也适用于不同的封装堆叠。对于在PoP内部实现不同的封装堆叠,可以依照同样的制备过程,这里就不做描述。对于二层以上bottom面的散热片的制备,可以在PCB载板制备中直接压合散热片,然后对散热片进行刻蚀,形成相应的散热片形状,在这个过程中,也可以相应刻蚀形成PoP焊盘(相邻两层载板之间通过PoP焊盘连接,PoP焊盘与散热片相互隔开)。对于bottom面焊盘和top面焊盘的连接,可以通过通孔连接。这些载板的制备和普通的PCB制备过程没有什么不同,在这里就不做描述。
请参阅图18-图20,图18为本发明实施例提供的顶层载板的结构示意图;图19为本发明实施例提供的第二层载板的结构示意图;图20为本发明实施例提供的第一层载板的结构示意图。
回流焊接芯片(BGA/CSP封装)到载板,在这个过程中,可以同时焊接焊球到载板形成相应的PoP焊球。首先需要在各层的top面通过钢网印刷焊锡锡膏,然后放置芯片在芯片焊盘区域,芯片的焊球正对载板的焊盘(芯片102的焊球正对顶层载板103的焊盘;芯片105的焊球正对第二层载板106的焊盘;芯片108的焊球正对第一层载板109的焊盘),同时在边缘PoP焊盘上放置焊球(如图21中的焊球111),焊球的直径可以根据芯片焊接后的高度以及要用的导热界面材料层112的厚度确定。然后把各层的载板进行高温回流,从而焊接芯片到PoP载板,同时形成PoP焊球。
请参阅图21,图21为本发明实施例提供的堆叠回流后的各层载板的结构示意图。
在载板堆叠回流过程中需要反转各层载板,然后在底层的焊盘上以及其他各层的PoP焊盘上印刷焊膏,在印刷过程中,需要设计相应的工装来支撑载板,避免倾斜以及对芯片的挤压冲击。同时在第二层(以三层载板为例,为第二层载板和顶层载板)以上的载板bottom面散热片正对芯片区域放置导热界面材料层112,导热界面材料层112的面积应该和芯片面积一致,厚度根据散热要求以及PoP设计确定。然后把各层的载板按照堆叠设计叠加在一起,第一层载板在上部,顶层载板在底部,需要设计工装来保证堆叠结构的稳定。在第一层载板的焊盘上放置焊球,之后把整个PoP封装放入回流炉中进行回流,从而把各层的载板焊接在一起,同时形成底部载板的ball grid array,整个过程完成后PoP结构如图21所示。
请参阅图22,图22为本发明实施例提供的顶层芯片贴有散热片的PoP封装结构的结构示意图。
为了提高顶层载板上的芯片的散热,顶层载板上的芯片上通过导热胶113粘接有散热片101,顶层载板top面设有用于焊接芯片的焊盘。散热片101在本实施例中可以导热胶113粘在芯片上,散热片也可以扩展到PoP封装之外,以便有效的散热。
请参阅图23,图23为本发明实施例提供的侧壁镀铜或者散热孔的PoP封装结构的结构示意图。
为了进一步提高PoP封装结构的散热效果,在散热片可粘接散热铜板或铜块的散热结构。也可以通过在散热片上开设散热孔114或者在载板的侧壁镀铜(即在载板的侧壁设置散热铜片)的方式,进一步的增强散热能力。
上述各个实施例公开的散热片均优选为铜片、铜箔等铜质散热结构,铜片的散散热效果优良,而且可通过蚀刻的方式形成各种形状。
综上所述,在与芯片顶部接触的载板区域设计铜箔(散热片),利用铜箔进行辅助散热。可以通过布局的设计实现电气信号与散热通道之间的隔离。在铜箔和芯片之间需要添加导热界面材料(TIM:thermal interface material),来减低铜箔和芯片之间的热阻,从而使热量有效的从芯片传导到铜箔。铜箔的厚度可以根据散热的要求进行相应的调整。
本发明实施例提供的PoP封装结构,通过在除第一层载板外的其它载板的bottom面设置散热片来对上一层载板上的芯片(裸硅片或者封装后的芯片)散热。本发明实施例通过散热片增加了芯片的散热面积,可以大幅度的提升PoP堆叠封装的散热能力,突破PoP堆叠封装的高密,小型化的瓶颈,提升PoP堆叠封装的封装密度。
本说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明,使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的,本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下,在其它实施例中实现。因此,本发明将不会被限制于本文所示的这些实施例,而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (13)

1.一种PoP封装结构,包括依次堆叠封装的至少两层载板,所述载板的top面设有芯片,其特征在于,除第一层载板外的其它载板的bottom面均设有散热片,所述第一层载板的bottom面设有焊接到系统板上的焊盘,除顶层载板外的其它载板上的芯片贴设于邻近该芯片的散热片上。
2.如权利要求1所述的PoP封装结构,其特征在于,所述散热片外伸于与该散热片连接的载板。
3.如权利要求2所述的PoP封装结构,其特征在于,所述散热片外伸于载板的部分向上或向下弯折。
4.如权利要求1所述的PoP封装结构,其特征在于,所述散热片避开与其连接的载板上的电气连接区域。
5.如权利要求4所述的PoP封装结构,其特征在于,所述散热片为长方形、工字型、十字形或异形结构。
6.如权利要求1所述的PoP封装结构,其特征在于,所述散热片和芯片之间设有导热界面材料层。
7.如权利要求1所述的PoP封装结构,其特征在于,所述顶层载板上的芯片上通过导热胶粘接有散热片。
8.如权利要求1-7任一项所述的PoP封装结构,其特征在于,所述散热片上设有散热铜板。
9.如权利要求1-7任一项所述的PoP封装结构,其特征在于,所述散热片上开设有散热孔。
10.如权利要求1-7任一项所述的PoP封装结构,其特征在于,所述载板的侧壁设有散热铜片。
11.如权利要求1-7任一项所述的PoP封装结构,其特征在于,所述散热片为直接压合至载板,并蚀刻成相应图形的铜片。
12.如权利要求1-7任一项所述的PoP封装结构,其特征在于,相邻两层载板之间通过PoP焊盘连接。
13.如权利要求12所述的PoP封装结构,其特征在于,所述PoP焊盘与所述散热片相互隔开。
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012159533A1 (en) * 2011-05-26 2012-11-29 Huawei Technologies Co., Ltd. Thermally enhanced stacked package and method
WO2013091441A1 (zh) * 2011-12-21 2013-06-27 华为技术有限公司 一种PoP封装结构
CN104538375A (zh) * 2014-12-30 2015-04-22 华天科技(西安)有限公司 一种扇出PoP封装结构及其制造方法
CN104733411A (zh) * 2014-12-30 2015-06-24 华天科技(西安)有限公司 一种三维堆叠圆片级扇出PoP封装结构及其制造方法
CN105453255A (zh) * 2013-08-12 2016-03-30 三星电子株式会社 热界面材料层及包括热界面材料层的层叠封装件器件
CN106356344A (zh) * 2016-09-08 2017-01-25 华进半导体封装先导技术研发中心有限公司 基于三维堆叠封装的风冷散热结构及制造方法
CN107993988A (zh) * 2017-11-13 2018-05-04 芯原微电子(上海)有限公司 一种叠层封装结构及其制备方法
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WO2024036765A1 (zh) * 2022-08-19 2024-02-22 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
KR102265243B1 (ko) 2015-01-08 2021-06-17 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102589684B1 (ko) 2018-12-14 2023-10-17 삼성전자주식회사 반도체 패키지
CN112864022B (zh) * 2019-11-26 2024-03-22 天芯互联科技有限公司 封装结构的制作方法及封装结构

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301779B1 (en) * 1998-10-29 2001-10-16 Advanced Thermal Solutions, Inc. Method for fabricating a heat sink having nested extended surfaces
US20020024798A1 (en) * 1998-06-30 2002-02-28 Moden Walter L. Heat sink with alignment and retaining features
US20040080036A1 (en) * 2002-10-24 2004-04-29 Advanced Semiconductor Engineering, Inc. System in package structure
US20050199993A1 (en) * 2004-03-10 2005-09-15 Jong-Joo Lee Semiconductor package having heat spreader and package stack using the same
CN1835230A (zh) * 2005-03-17 2006-09-20 松下电器产业株式会社 叠层型半导体装置
CN1961421A (zh) * 2004-03-31 2007-05-09 斯塔克泰克集团有限公司 集成电路堆叠系统及方法
CN101097906A (zh) * 2006-06-29 2008-01-02 海力士半导体有限公司 具有垂直形成的热沉的层叠封装
US20080048309A1 (en) * 2006-08-28 2008-02-28 Corisis David J Metal core foldover package structures, systems including same and methods of fabrication
CN101431033A (zh) * 2007-11-06 2009-05-13 南茂科技股份有限公司 多芯片堆栈封装方法
CN101937907A (zh) * 2009-06-29 2011-01-05 财团法人工业技术研究院 芯片堆叠封装结构及其制作方法
US20110176280A1 (en) * 2010-01-20 2011-07-21 Samsung Electronics Co., Ltd. Stacked semiconductor package

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US5043794A (en) * 1990-09-24 1991-08-27 At&T Bell Laboratories Integrated circuit package and compact assemblies thereof
JP2901835B2 (ja) * 1993-04-05 1999-06-07 株式会社東芝 半導体装置
JP2944449B2 (ja) * 1995-02-24 1999-09-06 日本電気株式会社 半導体パッケージとその製造方法
JP2806357B2 (ja) * 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
JP2914342B2 (ja) * 1997-03-28 1999-06-28 日本電気株式会社 集積回路装置の冷却構造
US20060012031A1 (en) * 2002-07-30 2006-01-19 Fernandez Elstan A Heat dissipation device for integrated circuits
JP4534796B2 (ja) 2005-02-25 2010-09-01 セイコーエプソン株式会社 制御システム
JP2006295119A (ja) * 2005-03-17 2006-10-26 Matsushita Electric Ind Co Ltd 積層型半導体装置
US7196427B2 (en) * 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
US7297574B2 (en) * 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
JP2007158279A (ja) * 2005-12-09 2007-06-21 Hitachi Ltd 半導体装置及びそれを用いた電子制御装置
TWI357135B (en) * 2008-05-29 2012-01-21 Ind Tech Res Inst Chip package structure and manufacturing method th
JP2012033875A (ja) * 2010-06-30 2012-02-16 Canon Inc 積層型半導体装置
CN102522380B (zh) * 2011-12-21 2014-12-03 华为技术有限公司 一种PoP封装结构

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020024798A1 (en) * 1998-06-30 2002-02-28 Moden Walter L. Heat sink with alignment and retaining features
US6301779B1 (en) * 1998-10-29 2001-10-16 Advanced Thermal Solutions, Inc. Method for fabricating a heat sink having nested extended surfaces
US20040080036A1 (en) * 2002-10-24 2004-04-29 Advanced Semiconductor Engineering, Inc. System in package structure
US20050199993A1 (en) * 2004-03-10 2005-09-15 Jong-Joo Lee Semiconductor package having heat spreader and package stack using the same
CN1961421A (zh) * 2004-03-31 2007-05-09 斯塔克泰克集团有限公司 集成电路堆叠系统及方法
CN1835230A (zh) * 2005-03-17 2006-09-20 松下电器产业株式会社 叠层型半导体装置
CN101097906A (zh) * 2006-06-29 2008-01-02 海力士半导体有限公司 具有垂直形成的热沉的层叠封装
US20080048309A1 (en) * 2006-08-28 2008-02-28 Corisis David J Metal core foldover package structures, systems including same and methods of fabrication
CN101431033A (zh) * 2007-11-06 2009-05-13 南茂科技股份有限公司 多芯片堆栈封装方法
CN101937907A (zh) * 2009-06-29 2011-01-05 财团法人工业技术研究院 芯片堆叠封装结构及其制作方法
US20110176280A1 (en) * 2010-01-20 2011-07-21 Samsung Electronics Co., Ltd. Stacked semiconductor package

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012159533A1 (en) * 2011-05-26 2012-11-29 Huawei Technologies Co., Ltd. Thermally enhanced stacked package and method
WO2013091441A1 (zh) * 2011-12-21 2013-06-27 华为技术有限公司 一种PoP封装结构
US9318407B2 (en) 2011-12-21 2016-04-19 Huawei Technologies Co., Ltd. Pop package structure
US10431522B2 (en) 2013-08-12 2019-10-01 Samsung Electronics Co., Ltd. Thermal interface material layer and package-on-package device including the same
CN105453255A (zh) * 2013-08-12 2016-03-30 三星电子株式会社 热界面材料层及包括热界面材料层的层叠封装件器件
US10950521B2 (en) 2013-08-12 2021-03-16 Samsung Electronics Co., Ltd. Thermal interface material layer and package-on-package device including the same
CN104538375A (zh) * 2014-12-30 2015-04-22 华天科技(西安)有限公司 一种扇出PoP封装结构及其制造方法
CN104733411A (zh) * 2014-12-30 2015-06-24 华天科技(西安)有限公司 一种三维堆叠圆片级扇出PoP封装结构及其制造方法
CN106356344A (zh) * 2016-09-08 2017-01-25 华进半导体封装先导技术研发中心有限公司 基于三维堆叠封装的风冷散热结构及制造方法
CN106356344B (zh) * 2016-09-08 2019-03-05 华进半导体封装先导技术研发中心有限公司 基于三维堆叠封装的风冷散热结构及制造方法
CN107993988A (zh) * 2017-11-13 2018-05-04 芯原微电子(上海)有限公司 一种叠层封装结构及其制备方法
CN109166828A (zh) * 2018-08-30 2019-01-08 成都明杰科技有限公司 基于热应力减缓翘曲幅度的高密度集成电路封装
WO2024036765A1 (zh) * 2022-08-19 2024-02-22 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

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