CN102456716B - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN102456716B
CN102456716B CN201110337700.6A CN201110337700A CN102456716B CN 102456716 B CN102456716 B CN 102456716B CN 201110337700 A CN201110337700 A CN 201110337700A CN 102456716 B CN102456716 B CN 102456716B
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大西泰彦
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Fuji Electric Co Ltd
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Abstract

本发明涉及半导体器件。为了提供其中的外围区具有高击穿电压以及高抗感生表面电荷鲁棒性的半导体器件，使用大规模生产率的工序制造该半导体器件。一种半导体器件，其中，在垂直于具有高杂质浓度的n型半导体衬底的一个主面的方向上沉积的层状的n型漂移区和p型部区在沿着该一个主面的方向上形成交替相邻的平行pn层作为漂移层，以及有电流流动的有源区和包围有源区的外围区包括：平行pn层，其中p型部区具有浓度从表面向衬底侧减小的杂质浓度分布；n型表面区，其置于外围区中的平行pn层上；p型保护环，其相互分隔开地置于n型表面区上；以及导电场板，其位于p型保护环的内圆周侧和外圆周侧上并且电连接。

Description

半导体器件
技术领域
本发明涉及可应用于MOSFET(金属氧化物半导体场效应晶体管)、IGBT(绝缘栅双极型晶体管)、双极型晶体管等的具有高击穿电压和高电流容量的超结半导体器件，并且涉及该器件的制造方法。在以下描述中，超结半导体器件将表示其中的漂移层具有在“导通”状态中使电流流动而在“截止”状态中保持击穿电压的功能的半导体器件，在该漂移层中，在垂直于半导体衬底的主面的方向上沉积的柱状或层状的p型区和n型区在沿着该主面的方向上形成交替相邻的平行pn层。
背景技术
一般而言，半导体器件被分为横向半导体器件和纵向半导体器件，在横向半导体器件中电极仅在半导体衬底的一个表面上且电流沿着一主面流动，而在纵向半导体器件中电极在半导体衬底的两个表面上且电流在主面上的电极之间流动。在纵向半导体器件中，在器件的“导通”状态中漂移电流流动的方向与耗尽层因器件的“截止”状态中的反偏压而延伸的方向相同。在常规平面n沟道纵向MOSFET的情况下，高电阻率n-漂移层用于在MOSFET的“导通”状态中使漂移电流在垂直方向上流动，且在“截止”状态中耗尽以保持击穿电压。缩短高电阻率n-漂移层的电流路径(即，使高电阻率n-漂移层较薄)导致MOSFET的导通电阻降低的效果，这归因于n-漂移层中的电阻减小。然而，随着从p型基区和n-漂移层之间的pn结扩展的耗尽层宽度减小，电场强度快速达到硅的临界电场且击穿电压下降。另一方面，具有高击穿电压的n沟道纵向MOSFET具有厚n-漂移层，且该厚n-漂移层导致高导通电阻，且MOSFET的导通损耗增大。这种导通电阻和击穿电压之间的关系被称作折衷关系。已知这种折衷关系存在于诸如IGBT、双极型晶体管、或二极管等的半导体器件中。
同时，为了在纵向半导体器件中实现高击穿电压，该器件需要包围有电流流动的有源区的环形外围区。在没有外围区的情况下，难以实现高击穿电压，这是因为漂移层的外侧区中的电场强度变高，这导致击穿电压降低。另外，即使一开始维持了击穿电压，具有低抗表面电荷鲁棒性的器件难以保证击穿电压的可靠性。外围区上的表面电荷影响耗尽层的延伸，这导致击穿电压随着时间流逝而降低。在下文中，具有高抗表面电荷鲁棒性的半导体器件表示即使时间流逝也能维持初始击穿电压的半导体器件，即该半导体器件具有高可靠性。公知一种用于解决击穿电压降低的可靠性问题的半导体器件，该半导体器件具有连接至外围区中的正向和反向多晶硅场板的保护环。对于具有该类型外围区的半导体器件而言，即使在外围区中的表面上存在正电荷或负电荷时，对于表面附近的耗尽层延伸的影响减弱。因此，抑制击穿电压的降级且改善了抗表面电荷鲁棒性。
此外，就半导体材料的使用效率而言，外围区尽可能窄是所期望的，因为外围区是非有源区。关于该点，公开了一种半导体器件，该半导体器件中通过采用具有p型保护环、外围区的角隅部中第一场板和第二场板电位相同的配置，直部中的外围区的宽度减小而有源区的面积相应地增大(JP-A-2008-193043)。
此外，公开了一种半导体器件，在该半导体器件中通过采用具有形成在外围区中的多个保护环、置于各保护环的内圆周侧和外圆周侧中的绝缘膜上的多晶硅场板、以及连接保护环和场板的铝电极的配置，有可能使多个场板之间的间隔变窄(JP-A-2009-117715摘要和图1)。
然而，在JP-A-2009-117715(摘要和图1)中描述的MOSFET中，尽管在外围区有窄宽度的情况下有电场的高驰豫和高抗感生表面电荷鲁棒性，但是有必要在形成多晶硅场板之前形成p型保护环。在该情况下，在形成多晶硅栅和多晶硅场板之后形成p型基区和p型保护环的工序中，需要添加用于形成p型保护环的光刻和离子注入步骤。由于这些附加步骤不仅增加制造成本，而且因为易于发生p型保护环和多晶硅场板之间的未对准，这些附加步骤还成为电场驰豫能力的波动和劣化和低抗感生表面电荷鲁棒性的起因，因此尽可能没有此类附加步骤是所期望的。
另外，在JP-A-2003-115589中描述的MOSFET中，当具有低杂质浓度的n-型表面区形成在具有高杂质浓度的平行pn层上时，从衬底至n-型表面区的自动掺杂是不可避免的，这意味着难以控制n-型表面区的杂质浓度。由于掺杂有As的衬底尤其易于向外扩散，这对于n-型表面区杂质浓度的影响大，这是n-型表面区的杂质浓度波动的一个因素。当不控制n-型表面区杂质浓度时，不仅难以维持有关击穿电压的可靠性，而且难以维持初始击穿电压。
发明内容
鉴于以上内容，本发明的目的在于提供一种超结半导体器件，使用大规模生产率的工序来制造的该半导体器件具有外围区，该外围区具有高击穿电压和高抗感生表面电荷鲁棒性。
为了实现本发明的目的，本发明的一个方面是一种半导体器件，在该半导体器件中，在与具有高杂质浓度的n型半导体衬底11的主面垂直的方向上的柱状或层状的n型漂移区1和p型分隔区2在沿着该主面的方向上形成交替相邻的平行pn层Z作为漂移层，在该半导体器件中，该平行pn层Z用于使电流在“导通”状态中流动而在“截止”状态中保持击穿电压，且有电流流动的有源区100和包围有源区100并保持击穿电压的外围区包括平行pn层Z，该器件包括：平行pn层Z，其中平行pn层Z的p型分隔区2具有一种杂质浓度分布，使得杂质浓度从pn层Z的表面向半导体衬底11减小；n型表面区31，其在沿着该主面的方向上置于外围区200中的平行pn层上；两个或以上p型保护环32，其相互分隔开地置于n型表面区31上；以及导电场板33，其位于p型保护环32的内圆周侧和外圆周侧上并电连接至p型保护环32的表面。另外，外围区200中的平行pn层Z的pn层间距宽度比有源区100中的平行pn层Z的间距宽度小也是优选的。此外，置于外围区200中的平行pn层上的n型表面区31的厚度是有源区100中的平行pn层Z的厚度的1/3或更小也是优选的。此外，置于外围区200中的平行pn层上的n型表面区31的杂质浓度为从2×1014/cm3至8×1014/cm3范围中的任意杂质浓度是所期望的。
根据本发明，有可能提供一种半导体器件，其中使用大规模生产率的工序制造的该半导体器件的外围区具有高击穿电压和高抗感生表面电荷鲁棒性。
附图简述
图1是根据本发明半导体器件的实施例1的纵向MOSFET的平面图；
图2是距根据本发明的图1表面一半深度处的平面图；
图3是沿着根据本发明的图1的线A-A’切割的截面图；
图4是沿着根据本发明的图1的线B-B’切割的截面图；
图5是沿着根据本发明的图3的线C-C’切割的杂质浓度分布；
图6是沿着根据本发明的图3的线D-D’切割的杂质浓度分布；
图7是示出根据本发明半导体器件的实施例1的纵向MOSFET中的击穿电压与n型表面区的杂质浓度之间的关系的曲线图；
图8是根据本发明半导体器件的实施例2的纵向MOSFET的平面图；
图9是距根据本发明的图8的表面一半深度处的平面图；
图10是沿着根据本发明的图8的线A-A’切割的截面图；
图11是沿着根据本发明的图8的线B-B’切割的截面图；
图12是已知纵向MOSFET的平面图；
图13是距根据已知纵向MOSFET的图12的表面一半深度处的平面图；
图14是沿着根据已知纵向MOSFET的图12的线A-A’切割的截面图；
图15是沿着根据已知纵向MOSFET的图12的线B-B’切割的截面图；
图16是沿着根据已知纵向MOSFET的图12的线C-C’切割的杂质浓度分布；
图17是沿着根据已知纵向MOSFET的图12的线D-D’切割的杂质浓度分布；以及
图18是示出已知纵向MOSFET中的击穿电压与n型表面区的杂质浓度之间的关系的曲线图。
具体实施方式
下面，将参考附图对本发明的半导体器件相关的实施例进行描述。只要不背离本发明的范围，本发明不限于下文所描述的实施例的内容。尽管以下描述将用n型作为第一导电型、p型作为第二导电型来给出，但是有可能反转n型和p型。作n或p的后缀的+和-标记符号分别表示n型或p型杂质浓度为相对高浓度或低浓度。
实施例1
图1-2是根据实施例1的纵向超结MOSFET的四分之一平面视图。在图1中，为了方便理解，示出了最外侧表面的平行pn层Z、n型表面区31、n型沟道停止区13，以及有源区100的最外围的p基区3和p型保护环32a、32b和32c。P基区3中的用虚线表示的矩形区示出p基区3下方的平行pn层Z。在图1中未示出n型漂移层4、p+接触区5、n型源区6、栅绝缘膜7、栅电极8、层间绝缘膜9、源电极10、场绝缘膜15、沟道停止电极16、场板33等。这些在图3中示出。另外，在图3中提供了高浓度半导体衬底11、在高浓度半导体衬底11的正面上通过外延生长形成的具有均匀杂质浓度的n型缓冲层17、以及在高浓度半导体衬底的背面上形成的漏电极12。有源区100的平行pn层Z具有条形平面视觉形状，且有源区100的平行pn层Z的外侧被具有保护环32a、32b、32c的n型表面区31所包围，其中这些保护环32a、32b和32c相互分隔开地置于n型表面区31中，且n型表面区31的最外围被n型沟道停止区13和p型表面区14所包围。
同时，图2示出与主面平行的、在平行pn层的一半深度附近的平面的截面图的一部分(四分之一)。附图中示出，在平行pn层的一半深度附近，间距与有源区100的平行pn层的间距(间距：P1)相同的平行pn层也置于外围区200中。图3和4是沿着图1和2的线A-A’和B-B’切割的截面图。如图3所示，n型表面区31置于外围区200中的平行pn层上，且间距与有源区100的平行pn层Z的间距相同的平行pn层Z置于n型表面区31下方。平行pn层Z的p型分隔区2和22形成一种杂质浓度分布，在该杂质浓度分布中杂质浓度从正面侧向背面侧减小，且即使在n型表面区的杂质浓度增大时也以驰豫电场的方式工作(n型表面区31的厚度越小，对n型表面区31电场的驰豫效应越大。当n型表面区31的厚度小于平行pn层厚度的1/3时，对n型表面区31的电场的驰豫效果尤其大)。图5和6示出沿着图3所示线C-C’和D-D’切割的杂质浓度分布。P型分隔区2和22设置成它们的杂质浓度在正面侧处比相邻的n型漂移区1和2高，而相反，在背面侧处更低。同时，n型漂移区1和21形成与它们的深度无关的均匀的杂质浓度分布。
根据实施例1的纵向超结MOSFET呈现600V级的击穿电压，且各部分的尺寸、杂质浓度等具有以下种类的值。漂移层的厚度为44.0μm，有源区100的n型漂移区1的宽度为6.0μm，且杂质浓度为3.0×1015cm-3，p型分隔区2的宽度为6.0μm(平行pn层间距12.0μm)且杂质浓度为(从背面侧开始)2.4×1015cm-3、2.7×1015cm-3、3.0×1015cm-3、3.3×1015cm-3以及3.6×1015cm-3，外围区200的n型漂移区21的宽度为6.0μm，杂质浓度为3.0×1015cm-3，p型分隔区22的宽度为6.0μm(平行pn层间距12.0μm)且杂质浓度为(从背面侧开始)2.4×1015cm-3、2.7×1015cm-3、3.0×1015cm-3、3.3×1015cm-3、以及3.6×1015cm-3，且外围区200的n型表面区31的杂质浓度为5.0×1014cm-3、深度为5.0μm，该深度小于44.0μm的漂移层厚度的1/8，从而增大电场驰豫效果。
在此，将描述图12-15所示的已知结构中的外围区的抗感生电荷鲁棒性。图12是已知纵向MOSFET的平面图。图13是距图12的表面一半深度处的平面图。图14是沿着图12的线A-A’切割的截面图，但是与图1和图3的描述方式相同，在图14中还示出为了方便理解从图12中省略的部分。图15是沿着图12的线B-B’切割的截面图。由于当外围区200的场绝缘膜15的表面上感生出正电荷(正离子)时，难以使n型表面区31的耗尽层扩展，有源区100的外侧外围附近(p型分隔区)的电场增大，但是由于通过放置p型保护环32a、32b和32c使电场驰豫，即使在外围区200的场绝缘膜15的表面上感生出正电荷(正离子)也能够保持击穿电压。同时，在负电荷(负离子)的情况下，由于耗尽层更易于在具有p型保护环32a、32b和32c的n型表面区31中、以及在场板33与沟道停止电极16之间延伸，耗尽层扩展到外围区200的n型沟道停止区13中，但是由于通过沟道停止电极16防止n型沟道停止区13的贯穿到达(reach-through)，击穿电压能够得以维持。由于电场从有源区100的外侧外围向外围区200的外侧外围减小，随着保护环达到外围区200的外侧外围，保护环之间的距离增大是合乎需要的。
但是，为了获得高击穿电压和高可靠性，为了n型表面区中的电场驰豫，减小杂质浓度是必要的，且这使耗尽层更易于扩展。当增大杂质浓度时，不仅存在抗感生表面电荷鲁棒性降低的风险，还存在初始击穿电压降低的风险。图18示出当n型表面区31的厚度为5μm，且存在4个保护环时，击穿电压对n型表面区31的杂质浓度的依赖性的模拟结果。附图中的诸如+1e12/cm2的符号表示+1×1012cm-2。当n型表面区31中的杂质浓度为4×1014cm-3时，初始击穿电压(表面电荷Qss＝0cm-2)开始下降，且相对于表面电荷为+1×1012/cm-2(+标识符表示正电荷)处的初始击穿电压，击穿电压下降5％或更多。同时，从雪崩能力来看，外围区200的击穿电压通常被设计成比有源区的击穿电压高数个百分点，使得首先在有源区中达到临界电场强度，因此在一定程度上耐受外围区200的击穿电压下降。在已知示例中击穿电压下降的容限率为5％时，n型表面区31的杂质浓度为3×1014cm-3(图18中用虚线表示)或更低是必要的。但是，由于n型表面区31是通过外延生长形成的，因此在半导体衬底、外延生长炉等中自动掺杂是不可避免的，且实际上将杂质浓度维持在如3×1014cm-3或更低的低浓度中的杂质浓度控制是极其困难的。
同时，由于能够通过采用p型分隔区(其具有杂质浓度梯度)来增大实施例中的n型表面区31的杂质浓度，减小了自动掺杂的影响。这是因为正面侧上的杂质浓度更高的p型分隔区起到嵌入式保护环的作用，即使在n型表面区31的杂质浓度升高时也使n型表面区31的电场驰豫，且击穿电压得以维持。图7与图18的已知示例中一样示出了击穿电压对n型表面区的杂质浓度的依赖性的模拟结果。在图7中，当表面电荷Qss＝0cm-2时，在1×1014cm-3至9×1014cm-3的范围中观察不到初始击穿电压的下降，但是当表面电荷为+1×1012cm-3时(+标识符表示正电荷)，在2×1014cm-3或更低以及8×1014cm-3或更高时击穿电压下降5％或更多。即，当杂质浓度在2×1014cm-3至8×1014cm-3的范围中时，击穿电压的下降保持为小于5％。与已知示例中的方式一样，当击穿电压下降的容限率为5％时，有可能在实施例1中安排成：即使n型表面区31的杂质浓度从3×1014cm-3显著增大至约8×1014cm-3时，也不发生击穿电压的下降。因此，由于自动掺杂的影响减小，能够提供具有高可靠性和大规模生产率(几乎没有击穿电压波动)的外围区200。
实施例2
根据实施例2的超结MOSFET在图8、9、10和11中示出。图8和9分别示出MOSFET的平面图和平行pn层的一半深度附近的一部分(四分之一)的截面图。图10和11分别是沿着图8和9的线A-A’和B-B’切割的截面图。在图8中，与图1一样，为了方便理解，省略了表面部分的一部分。实施例1和实施例2之间的不同之处在于，外围区200中的平行pn层的间距比有源区100中的平行pn层的间距小，且具有较小间距的外围区200中的平行pn层的、包围有源区100中的平行pn层的条带的取向垂直于有源区100中的平行pn层的取向，且各导电场板33连接至p型保护环32a、32b和32c。由于n型表面区31的电场更容易被具有杂质浓度梯度的p型分隔区22来驰豫，因此当平行pn层的间距P2减小时，容易获取更高的击穿电压。
同时，由于连接至p型保护环32a、32b和32c的导电场板33起到收集感生额外电荷的作用，以及缓和电场并抑制p型保护环32a、32b和32c的耗尽层扩展的作用，它还可起到抑制击穿电压归因于粘附到场绝缘膜15的电荷的波动。假若外围区200中的平行pn层的p型分隔区22的杂质浓度在正面侧高而在背面侧低，可获得与实施例1中同样的、高抗感生表面电荷鲁棒性的优势。
如上所述，在实施例1中，超结MOSFET的结构为平行pn层的p型分隔区(其中杂质浓度从正面侧向背面侧减小)置于超结MOSFET的外围区200中的n型表面区下方，这可显著改善导通电阻和击穿电压之间的折衷关系。由于通过采用具有这种结构的超结MOSFET来增大n型表面区的杂质浓度，因此n型表面区中的由自动掺杂造成的杂质浓度变化减小。由于n型表面区中的杂质浓度变化减小，能够提供具有高击穿电压的高可靠性外围区200。

Claims (3)

1.一种半导体器件，其特征在于
沿着垂直于具有高杂质浓度的第一导电型半导体衬底的一个主面的方向上沉积的柱状或层状的第一导电型半导体区和第二导电型半导体区在沿着所述主面的方向上形成交替相邻的平行pn层作为漂移层，其中
所述平行pn层配置成在“导通”状态中使电流流动而在“截止”状态中维持击穿电压，且有电流流动的有源区和包围所述有源区并维持击穿电压的外围区包括所述平行pn层，
所述器件包括：
平行pn层，其中所述平行pn层的所述第二导电型半导体区具有杂质浓度从所述pn层的表面向所述半导体衬底侧减小的杂质浓度分布；
第一导电型表面区，其置于所述外围区中的所述平行pn层上；
两个或更多个第二导电型保护环，其相互分隔开地置于所述第一导电型表面区上；以及
导电场板，其置于所述保护环的内圆周侧和外圆周侧的每一侧上，并电连接至所述保护环中的每一个环的所述表面，
置于所述外围区中的所述平行pn层上的所述第一导电型表面区的厚度是所述有源区中的所述平行pn层厚度的1/3或更小。
2.如权利要求1所述的半导体器件，其特征在于，
所述外围区中的所述平行pn层的所述pn层间距宽度比所述有源区中的所述平行pn层的所述pn层间距宽度小。
3.如权利要求1或2所述的半导体器件，其特征在于，
置于所述外围区中的所述平行pn层上的所述第一导电型表面区的杂质浓度为从2×1014/cm3至8×1014/cm3范围中的任一杂质浓度。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5719167B2 (ja) * 2010-12-28 2015-05-13 ルネサスエレクトロニクス株式会社 半導体装置
JP2012204811A (ja) * 2011-03-28 2012-10-22 Sony Corp 半導体装置
CN104009072A (zh) * 2013-02-25 2014-08-27 中国科学院微电子研究所 一种绝缘栅双极型晶体管及其制作方法
JP6324805B2 (ja) * 2014-05-19 2018-05-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6375176B2 (ja) * 2014-08-13 2018-08-15 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6468824B2 (ja) * 2014-12-04 2019-02-13 ローム株式会社 半導体装置
US9515199B2 (en) 2015-01-02 2016-12-06 Cree, Inc. Power semiconductor devices having superjunction structures with implanted sidewalls
US9825128B2 (en) * 2015-10-20 2017-11-21 Maxpower Semiconductor, Inc. Vertical power transistor with thin bottom emitter layer and dopants implanted in trenches in shield area and termination rings
KR102286014B1 (ko) * 2015-11-23 2021-08-06 에스케이하이닉스 시스템아이씨 주식회사 개선된 온저항 및 브레이크다운전압을 갖는 고전압 집적소자
TWI581425B (zh) * 2015-11-24 2017-05-01 Macroblock Inc And a power semiconductor device having an edge terminal structure having a gradation concentration
CN105470242B (zh) * 2016-01-21 2018-05-08 上海华虹宏力半导体制造有限公司 密封环及具有密封环的半导体结构
US10164078B2 (en) * 2016-03-18 2018-12-25 Infineon Technologies Americas Corp. Bipolar semiconductor device with multi-trench enhancement regions
US11075264B2 (en) 2016-05-31 2021-07-27 Cree, Inc. Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods
JP6740759B2 (ja) * 2016-07-05 2020-08-19 株式会社デンソー 炭化珪素半導体装置およびその製造方法
CN106571394B (zh) * 2016-11-01 2018-05-11 杭州士兰微电子股份有限公司 功率器件及其制造方法
US9929284B1 (en) 2016-11-11 2018-03-27 Cree, Inc. Power schottky diodes having local current spreading layers and methods of forming such devices
JP6870516B2 (ja) * 2017-07-18 2021-05-12 富士電機株式会社 半導体装置および半導体装置の製造方法
DE102018132435B4 (de) * 2018-12-17 2021-01-21 Infineon Technologies Austria Ag Verfahren zum Herstellen eines Superjunction-Transistorbauelements
US11171248B2 (en) * 2019-02-12 2021-11-09 Semiconductor Components Industries, Llc Schottky rectifier with surge-current ruggedness
CN111584623A (zh) * 2020-06-02 2020-08-25 吉林华微电子股份有限公司 一种双极结型晶体管器件及其制造方法、电子产品

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629552A (en) * 1995-01-17 1997-05-13 Ixys Corporation Stable high voltage semiconductor device structure
US7642597B2 (en) * 2006-11-14 2010-01-05 Kabushiki Kaisha Toshiba Power semiconductor device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4843843B2 (ja) 2000-10-20 2011-12-21 富士電機株式会社 超接合半導体素子
JP4785335B2 (ja) * 2001-02-21 2011-10-05 三菱電機株式会社 半導体装置およびその製造方法
JP3731520B2 (ja) * 2001-10-03 2006-01-05 富士電機デバイステクノロジー株式会社 半導体装置及びその製造方法
JP4304433B2 (ja) 2002-06-14 2009-07-29 富士電機デバイステクノロジー株式会社 半導体素子
JP4524539B2 (ja) 2002-08-13 2010-08-18 富士電機システムズ株式会社 半導体素子
JP3634830B2 (ja) * 2002-09-25 2005-03-30 株式会社東芝 電力用半導体素子
US7169634B2 (en) * 2003-01-15 2007-01-30 Advanced Power Technology, Inc. Design and fabrication of rugged FRED
JP5188037B2 (ja) * 2006-06-20 2013-04-24 株式会社東芝 半導体装置
JP2008091450A (ja) * 2006-09-29 2008-04-17 Toshiba Corp 半導体素子
US8008734B2 (en) 2007-01-11 2011-08-30 Fuji Electric Co., Ltd. Power semiconductor device
JP5205856B2 (ja) 2007-01-11 2013-06-05 富士電機株式会社 電力用半導体素子
JP4620075B2 (ja) * 2007-04-03 2011-01-26 株式会社東芝 電力用半導体素子
JP4356764B2 (ja) * 2007-04-18 2009-11-04 株式会社デンソー 炭化珪素半導体装置
JP2009117715A (ja) 2007-11-08 2009-05-28 Toshiba Corp 半導体装置及びその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629552A (en) * 1995-01-17 1997-05-13 Ixys Corporation Stable high voltage semiconductor device structure
US7642597B2 (en) * 2006-11-14 2010-01-05 Kabushiki Kaisha Toshiba Power semiconductor device

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