CN102420202B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN102420202B
CN102420202B CN201110061664.5A CN201110061664A CN102420202B CN 102420202 B CN102420202 B CN 102420202B CN 201110061664 A CN201110061664 A CN 201110061664A CN 102420202 B CN102420202 B CN 102420202B
Authority
CN
China
Prior art keywords
insulating barrier
semiconductor device
semiconductor element
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110061664.5A
Other languages
English (en)
Other versions
CN102420202A (zh
Inventor
丸谷尚一
岩见康成
近井智哉
高桥知子
山方修武
三次真吾
陈崇浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rely On Technology Japan Co
Original Assignee
J Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by J Devices Corp filed Critical J Devices Corp
Publication of CN102420202A publication Critical patent/CN102420202A/zh
Application granted granted Critical
Publication of CN102420202B publication Critical patent/CN102420202B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2101—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/215—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/22—Structure, shape, material or disposition of high density interconnect preforms of a plurality of HDI interconnects
    • H01L2224/221—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24146—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供一种提高在半导体元件上形成的布线的连接性的合格率、且在支持板上安装半导体元件时无需高精度的半导体装置及其制造方法。半导体装置的特征在于具备：支持板；载置在支持板上并具有形成了多个第一电极的电路元件面的半导体元件；覆盖半导体元件的电路元件面并具有将多个第一电极露出的多个第一开口的第一绝缘层；覆盖形成有第一绝缘层的半导体元件的侧部和支持板的上部的第二绝缘层；和与第二绝缘层的上部和第一绝缘层相接触地形成并与多个第一电极电连接的布线层。根据本发明的半导体装置的制造方法，可以制造减轻热应力导致的支持板翘曲、提高布线连接性的合格率、且无需在开口形成时所要求的半导体元件的高安装精度的半导体装置。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置，特别地涉及一种具有将载置于支持板上的半导体元件树脂密封的结构的半导体装置及其制造方法。
背景技术
作为现有的具有树脂密封结构的半导体装置的制造方法，一直使用以下方法：在将单片化了的半导体元件载置于支持板上之后，在各个半导体元件上以及支持板上涂敷绝缘性树脂而形成绝缘层，将在半导体元件的电路面上形成的电极部上的树脂去除而形成开口部。
这种现有的半导体装置的制造方法的一个例子如专利文献1所示。在专利文献1中记载了这样的例子：将多个单片化了的裸片粘结在基座上，然后利用由绝缘性树脂等构成的第一材料层将基座上的多个裸片之间填充，在多个裸片上以及第一材料层上形成第二材料层，以及将多个裸片的电极焊盘上的第二材料层部分地刻蚀而形成开口。
【专利文献】
专利文献1：日本特开2005-167191号公报
发明内容
(发明所要解决的问题)
但是，根据这种制造方法，由于在涂敷绝缘性树脂的制造工序中的热应力，在支持板与半导体元件的粘结面处会因CTE(热膨胀率)差而使支持板产生翘曲，导致随后在绝缘性树脂上形成的布线连接部的开口位置精度降低这一问题。另外，随着近年来半导体元件尺寸的减小，为了在半导体元件电路面上形成将电极部露出的微小开口，在将单片化的半导体元件载置于支持板上时需要高的安装精度，由于所述开口形成的难度，也存在半导体装置的制造合格率降低的问题。
本发明是鉴于上述问题而提出的，其目的在于实现一种减轻支持板的翘曲所造成的影响、提高开口位置精度、且无须开口形成时所要求的半导体元件的高安装精度的半导体装置的制造方法，提高半导体装置制造时的合格率。
(解决问题的手段)
本发明的一个实施方式的半导体装置的特征在于具备：支持板；载置在支持板上并具有形成了多个第一电极的电路元件面的半导体元件；覆盖半导体元件的电路元件面并具有将多个第一电极露出的多个第一开口的第一绝缘层；覆盖形成有第一绝缘层的半导体元件的侧部以及支持板的上部的第二绝缘层；以及被形成为与第二绝缘层的上部以及第一绝缘层相接触并与多个第一电极电连接的布线层。
本发明的一个实施方式的半导体装置也可以具备形成于布线层上并具有将布线层的一部分露出的多个第二开口的第三绝缘层。
本发明的一个实施方式的半导体装置的制造方法的特征在于包含如下步骤：在半导体基板上形成各自具有包含多个第一电极的电路元件面的多个半导体元件；在形成了多个半导体元件的半导体基板上形成第一绝缘层；去除第一绝缘层的一部分，来形成将多个半导体元件的多个第一电极露出的多个第一开口；切断半导体基板，来将多个半导体元件单片化；将单片化了的多个半导体元件的电路元件面朝上，将多个半导体元件载置于支持板上；形成覆盖多个半导体元件的各个侧部以及支持板上的第二绝缘层；形成与所述第二绝缘层的上部以及第一绝缘层相接触并与多个半导体元件的多个第一电极电连接的布线层。
另外，本发明的一个实施方式的半导体装置的制造方法可以是包含如下步骤的方法：在布线层的上部形成第三绝缘层；去除第三绝缘层的一部分，来形成将所述布线层的一部分即多个第二电极露出的多个第二开口；在形成于第三绝缘层的多个第二开口处形成与多个第二电极电连接的多个外部连接用电极；以及切断支持板来将多个半导体元件单片化。
本发明的一个实施方式的层叠型半导体装置的特征在于具备：形成于半导体装置上并具有将布线层的一部分或多个第二电极露出的多个第三开口的第四绝缘层；隔着第四绝缘层层叠在所述半导体装置上的另一个半导体装置；形成在第四绝缘层的多个第三开口内并将半导体装置的布线层或多个第二电极部与另一个半导体装置的布线层电连接的多个导电层；以及形成在半导体装置与第四绝缘层之间并至少覆盖半导体装置的上表面的一部分的金属层。
本发明的一个实施方式的层叠型半导体装置可以具备：半导体装置；形成于半导体装置上并具有将布线层的一部分或多个第二电极露出的多个第三开口的第四绝缘层；隔着第四绝缘层层叠在半导体装置上的另一个半导体装置；形成在第四绝缘层的多个第三开口内并将半导体装置的布线层或多个第二电极部与另一个半导体装置的布线层电连接的多个导电层。
(发明的效果)
根据本发明，具有树脂密封结构的半导体装置中，可以降低制造工序中的热应力，可以减轻支持板翘曲的影响并提高开口的精度，并且无需为开口形成而要求的半导体元件的高安装精度，由此可以提高半导体装置的制造过程的合格率。
附图说明
图1中，(A)是表示本发明的实施方式1的半导体装置的示意性结构的俯视图，(B)是图1(A)的A-A′线处的截面图。
图2中，(A)是表示本发明的实施方式2的半导体装置的示意性结构的俯视图；(B)是图2(A)的B-B′线处的截面图。
图3A中，(A-1)是表示本发明的半导体装置的制造工序的截面图；(A-2)是表示本发明的半导体装置的制造工序的俯视图。
图3B中，(B-1)是表示本发明的半导体装置的制造工序的截面图；(B-2)是表示本发明的半导体装置的制造工序的俯视图。
图3C中，(C-1)是表示本发明的半导体装置的制造工序的截面图；(C-2)是表示本发明的半导体装置的制造工序的俯视图。
图3D中，(D-1)是表示本发明的半导体装置的制造工序的截面图；(D-2)是表示本发明的半导体装置的制造工序的俯视图。
图3E中，(E-1)是表示本发明的半导体装置的制造工序的截面图；(E-2)是表示本发明的半导体装置的制造工序的俯视图。
图3F中，(F-1)是表示本发明的半导体装置的制造工序的截面图；(F-2)是表示本发明的半导体装置的制造工序的俯视图。
图3G中，(G-1)是表示本发明的半导体装置的制造工序的截面图；(G-2)是表示本发明的半导体装置的制造工序的俯视图。
图3H中，(H-1)是表示本发明的半导体装置的制造工序的截面图；(H-2)是表示本发明的半导体装置的制造工序的俯视图。
图3I中，(I-1)是表示本发明的半导体装置的制造工序的截面图；(I-2)是表示本发明的半导体装置的制造工序的俯视图。
图3J中，(J-1)是表示本发明的半导体装置的制造工序的截面图；(J-2)是表示本发明的半导体装置的制造工序的俯视图。
图4是表示本发明的实施方式3的半导体装置的示意性结构的截面图。
图5中，(A)是本发明的实施方式4的半导体装置的截面图；(B)是本发明的实施方式5的半导体装置的截面图；(C)是本发明的实施方式6的半导体装置的截面图。
(附图标记说明)
100、200、300、400、500：半导体装置；1：支持板；3：半导体元件
13：半导体基板；5：第一电极；7：第一绝缘层；9：第一开口
17：第二绝缘层；20：布线层；27：第三绝缘层；15：第二电极
19：第二开口；30、40：外部连接用电极；600、700：层叠型半导体装置
23：另一个半导体元件；37：第四绝缘层；29：第三开口
50：导电层；60：金属层
具体实施方式
以下参照附图说明本发明的实施方式。注意，在实施方式中，对相同的构成要素附加相同的附图标记，并省略实施方式间的重复说明。
(实施方式1)
参照附图说明实施方式1的本发明的半导体装置。
[半导体装置的结构]
图1(A)和图1(B)是表示实施方式1的半导体装置100的示意性结构的图。图1(B)是表示半导体装置100的示意性结构的俯视图，图1(A)是从图1(B)所示的A-A′线观察的半导体装置100的截面图。在图1(A)和图1(B)中，半导体装置100具备：支持板1；载置在支持板1上并具有形成了多个第一电极5的电路元件面的半导体元件3；覆盖半导体元件3的电路元件面并具有将多个第一电极5露出的多个第一开口9的第一绝缘层7；覆盖支持板1的上部并覆盖形成有第一绝缘层7的半导体元件3的侧部的第二绝缘层17；以及被形成为与第二绝缘层17的上部和第一绝缘层7相接触并与多个第一电极5电连接的布线层20。
实施方式1的半导体装置100的支持板1可以由树脂或金属制成。所述支持板1的形状和大小并无特别限制。例如，支持板1的形状可以是矩形或圆形。支持板1的材料优选例如树脂等有机类材料、可以进行平板加工的金属(例如SUS、铜、铝等)，但也可以使用玻璃、硅等。
在实施方式1的半导体装置100的半导体元件3的表面具有元件电路面。半导体元件3的厚度例如可以是50μm左右，但半导体元件3的厚度小于等于100μm。半导体元件3在支持板1上通过粘结剂(未图示)等固定在支持板1上。粘结剂的材料例如可以使用环氧类的膜或糊剂，但其它材料只要是可以将半导体元件3固定在支持板1上的材料即可以使用。
形成在半导体元件3上的第一绝缘层7的材料例如可以使用环氧类树脂或聚酰亚胺类树脂等，但不限于此，只要是保护半导体元件3上的电路面且具有绝缘性的材料即可。第一绝缘层7的厚度为5μm至20μm左右，例如可以是10μm。只要是可以在第一绝缘层7上设置开口的厚度即可，也可以是大于等于20μm的厚度，但第一绝缘层7的厚度一般小于等于30μm。
对于形成在半导体元件3之间以及支持板1上的第二绝缘层17的高度与第一绝缘层7的高度之间的关系没有特别限制。第二绝缘层17的材料可使用作为第一绝缘层7的材料所列举的那些材料。另外，第二绝缘层17的材料可以与第一绝缘层7的材料相同，也可以使用不同的材料。
布线层20与形成在半导体元件3上的多个第一电极5电连接。布线层20的材料例如可使用铜、银等，但不限于此，只要是具有导电性的材料即可，也可以使用其他材料。此外，形成在半导体元件3上的布线结构也不限于图1(B)所示的结构，例如也可以是多个布线与形成在半导体元件3上的共用外部连接端子即球焊盘相连接的布线结构。
根据本发明的实施方式1，由于在半导体元件上形成第一绝缘层的工序不在支持板上进行，因此与在支持板上形成第一绝缘层和第二绝缘层的现有制造方法中相比，不受第一绝缘层形成工序中产生的热应力的影响，可以减轻在该工序中支持板的翘曲的影响，因此可高精度地形成开口。其结果是，可以提高半导体元件上的电极部的密度并提高连接管脚的数量。另外，根据本发明的实施方式1，可以获得如下效果，即，由独立的工序制造在半导体元件3上的第一绝缘层7和在多个半导体元件3之间的第二绝缘层17并控制各个绝缘层的高度，由此可以防止因绝缘层彼此的高低差造成的布线断裂等，可以制造具有连接可靠性的布线层20。
(实施方式2)
参照附图说明实施方式2的本发明的半导体装置200。本发明的实施方式2说明了在所述实施方式1的半导体装置100上进一步形成具有多个第二开口19的第三绝缘层27的例子。
图2是表示实施方式2的半导体装置200的示意性结构的截面图。注意，实施方式2的半导体装置200的特征是，形成具有多个第二开口19的第三绝缘层27，其他结构与实施方式1中说明的结构相同，因此省略对其他结构的说明。
如图2(A)所示，实施方式2的半导体装置200的特征是，在布线层20上形成具有多个第二开口19的第三绝缘层27。第三绝缘层27的材料可以使用作为第一绝缘层7的材料所列举的材料。另外，第三绝缘层27的材料可以与第一绝缘层7的材料或第二绝缘层17的材料全部相同，也可以是仅一部分相同，或可以分别使用不同的材料。
其他结构和制造方法与实施方式1相同。根据本发明的实施方式2，可以获得如下效果：在利用第三绝缘层27来保护布线层20的同时，也可以确保外部电极，使半导体装置与外部装置的连接成为可能。
(实施方式3)
参照附图说明实施方式3的本发明的半导体装置300的结构和制造方法。本发明的实施方式3说明了在所述实施方式2的半导体装置200中，在具有将第二电极15露出的多个第二开口19的第三绝缘层27上形成外部连接用电极30，并进一步单片化为单个的半导体装置300的例子。
图3J的(J-1)和图3J的(J-2)是表示实施方式3的半导体装置300的示意性结构的截面图和俯视图。注意，实施方式3的半导体装置300的特征是，在所述实施方式2的半导体装置200中，在具有将第二电极露出的多个第二开口的第三绝缘层27上形成外部连接用电极30，并进一步单片化为单个的半导体装置，其他结构与实施方式2中说明的结构相同，因此省略对其他结构的说明。
如图3J的(J-1)所示，实施方式3的半导体装置300的特征是，在所述实施方式2的半导体装置200中，在具有将第二电极15(参照图3H的(H-1))露出的多个第二开口19的第三绝缘层27上形成外部连接用电极30，并进一步单片化为单个的半导体装置300。外部连接用电极30的材料可以是如图3I的(I-1)和图3I的(I-2)所示的焊料球，但不限于此，只要是导电性的结构件即与第二电极15电连接的结构件即可，也可以由其他形状或材料构成。
[半导体装置的制造方法]
参照附图说明实施方式3的半导体装置300的制造方法。图3A的(A-1)至图3J的(J-2)分别表示了实施方式3的本发明半导体装置300的各个制造过程。注意，由于在实施方式3的半导体装置300的制造过程中分别制造本发明实施方式1和实施方式2的半导体装置100、200，因此在此一并说明实施方式1和实施方式2的半导体装置的制造方法。
首先，如图3A的(A-1)所示，在形成有由硅或化合物半导体等构成的半导体电路和多个第一电极5的半导体基板13(半导体晶片)的整个上表面涂敷要成为第一绝缘层7的材料的树脂等。涂敷树脂等的方法例如可以使用旋转涂敷法、印刷法、喷墨法、点胶法等，但并不限于这些方法，只要是可以将第一绝缘层7控制得具有一定厚度的方法即可，也可以是其他涂敷方法。接着如图3B的(B-1)所示，通过仅将涂敷在半导体基板13的上表面上的第一绝缘层7中的在多个第一电极5上的部分去除，形成多个第一开口9。作为具有这种第一开口9的第一绝缘层7的形成方法，例如可以使用将感光性树脂涂敷在包含多个第一电极5上部的半导体基板13的整个上表面上之后，用光刻技术在多个第一电极5上进行部分地曝光来形成开口的方法。不过，在半导体基板13的整个上表面上形成第一绝缘层7之后再形成多个第一开口9的方法并不限于这种使用光刻技术的方法，只要是可以在第一绝缘层7上形成开口的方法即可，其他方法也可以。
图3A的(A-1)和图3B的(B-1)表示了首先将第一绝缘层7涂敷在包含多个第一电极5的上方在内的半导体基板13的整个上表面上之后，形成将第一电极5的上部露出的多个第一开口9的制造工序，但具有多个第一开口9的第一绝缘层7的形成方法并不限于这种制造工序。作为形成第一开口9的其它方法例如可以是：在将第一绝缘层7形成于半导体基板13上时，预先仅在除了多个第一电极5的上部以外的半导体基板13的上表面上涂敷要成为第一绝缘层7的材料的树脂等，然后对在除了多个第一电极5的上部以外的半导体基板13的上表面上涂敷的树脂等进行后焙烤，来形成在多个第一电极5上具有多个第一开口9的第一绝缘层7。
如图3C的(C-1)和图3C的(C-2)所示，在半导体基板13上形成具有多个第一开口9的第一绝缘层7之后，用划片机或切片机将半导体基板13单片化成单个的半导体元件3。
接着，如图3D的(D-1)和图3D的(D-2)所示，将单片化的半导体元件3搭载在支持板1上。通过粘结剂等将单片化的半导体元件3以大致相等间距的方式固定在支持板1上。
然后，如图3E的(E-1)和图3E的(E-2)所示，将载置于支持板1上的多个半导体元件3之间填充，并形成覆盖支持板1的上表面的第二绝缘层17。第二绝缘层17的形成方法例如可以使用旋转涂敷法、印刷法、喷墨法、点胶法等，但并不限于这些方法，只要是可以将第二绝缘层17控制得具有一定厚度的方法即可，可以是其他涂敷方法。另外，第二绝缘层17的制造方法可以与所述第一绝缘层7的制造方法相同，也可以不同。
再者，如图3F的(F-1)和图3F的(F-2)所示，在第一绝缘层7、第二绝缘层17的上部以及多个第一电极5上形成布线层20。所述布线层20例如可以通过镀敷法、印刷法或喷墨法形成。布线层20与半导体元件3上的多个第一电极5电连接。利用上述制造工序，形成实施方式1的本发明半导体装置100。
接着，如图3G的(G-1)和图3G的(G-2)所示，在包含布线层20的上方在内的支持板1的整个上表面涂敷要成为第三绝缘层27的材料的树脂等。涂敷树脂等的方法例如可以使用旋转涂敷法、印刷法、喷墨法、点胶法等，但并不限于这些方法，只要是可以将第三绝缘层27控制得具有一定厚度的方法即可，也可以是其他涂敷方法。接着，如图3H的(H-1)所示，通过仅将涂敷在包含布线层20的支持板1的上表面上的第三绝缘层27中的在所述布线层20的一部分即多个第二电极15上的部分去除，来形成多个第二开口19。具有这种第二开口19的第三绝缘层27的形成方法例如可以使用在包含布线层20的上部在内的支持板1的整个上表面上涂敷感光性树脂之后，利用光刻技术在多个第二电极15上进行部分地曝光来形成开口的方法。不过，在包含布线层20在内的支持板1的整个上表面上形成第三绝缘层27之后再形成多个第二开口19的方法并不限于这种使用光刻技术的方法，只要是可以在第三绝缘层27上形成开口的方法即可，也可以是其他方法。通过上述制造工序，形成实施方式2的本发明半导体装置200。
再者，如图3I的(I-1)和图3I的(I-2)所示，可以在由第三绝缘层27上的多个第二开口19露出的多个第二电极15上，分别形成外部连接用电极30。外部连接用电极30可以是如图3I的(I-1)和图3I的(I-2)所示的焊料球，但并不限于此，只要是具有导电性且与第二电极15电连接的结构件即可，也可以由其他形状或材料构成。外部连接用电极30例如通过焊接法、镀敷法、印刷法等形成在第二电极15上。
接着，如图3J的(J-1)和图3J的(J-2)所示，用划片机或切片机将在支持板1上一起地形成的多个半导体元件3的每个分别切断，来制造单个的半导体装置。切断半导体元件3的间隔一般为0.1mm到0.5mm左右，但不限于此。通过这些制造过程来制造实施方式3的本发明半导体装置300。
(实施方式4)
参照附图说明实施方式4的本发明半导体装置400。本发明的实施方式4说明了在所述实施方式3的半导体装置300中，外部连接用电极40由导电性结构件构成的结构例。
图4为表示实施方式4的半导体装置400的示意性结构的截面图。此外，实施方式4的半导体装置400的特征是，外部连接用电极40由导电性结构件构成，其他结构与实施方式3中说明的结构相同，因此省略对其他结构、半导体装置400的制造方法等的相关图示和说明。
如图4所示，实施方式4的半导体装置400的特征是，外部连接用电极40由导电性结构件构成。配置于本发明半导体装置上的外部连接用电极40的形状不限于图3I、图3H所示的焊料球30，也可以是如图4所示的圆柱形的结构件40。另外，外部连接用电极40的形状除此之外也可以是柱状、球状、突起形状、针状等。此外，关于外部连接用电极40的配置位置，只要是外部连接用电极40与布线层20的一部分即第二电极15电连接即可，也可以如图4所示是布线层20的上部。
根据本发明的实施方式4，通过使用导电性结构件作为外部连接用电极40，可以获得提高了电极相互间的电连接性的半导体装置。
(实施方式5)
参照附图说明实施方式5的本发明半导体装置500。实施方式5的本发明的半导体装置500说明了通过将所述实施方式1至4的半导体装置并排地配置多个，来制成可以搭载多个半导体元件3的多芯片结构的半导体装置。
图5(A)是表示实施方式5的半导体装置500的示意性结构的图。此外，实施方式5的半导体装置500的特征是，将实施方式1至4的半导体装置并排地配置多个，其他结构与实施方式1至4中说明的结构相同，因此省略对其他结构、半导体装置的制造方法的相关说明。
如图5(A)所示，在实施方式5的半导体装置上搭载至少一个半导体元件3。图5(A)表示的是与半导体元件3并排地搭载了另一个半导体元件23的例子，但实施方式5的半导体装置的构造并不限于此，例如也可以形成半导体元件以外的电子部件或电极等结构件来代替另一个半导体元件23。
根据本发明的实施方式5，可获得并排地具备多个部件的多芯片结构的半导体装置。
(实施方式6)
参照附图说明实施方式6的本发明的层叠型半导体装置600。本发明的实施方式6说明了通过将所述实施方式1至4的半导体装置多个层叠地配置，来制成可以搭载多个半导体元件的结构的立体/层叠型半导体装置。注意，实施方式6的层叠型半导体装置600的特征是，通过将实施方式1至4的半导体装置多个层叠地配置，来制造可以搭载多个半导体元件的结构的立体/层叠型半导体装置，其他结构与实施方式1至4中说明的结构相同，因此省略对其他结构、半导体装置600的制造方法等的相关图示和说明。
如图5(B)所示，在实施方式6的层叠型半导体装置600上搭载至少一个半导体元件3。就具体的层叠构造进行说明。首先，在实施方式1的半导体装置100上形成第四绝缘层37，接着在第四绝缘层37上形成将第二电极15或布线层20的其他的一部分露出的多个第三开口29。注意，作为制造具有所述多个第三开口29的第四绝缘层37的方法，可以与第一、第三绝缘层7、27同样地，预先仅在第三开口29部分以外的部分涂敷要成为第四绝缘层37的材料的树脂等，然后进行后焙烤，来形成具有多个第三开口29的第四绝缘层37；或者可以是在包括第三开口29部分在内的半导体装置的整个上表面上涂敷第四绝缘层37的材料，然后仅将第三开口29上的第四绝缘层37部分地去除，来形成多个第三开口29。另外，作为第四绝缘层37的材料，可使用作为第一至第三绝缘层27的材料所列举的那些材料。另外，第一至第四绝缘层7、37的各个材料可以全部相同，可以仅一部分相同，也可以分别不同。
接着，在第四绝缘层37上载置另一个半导体元件23，形成与第三开口29内的第二电极15或布线层20的其他的一部分电连接的导电层50，导电层50与另一个半导体装置上的电极电连接。另外，另一个半导体元件23与第四绝缘层37之间用树脂密封。作为所述导电层50的制造方法，例如可以使用通孔镀敷等镀敷法。
图5(B)图示的是在半导体元件3上层叠另一个半导体元件23的例子，但实施方式6的层叠型半导体装置的结构并不限于此，例如可以层叠半导体元件以外的电子部件来代替另一个半导体元件23。
根据本发明的实施方式5，可以获得通过层叠而具备多个部件的层叠结构的半导体装置，可以缩小安装面积。
(实施方式7)
参照附图说明实施方式7的本发明的层叠型半导体装置700。本发明的实施方式7说明了在所述实施方式6的层叠型半导体装置中，半导体元件3与绝缘层4之间具有金属层60的例子。注意，实施方式7的层叠型半导体装置700的特征是，在实施方式6的层叠型半导体装置中，在半导体元件3与第四绝缘层37之间具有金属层60，其他结构与实施方式6中说明的结构相同，因此省略对其他结构、层叠型半导体装置700的制造方法等的相关图示和说明。
如图5(C)所示，在实施方式7的半导体装置700上搭载至少一个半导体元件3。就具体的层叠构造进行说明。首先，在实施方式1的半导体装置100上形成第四绝缘层37，再在第四绝缘层37上形成将第二电极15或布线层20的其他的一部分露出的多个第三开口29，在这一点上与实施方式6相同。
接着，在第四绝缘层37上形成覆盖半导体元件3的上表面的至少一部分的金属层60。在其上载置另一个半导体元件23，并形成与第三开口29内的第二电极15或布线层20的其他的一部分电连接的导电层50。所述导电层50与另一个半导体装置上的电极电连接。另外，在另一个半导体元件23的上表面和金属层60与第四绝缘层37之间用树脂密封。
图5(C)表示的是在半导体元件3上隔着金属层60层叠另一个半导体元件23的例子，但实施方式7的层叠型半导体装置的结构并不限于此，例如可以层叠半导体元件以外的电子部件来代替另一个半导体元件23。
根据本发明的实施方式7，可以得到通过层叠而具备多个部件的层叠结构的半导体装置。另外，通过在密封树脂内部具有金属层60，可以将由半导体元件3所产生的热量有效地散热到外部，因此可以获得具有优良散热特性的层叠型半导体装置。另外，通过以与连接于半导体装置的任一电极电连接的方式形成金属层60，可以使金属层60具有接地功能，可以获得具有噪声防止效果的半导体装置。
在本发明的一个实施方式的半导体装置中，第二绝缘层的高度可以小于等于第一绝缘层的高度。
另外，在本发明的一个实施方式的半导体装置的制造方法中，第二绝缘层的高度可以小于等于第一绝缘层的高度。

Claims (5)

1.一种半导体装置，其特征在于，具备：
支持板；
载置在所述支持板上并具有形成了多个第一电极的电路元件面的半导体元件；
覆盖所述半导体元件的电路元件面并具有将所述多个第一电极露出的多个第一开口的第一绝缘层；
覆盖形成有所述第一绝缘层的半导体元件的侧部以及所述支持板的上部的第二绝缘层；以及
与第二绝缘层的上部以及所述第一绝缘层相接触地形成并与所述多个第一电极电连接的布线层，
所述第一绝缘层部与所述支持板不接触。
2.如权利要求1所述的半导体装置，其特征在于，具备形成于所述布线层上并具有将所述布线层的一部分露出的多个第二开口的第三绝缘层。
3.一种半导体装置的制造方法，其特征在于，包括如下步骤：
在半导体基板上形成各自具有包含多个第一电极的电路元件面的多个半导体元件；
在形成了所述多个半导体元件的半导体基板上形成第一绝缘层；
去除所述第一绝缘层的一部分，来形成将所述多个半导体元件的所述多个第一电极露出的多个第一开口；
切断所述半导体基板，来将所述多个半导体元件单片化；
将单片化了的所述多个半导体元件的所述电路元件面朝上，将所述多个半导体元件载置于支持板上；
形成覆盖所述多个半导体元件的各个侧部以及所述支持板上的第二绝缘层；以及
形成与所述第二绝缘层的上部以及所述第一绝缘层相接触并与所述多个半导体元件的所述多个第一电极电连接的布线层。
4.如权利要求3所述的半导体装置的制造方法，其特征在于包括如下步骤：
在所述布线层的上部形成第三绝缘层；
去除所述第三绝缘层的一部分，来形成将所述布线层的一部分即多个第二电极露出的多个第二开口；
在形成于所述第三绝缘层的所述多个第二开口处形成与所述多个第二电极电连接的多个外部连接用电极；以及
将所述支持板切断，来将所述多个半导体元件单片化。
5.一种层叠型半导体装置，其特征在于，具备：
如权利要求1或2所述的半导体装置；
形成于所述半导体装置上的第四绝缘层，所述第四绝缘层具有多个第三开口，所述多个第三开口将所述布线层的一部分露出；
隔着所述第四绝缘层层叠在所述半导体装置上的另一个半导体装置；
形成在所述第四绝缘层的所述多个第三开口内并将所述半导体装置的所述布线层与所述另一个半导体装置的布线层电连接的多个导电层；以及
形成在所述半导体装置与所述第四绝缘层之间并至少覆盖所述半导体装置的上表面的一部分的金属层。
CN201110061664.5A 2010-09-24 2011-03-15 半导体装置及其制造方法 Active CN102420202B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010214306A JP5606243B2 (ja) 2010-09-24 2010-09-24 半導体装置の製造方法
JP2010-214306 2010-09-24

Publications (2)

Publication Number Publication Date
CN102420202A CN102420202A (zh) 2012-04-18
CN102420202B true CN102420202B (zh) 2016-03-16

Family

ID=45869842

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110061664.5A Active CN102420202B (zh) 2010-09-24 2011-03-15 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US8786110B2 (zh)
JP (1) JP5606243B2 (zh)
KR (2) KR101676047B1 (zh)
CN (1) CN102420202B (zh)
TW (1) TWI515850B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134270A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
CN105280567B (zh) * 2014-06-19 2018-12-28 株式会社吉帝伟士 半导体封装件及其制造方法
CN110729255A (zh) * 2019-08-08 2020-01-24 厦门云天半导体科技有限公司 一种键合墙体扇出器件的三维封装结构和方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
JPH05259208A (ja) 1992-03-10 1993-10-08 Fujitsu Ltd 半導体装置及びその製造方法
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH08111495A (ja) 1994-10-07 1996-04-30 Fujitsu Ltd 半導体装置及びその製造方法
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
JP2806357B2 (ja) * 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
DE10010461A1 (de) 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
DE10129388B4 (de) 2001-06-20 2008-01-10 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils
DE10137184B4 (de) 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
DE10158563C1 (de) 2001-11-29 2003-07-17 Infineon Technologies Ag Verfahren zur Herstellung eines Bauelementmoduls
DE10235332A1 (de) 2002-08-01 2004-02-19 Infineon Technologies Ag Mehrlagiger Schaltungsträger und Herstellung desselben
JP3888267B2 (ja) * 2002-08-30 2007-02-28 カシオ計算機株式会社 半導体装置およびその製造方法
WO2004015771A2 (en) 2002-08-09 2004-02-19 Casio Computer Co., Ltd. Semiconductor device and method of manufacturing the same
DE10240461A1 (de) 2002-08-29 2004-03-11 Infineon Technologies Ag Universelles Gehäuse für ein elektronisches Bauteil mit Halbleiterchip und Verfahren zu seiner Herstellung
DE10250538B4 (de) 2002-10-29 2008-02-21 Infineon Technologies Ag Elektronisches Bauteil als Multichipmodul und Verfahren zu dessen Herstellung
DE10251527B4 (de) 2002-11-04 2007-01-25 Infineon Technologies Ag Verfahren zur Herstellung einer Stapelanordnung eines Speichermoduls
DE10255844B3 (de) 2002-11-29 2004-07-15 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Schaltung mit einer Umverdrahtungseinrichtung und entsprechende integrierte Schaltung
DE10333841B4 (de) 2003-07-24 2007-05-10 Infineon Technologies Ag Verfahren zur Herstellung eines Nutzens mit in Zeilen und Spalten angeordneten Halbleiterbauteilpositionen und Verfahren zur Herstellung eines Halbleiterbauteils
DE10340129B4 (de) 2003-08-28 2006-07-13 Infineon Technologies Ag Elektronisches Modul mit Steckkontakten und Verfahren zur Herstellung desselben
US7459781B2 (en) 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
DE102004049356B4 (de) 2004-10-08 2006-06-29 Infineon Technologies Ag Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben
US7238602B2 (en) 2004-10-26 2007-07-03 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
JP2006203079A (ja) * 2005-01-21 2006-08-03 Sharp Corp 半導体装置および半導体装置の製造方法
US7183652B2 (en) 2005-04-27 2007-02-27 Infineon Technologies Ag Electronic component and electronic configuration
DE102005045767B4 (de) 2005-09-23 2012-03-29 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauteils mit Kunststoffgehäusemasse
DE102006005994A1 (de) 2006-02-08 2007-08-16 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip und Verfahren zur Herstellung derartiger Halbleiterbauteile
TW200805595A (en) 2006-07-07 2008-01-16 Advanced Chip Eng Tech Inc Fan out type wafer level package structure and method of the same
DE102006037118B3 (de) 2006-08-07 2008-03-13 Infineon Technologies Ag Halbleiterschaltmodul für Bordnetze mit mehreren Halbleiterchips, Verwendung eines solchen Halbleiterschaltmoduls und Verfahren zur Herstellung desselben

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity

Also Published As

Publication number Publication date
KR20160084344A (ko) 2016-07-13
US8786110B2 (en) 2014-07-22
KR101676047B1 (ko) 2016-11-14
TW201214640A (en) 2012-04-01
JP5606243B2 (ja) 2014-10-15
US20120074594A1 (en) 2012-03-29
KR20120031423A (ko) 2012-04-03
CN102420202A (zh) 2012-04-18
JP2012069804A (ja) 2012-04-05
TWI515850B (zh) 2016-01-01
KR101676225B1 (ko) 2016-11-22

Similar Documents

Publication Publication Date Title
JP3904541B2 (ja) 半導体装置内蔵基板の製造方法
US6400010B1 (en) Substrate including a metal portion and a resin portion
JP5032623B2 (ja) 半導体記憶装置
JP5143451B2 (ja) 半導体装置及びその製造方法
US10045436B2 (en) Printed circuit board and method of manufacturing the same
JP2015176906A (ja) 半導体装置および半導体装置の製造方法
JP2012104790A (ja) 半導体装置
JP4704800B2 (ja) 積層型半導体装置及びその製造方法
TW201448131A (zh) 配線基板
WO2007114106A1 (ja) 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
JP2015177061A (ja) 半導体装置の製造方法および半導体装置
JP2018022824A (ja) 電子部品内蔵基板及びその製造方法と電子部品装置
CN102420202B (zh) 半导体装置及其制造方法
JP4970388B2 (ja) 半導体装置及び半導体装置の製造方法
JP2010109274A (ja) 半導体モジュールおよび半導体モジュールの製造方法
US20140167276A1 (en) Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
US20100301468A1 (en) Semiconductor device and method of manufacturing the same
JP4480710B2 (ja) 半導体装置内蔵基板
JP2017034224A (ja) 電子モジュール
US20210035817A1 (en) Methods for manufacturing semiconductor device and wiring struture
JP2008084998A (ja) 板状体およびそれを用いた回路装置の製造方法
JP5606569B2 (ja) 半導体装置及び積層型半導体装置
JP2010238994A (ja) 半導体モジュールおよびその製造方法
JP5089660B2 (ja) 半導体装置内蔵基板の製造方法
JP4700641B2 (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Japan pestle City

Patentee after: Rely on Technology Japan company

Address before: Japan pestle City

Patentee before: J-DEVICES Corp.