CN102234096A - 半导体结构体及半导体结构体的制造方法 - Google Patents

半导体结构体及半导体结构体的制造方法 Download PDF

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CN102234096A
CN102234096A CN2011100763470A CN201110076347A CN102234096A CN 102234096 A CN102234096 A CN 102234096A CN 2011100763470 A CN2011100763470 A CN 2011100763470A CN 201110076347 A CN201110076347 A CN 201110076347A CN 102234096 A CN102234096 A CN 102234096A
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CN102234096B (zh
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胁坂伸治
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Aoi Electronics Co Ltd
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Casio Computer Co Ltd
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Abstract

本发明提供一种半导体结构体，使在电子电路周围需要光透射部的半导体结构体的生产性提高。半导体结构体包含：在规定区域设有电子电路的半导体基板；围绕上述半导体基板上的规定区域而形成的壁；设在上述半导体基板上的上述规定区域外部的配线；设在上述配线上的外部连接用电极；在上述壁的外部填充的、用于密封上述配线的密封树脂；在上述壁的内部填充的、用于密封上述规定区域的透明树脂。

Description

半导体结构体及半导体结构体的制造方法
技术领域
本发明涉及半导体结构体以及半导体结构体的制造方法。
背景技术
提出有一种半导体结构体(参照日本特开2005-109221号公报)，该半导体结构体，在半导体基板上除了形成电子电路以外，还形成具有MEMS(Micro Electro Mechanical Systems微机电系统)的电子电路，该MEMS为加速度传感器(参照日本特开2009-72848号公报)、悬臂(参照日本特开2004-209585号公报)等机械元件、光学元件等。
但是，对于具有光学元件的半导体结构体，需要光的入射或出射的场所。
发明内容
本发明的课题，是提高这种半导体结构体的生产性。
本发明的半导体结构体，包含：
在规定区域设有电子电路的半导体基板；围绕上述半导体基板上的规定区域而形成的壁；设在上述半导体基板上的上述规定区域外部的配线；设在上述配线上的外部连接用电极；填充在上述壁的外部的、用于密封上述配线的密封树脂；填充在上述壁的内部的、用于密封上述规定区域的透明树脂。
对于该半导体结构体的制造方法，包括：
将外部连接用电极形成在半导体基板上的规定区域的外部所配置的配线层上，并同时形成围绕上述规定区域的壁，
在上述壁的上部，载置用于封堵上述规定区域以外的上部空间的盖，
在上述壁的内部，填充用于密封上述规定区域的透明树脂，
去除上述盖，
在上述壁的外部，填充用于密封上述连接焊盘和上述配线的密封树脂，
与上述透明树脂一起，对上述密封树脂的上表面、上述外部连接用电极的上表面以及上述壁的上表面进行切削。
发明效果
根据本发明，半导体结构体的生产性可获得提高。
附图说明
图1是表示关于本发明第一实施方式的半导体结构体1B的平面图。
图2是图1的II-II向视剖视图。
图3是半导体结构体1B的制造方法的说明图。
图4是半导体结构体1B的制造方法的说明图。
图5是半导体结构体1B的制造方法的说明图。
图6是半导体结构体1B的制造方法的说明图。
图7是半导体结构体1B的制造方法的说明图。
图8是半导体结构体1B的制造方法的说明图。
图9是半导体结构体1B的制造方法的说明图。
图10是半导体结构体1B的制造方法的说明图。
图11是表示半导体结构体1B的制造过程中、切割前的半导体基板的平面图。
图12是图11的XII-XII向视剖视图。
图13是表示半导体结构体1B的制造过程中、切割前的半导体基板的平面图。
图14是图13的XIV-XIV向视剖视图。
图15是表示半导体结构体1B的制造过程中、切割前的半导体基板的平面图。
图16是图15的XVI-XVI向视剖视图。
图17是表示半导体结构体1B的制造过程中、切割前的半导体基板的平面图。
图18是图17的XVIII-XVIII向视剖视图。
图19是表示半导体结构体1B的制造过程中、切割前的半导体基板的平面图。
图20是图19的XX-XX向视剖视图。
图21是表示安装有半导体结构体1B的结构的剖视图。
符号说明
1B  半导体结构体
2   电子电路
10  半导体器件晶片
11  半导体基板
12  连接焊盘
13  保护绝缘膜
13a、13b、14a、14b、20a、20b、201  开口
14、214  绝缘膜
15  配线
16  电镀用种子层
17  配线抗蚀剂
19、219  配线层
20  抗蚀剂
21  外部连接用电极
22  密封树脂
23  壁
25B 盖
26  透明树脂
200 基板
223 焊接端子
具体实施方式
图1是表示本发明实施方式的半导体结构体1B的平面图，图2为图1的II-II向视剖视图。如图1、图2所示，半导体结构体1B，通过在半导体器件晶片10的表面形成绝缘膜14、配线15、外部连接用电极21、密封树脂22、壁23、透明树脂26等而成。
半导体器件晶片10如图1所示，具有：由硅等构成的半导体基板(包含半导体晶片)11，由金属等导电材料构成的多个连接焊盘12，由氧化硅或氮化硅等绝缘材料构成的保护绝缘膜13等。
在半导体基板11的表面，形成有电子电路2、连接焊盘12，以及连接它们的配线等。电子电路2是没有可动部的光学元件，例如光敏传感器、红外成像器等。
连接焊盘12与硅基板11上的配线连接。保护绝缘膜13形成在半导体基板11的表面，并覆盖配线等。
另外，在保护绝缘膜13中，设有使连接焊盘12露出的开口13a和使电子电路2露出的开口13b。如图1、图2所示，开口13a比连接焊盘12小，开口13b比电子电路2大。
在保护绝缘膜13的上表面，形成有由环氧类树脂、聚酰亚胺类树脂等构成的绝缘膜14。绝缘膜14可以采用聚酰亚胺、聚苯并恶唑(PBO)等高性能塑料材料、环氧类、酚类、硅类等塑料材料，或这些材料的复合材料。
在绝缘膜14中，设有使连接焊盘12露出的开口14a，和使电子电路2露出的开口14b。如果绝缘膜14为感光性树脂，则可以在半导体器件晶片10上通过涂敷-曝光-显影-硬化而统一形成开口14a、14b。此外，开口14a、14b例如可以通过激光形成。如图1、图2所示，绝缘膜14的开口14a比保护绝缘膜13的开口13a小，连接焊盘12和绝缘膜14在开口14a的外周部紧密接触。此外，绝缘膜14的开口14b比电子电路2大，电子电路2在绝缘膜14的开口14b内露出。
在绝缘膜14上表面的一部分，以及从开口14a露出的连接焊盘12的上部，形成有配线15。
配线15包含：作为下层的、成为用于对上层进行电镀的核的具有铜等的电镀用种子层16；作为上层的、具有铜等导电材料的配线层19。电镀用种子层16的厚度，以200nm～2000nm为宜。电镀用种子层16的一部分，经由开口13a和14a连接到连接焊盘12。配线15用于，使电子电路2及设在半导体结构体1A的硅基板11的晶体管等其它电子电路与外部连接用电极21导通。
在电镀用种子层16的上表面，形成由铜等导电材料构成的配线层19以及壁层24。
镀层19比电镀用种子层16厚，例如，以1μm～15μm的厚度为宜。在配线15的与连接焊盘12相反侧的端部的焊接区(land)上表面，形成由铜等导电材料构成的外部连接用电极21。外部连接用电极21例如为柱状的形状，外部连接用电极21的直径为50～500μm。外部连接用电极21的高度为45～99μm左右，加上配线15的厚度则是50～100μm左右。
作为电镀用种子层16和配线层19的层叠体的配线15，将对应的一个或多个连接焊盘12与一个或多个外部连接用电极21连接。此外，配线15分别与邻接的其它配线15电绝缘地排列。
壁23围绕开口13b和14b地设置，从上侧俯视呈四边形的形状。壁23包括：作为下层的、成为用于对上层进行电镀的核的具有铜等的电镀用种子层16；和作为上层的、具有铜等导电材料的壁层24。壁层24含有铜等导电材料。壁23的宽度为70～100μm。壁23的上表面和外部连接用电极21的上表面基本齐平，高度为50～100μm左右。由于壁23与半导体基板11之间存在保护绝缘膜13，因此壁23与电子电路2及在半导体结构体1A的硅基板11设置的晶体管等其它电子电路绝缘。
此外，与接地的连接焊盘12连接的一根配线15延伸到壁23的下部，某一个外部连接用电极21经由该配线15与壁23导通。该外部连接用电极21为接地用端子，使壁23接地。
在半导体基板11的上面，在壁23的内侧部分，填充有用于密封电子电路2的透明树脂26。透明树脂26可以采用例如热硬化性聚酰亚胺、环氧类树脂、酚类树脂等热硬化性树脂等。
在配线15及绝缘膜14的上面、在外部连接用电极21的周围以及壁23的外侧部分，填充有密封树脂22。密封树脂22由例如热硬化性聚酰亚胺、环氧类树脂、酚类树脂等热硬化性树脂与二氧化硅等填料的复合物(复合材料)构成。但是，不含填料的热硬化性树脂也可以。外部连接用电极21的上表面从密封树脂22露出。
下面关于半导体结构体1B的制造方法，由图3～图18进行说明。这里，图3～图10为制造过程中切割前的半导体基板的剖视图。此外，图11、图13、图15、图17为半导体结构体1B制造过程中切割前的半导体基板的平面图，图12为图11的XII-XII向视剖视图，图14为图13的XIV-XIV向视剖视图，图16为图15的XVI-XVI向视剖视图，图18为图17的XVIII-XVIII向视剖视图，图20为图19的XX-XX向视剖视图。
首先，如图3所示，在半导体基板(包括半导体晶片)11上，在具有连接焊盘12以及保护绝缘膜13的、切割前的半导体器件晶片10的表面，形成绝缘膜14。另外，在保护绝缘膜13还未设有使电子电路2露出的开口14b，电子电路2被保护绝缘膜13所覆盖。
接着，如图4所示，通过溅射等气相淀积方法形成覆盖绝缘膜14整面以及连接焊盘12的电镀用种子层16。
接着，如图5所示，除电镀用种子层16上的形成配线层19的区域之外，形成配线抗蚀剂17。
接着，如图6所示，在未形成配线抗蚀剂17的部分，通过以电镀用种子层16为阴极的电镀来堆积配线层19。
之后，如图7所示，去除配线抗蚀剂17。
接着，如图8所示，在电镀用种子层16以及配线层19的上表面粘附干膜并进行构图，从而形成外部连接用电极21和壁层24用的抗蚀剂20。另外，在抗蚀剂20中，在多个形成外部连接用电极21的部分设置多个开口20a，在形成壁层24的部分设置开口20b。
接着，如图9所示，通过以电镀用种子层16为阴极的电镀，分别在抗蚀剂20的开口20a内堆积外部连接用电极21，在开口20b内堆积壁层24。
接着，如图10所示，去除抗蚀剂20。
接着，如图11、图12所示，通过软刻蚀(soft etching)去除未形成配线层19、外部连接用电极21、壁层24的区域的电镀用种子层16，形成作为配线层19和其下部的电镀用种子层16的层叠体的配线15，并且形成作为壁层24和其下部的电镀用种子层16的层叠体的壁23。
另外，这时，虽然配线层19、外部连接用电极21、壁层24的表面也被刻蚀和电镀用种子层16相同程度的厚度，但由于配线层19、外部连接用电极21、壁层24与电镀用种子层16相比具有足够的厚度，因而不会有影响。
接下来，通过外观检查来确认是否有配线15的断线及半导体器件晶片10上是否存在异物。接着，利用氧等离子体对绝缘膜14的表面进行处理，从而去除表面的碳化物等异物。
接下来，如图13、图14所示，将封堵壁23外侧部分(有外部连接用电极21及配线15的区域)的盖25B置于壁23的上部。盖25B例如可以采用由铜、不锈钢等构成的印刷掩模版。
接下来，如图15、图16所示，在壁23的内侧部分填充透明树脂26。此时，由于壁23的外侧部分已被盖25B封堵住，因此不会被填充透明树脂26。
接着，在透明树脂26硬化后，如图17、图18所示，去除盖25B。
接着，如图19、图20所示，在半导体基板11的上面整体涂敷密封树脂22。密封树脂22的透射性可以比透明树脂26低。
接下来，从密封树脂22的上表面进行切削，从而使外部连接用电极21、密封树脂22、壁23以及透明树脂26上表面共面。之后，切割半导体基板11，从而图1、图2所示的半导体结构体1B完成。
图21是表示已将半导体结构体1B安装在外部电路基板上的结构的剖视图。在外部电路基板的基底基板(ベ一ス基板)200的上表面形成有配线219，除设有焊接端子223的部分以外，配线219被绝缘膜214覆盖。半导体结构体1B的外部连接用电极21和配线219经由焊接端子223而连接。基底基板200具有开口201，在与开口201的外周部对应的位置配置壁23，在与开口201对应的位置配置电子电路2。
这样，根据本发明，形成包围半导体器件晶片10的形成有电子电路2的区域的壁23，用盖25B进行封堵后在壁23的内侧部分填充透明树脂26，能够将形成有电子电路2的区域密封。此外，由于壁23与外部连接用电极21同时形成，因此可以减少工序数，生产性可以获得提高。

Claims (17)

1.一种半导体结构体，其特征在于，包括：
在规定区域设有电子电路的半导体基板；
包围上述半导体基板上的规定区域而形成的壁；
设在上述半导体基板上的上述规定区域的外部的配线；
设在上述配线上的外部连接用电极；
在上述壁的外部填充的、用于密封上述配线的密封树脂；以及
在上述壁的内部填充的、用于密封上述规定区域的透明树脂。
2.如权利要求1记载的半导体结构体，其特征在于，
上述壁及上述外部连接用电极由同一材料形成。
3.如权利要求1记载的半导体结构体，其特征在于，
上述壁及上述外部连接用电极被设定为相同的高度。
4.如权利要求1记载的半导体结构体，其特征在于，
在上述壁与上述半导体基板之间存在保护绝缘膜。
5.如权利要求1记载的半导体结构体，其特征在于，
上述壁接地。
6.如权利要求5记载的半导体结构体，其特征在于，
上述半导体基板具有接地用的连接焊盘，上述接地用连接焊盘经由接地用配线与上述壁连接。
7.如权利要求1记载的半导体结构体，其特征在于，
上述外部连接用电极与外部电路基板相接。
8.如权利要求7记载的半导体结构体，其特征在于，
在上述外部连接用电极和上述外部电路基板之间设有焊接端子。
9.如权利要求7记载的半导体结构体，其特征在于，
在上述外部电路基板，与上述半导体基板的上述规定区域对应的部位开口。
10.一种半导体结构体的制造方法，其特征在于，包括以下工序：
将外部连接用电极形成于在半导体基板上的规定区域的外部所配置的配线层上，并同时形成围绕上述规定区域的壁；
在上述壁的上部，载置用于封堵上述规定区域以外的上部空间的盖；
在上述壁的内部，填充用于密封上述规定区域的透明树脂；
去除上述盖；
在上述壁的外部，填充用于密封上述连接焊盘和上述配线的密封树脂；
将上述密封树脂、上述外部连接用电极以及上述壁与上述透明树脂一起进行上表面切削。
11.如权利要求10记载的半导体结构体的制造方法，其特征在于，
形成具有开口的抗蚀剂，该开口位于上述配线上以及围绕上述规定区域的区域。
12.如权利要求10记载的半导体结构体的制造方法，其特征在于，
上述外部连接用电极和上述壁通过电镀而形成于上述抗蚀剂的上述开口。
13.如权利要求10记载的半导体结构体的制造方法，其特征在于，
上述壁接地。
14.如权利要求13记载的半导体结构体的制造方法，其特征在于，
上述半导体基板具有接地用的连接焊盘，上述接地用连接焊盘经由接地用配线与上述壁连接。
15.如权利要求10记载的半导体结构体的制造方法，其特征在于，
上述外部连接用电极与外部电路基板连接。
16.如权利要求15记载的半导体结构体的制造方法，其特征在于，
在上述外部连接用电极与上述外部电路基板之间设有焊接端子。
17.如权利要求10记载的半导体结构体的制造方法，其特征在于，
在上述外部电路基板，与上述半导体基板的上述规定区域对应的部位开口。
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