CN102203915A - 晶体管内与先进的硅化物形成结合的凹槽式漏极和源极区 - Google Patents

晶体管内与先进的硅化物形成结合的凹槽式漏极和源极区 Download PDF

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CN102203915A
CN102203915A CN2009801431539A CN200980143153A CN102203915A CN 102203915 A CN102203915 A CN 102203915A CN 2009801431539 A CN2009801431539 A CN 2009801431539A CN 200980143153 A CN200980143153 A CN 200980143153A CN 102203915 A CN102203915 A CN 102203915A
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transistor
source area
drain electrode
gate electrode
electrode
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CN102203915B (zh
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U·格里布诺
A·卫
J·亨奇科
T·沙伊帕
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

在形成复杂的晶体管元件的制造工艺中，可减少栅极的高度，也可在各自的金属硅化物区域形成之前，在共同的蚀刻序列得到漏极和源极配置。因为在蚀刻序列时，相应的侧壁间隔结构可维持，因此可控性和栅电极内的硅化处理的统一性可加强，从而得到减少程度的阈值变异性。此外，可提供凹槽式漏极和源极配置以减少整体串联电阻和增加应力传递效率。

Description

晶体管内与先进的硅化物形成结合的凹槽式漏极和源极区
技术领域
一般而言，本发明系关于集成电路，且尤系关于通过使用应力源的具有应变沟道区域的晶体管，如，应力覆盖层，在漏极和源极区的应变半导体合金，以提高MOS晶体管的沟道区内的载流子迁移(charge carrier mobility)。
背景技术
一般来说，半导体生产领域目前实行的许多工艺技术，其中，对于复杂的电路，如微处理器，复杂的存储芯片和之类，由于优越的特点鉴于运行速度和/或功耗和/或成本效益，CMOS技术是最有前途的方法之一。使用CMOS技术在复杂的集成电路的制造，数百万晶体管，即，N沟道晶体管和p沟道晶体管形成在包括结晶半导体层的衬底上。MOS晶体管，不论是否考虑N沟道晶体管或P沟道晶体管，包括所谓的PN结(pn-junction)，由高掺杂漏极和源极区的界面形成，其带有负或弱掺杂沟道区于漏极区和源极区之间。沟道区的电导率，即导电沟道的驱动电流能力，是由形成在沟道区附近和由薄绝缘层分离之闸电极控制。导电沟道形成后，沟道区的电导率，由于适当的控制电压应用在栅电极，依赖于掺杂浓度，多数载流子迁移率，以及-在晶体管宽度方向的沟道区的给定延伸-在源极和漏极区之间的距离，其也被称为沟道长度。因此，在栅电极控制电压的应用，结合快速创建在绝缘层下的导电沟道的能力，沟道区域的整体导电率大致决定了MOS晶体管的性能。因此，对于完成运算速度和集成电路包装密度的增加，沟道长度减少是主导设计标准。
晶体管的尺寸不断缩小，但是，涉及到与此相关的问题必须得到解决，以便不被不适当地偏移通过不断降低MOS晶体管的沟道长度获得的优势。在这方面的一个主要问题是源极和漏极区的低薄板及接触电阻率及所连的任何接触点，并保持沟道可控性。例如，减少沟道长度可能需要栅电极与沟道区域之间的电容耦合的增加，其可能需要栅极绝缘层的厚度减少。目前，二氧化硅基栅绝缘层的厚度是在1到2纳米的范围，其中鉴于降低栅极电介质厚度时，漏电流通常成倍增加，进一步减少可能会不太理想。
临界尺寸的不断尺寸缩小，即晶体管的栅极长度，必须适应化修改和可能有关上述问题的高度复杂工艺技术的新发展。因此，已被提出通过给定的沟道长度的沟道区域内的载流子迁移率增加，通过提高晶体管元件的沟道导电率改进晶体管的性能，从而比未来的技术提供了实现性能改进的潜力，同时避免或至少推迟如栅极电介质缩放的上述问题。增加载流子迁移率的一个有效机制是沟道区域内的晶格结构的修正，例如，通过在沟道区域附近建立拉伸或压缩应力，以便在沟道区域内产生相应的应变，分别导致电子和电洞修正的迁移率。例如，对于标准的硅衬底创建沟道区域内的拉伸应变增加电子的迁移率，反过来，可以直接转换成电导率相应增加和因此之驱动电流和运行速度。另一方面，沟道区域内的压缩应变可能会增加电洞的迁移率，从而为提高p型晶体管性能的潜力。应力或应变工程的引入集成电路制造是进一步器件世代非常有前途的方法，因为例如应变硅可作为“新”型半导体材料，它可以使快速强大的半导体器件制造不需要昂贵的半导体材料，而许多行之有效的制造技术仍然可以使用。
依据创建晶体管元件的沟道区域的应变的有前途的方法，形成基本晶体管结构上的电介质材料可提供高应力状态，以在晶体管特别是在其沟道区域中，诱导所需类型的应变。例如，晶体管结构一般由层间电介质材料封闭，其可提供个别晶体管结构所需的机械和电子完整性，并可对额外的布线层的形成提供平台，个别电路元件之间提供电性互连通常是需要的。也就是说，可提供多个布线水平或金属化层，其可包括水平金属线和包括适当的导电材料用以建立电性连接的垂直通孔。因此，要提供适当的接触结构连接实际的电路元件，如晶体管，电容器之类，或带有第一金属化层的其个别部分。为此目的，层间电介质材料必须适当的图案化，以提供连接到电路元件的所需的接触区的个别开口，一般可通过使用蚀刻停止材料结合实际层间电介质材料来完成。
例如，二氧化硅结合氮化硅是一种行之有效的层间电介质材料，其可在接触开口形成期间，作为有效的蚀刻停止材料。因此蚀刻停止材料，即硅氮化物材料，与基本晶体管结构密切接触，从而可以有效使用于晶体管内诱导应变，特别是在行之有效的具有高内部应力的等离子增强化学气相沉积(化学气相沉积)技术的基础可沉积硅氮化物。例如，内部压缩应力高达2GPa和甚至更高，可通过选择合适的沉积参数沉积硅氮化物。另一方面，通过适当调整工艺参数，适度高的内部拉伸应力水平，可创建1GPa和较高。特别是例如离子轰击的程度，在氮化硅材料的沉积期间。因此，在晶体管元件的沟道区域内造成的应变大小可取决于介质蚀刻停止材料的内部应力水平和应力电介质材料的厚度结合关于沟道区域的高应力介质材料的有效的偏移。因此，鉴于提高晶体管的性能，其需要增加内部应力水平，也提供在晶体管元件附近的高应力电介质材料的数量的提高，同时也定位应力电介质材料尽可能接近沟道区域。然而，通过目前可用的等离子增强化学气相沉积技术的整体沉积能力，氮化硅材料的内应力水平可能受限制，同时通过基本晶体管形貌结构(topography)和邻近的电路元件之间的距离也大致决定有效层厚度。因此，尽管提供显着的优势，对应力传递机制的效率可能显着依赖于工艺和器件的特性，并可能导致对既定标准晶体管具有50纳米栅极长度的设计，减少降低性能增益，因为给定的器件形貌结构和各自的沉积工艺的间隙填充能力结合通过精密的间隔结构造成的来自沟道区域的高应力材料的适度高偏移，可能会降低最终在沟道区域内获得的应变。
基于这些原因，也有建议通过提供半导体材料，以在相邻的沟道区域可产生所需类型的应变这样的方式，至少在漏极和源极区的部分，改善晶体管(如P-沟道晶体管)性能。对此，经常使用硅/锗混合物或合金，其可通过在硅模板材料上的选择性外延生长技术生长，从而创建硅/锗合金的应变状态，其可在相邻的沟道区域上施加一定的压力，从而在其中创建所需类型的应变。因此，结合覆盖应力电介质材料，P-沟道晶体管可完成高效的应变诱发机制。
如前所述，在复杂的晶体管元件许多功能最终确定晶体管的整体性能，其中这些因素复杂的相互作用可能很难评估，因此，给定的基本晶体管配置可观察性能的各种变化。例如，通过在其中提供金属硅化物，掺杂硅基半导体区域的导电性可增加，以降低整体片电阻和接触电阻。例如，漏极和源极区可接收金属硅化物，如镍硅化物，镍铂硅化物和之类，从而降低了漏极和源极端和中间沟道区域之间的传导路径的整体串联电阻。同样，金属硅化物可典型形成于栅电极，其可包括多晶硅材料，从而提高电导率和降低信号传输延迟。虽然，鉴于减少其整体电阻，栅电极内的金属硅化物的量增加本身可能是理想的，鉴于相应晶体管元件阈值电压调整，在栅极介电材料下实质完成多晶硅材料的硅化可能是不理想的。因此，有必要维持掺杂多晶硅材料的一定部分直接接触栅介质材料，以提供沟道区域内的定义良好的电子特性，以避免显着的阈值变化，这可能是由在栅电极的部分内大致的全硅化造成。因此，可能难以提供大量的金属硅化物，但可靠地避免多晶硅材料的完全硅化。
栅电极的其他特性也有可能对整体晶体管的性能有影响。例如，对于晶体管元件不断减少的特征尺寸，减少其栅电极的高度是理想的，但是这通常是有限的，因为通过先进的植入技术，漏极和源极掺杂剖面产生期间需要离子阻断能力。这需要栅极的高度，但是，可能会导致就触点元件增加边缘电容，其可能形成以连接漏极和源极区。因此，对复杂的晶体管元件的整体性能可能会比预期的不那幺明显，即使相应的性能增加机制，如应变硅/锗材料和之类可使用，将参考图1a和1b进行更详细的描述。
图1a示意说明包括衬底101的半导体器件100的横截面视图，其上形成半导体层103，其中有多个隔离结构104分别定义N沟道150a和P沟道晶体管150b的有源区103a，103b。有源区理解为半导体层103的部分，其中建立适当的掺杂剖面，以获得所需的晶体管功能。在所示制造阶段，晶体管150a，150b包括形成在栅极绝缘层152上的栅电极151，栅极绝缘层152从沟道区域153隔开栅电极151。此外，间隔结构155形成在栅电极151的侧壁部分上，其中，应该明白间隔结构155可有适当的配置，定义相应的漏极和源极区154的掺杂剖面。例如，间隔结构155可包括多个个别间隔元件，可能与相应的蚀刻停止衬垫(未显示)结合。如前所述，p沟道晶体管150b包括硅/锗合金105，其可具有应变状态，从而在晶体管150b的沟道区域153内创建相应的压缩应变分量。
如图1a所示的半导体器件100可在以下工艺顺序的基础上形成。形成隔离结构104后，例如由微影蚀刻，沉积和平坦化技术，通过植入技术结合相应的掩膜机制，可以定义有源区103a，103b。此后，可形成栅电极151与栅极绝缘层152的组合，例如提供适当的电介质材料和沉积多晶硅材料，然后可以在复杂的光刻和蚀刻技术的基础上图案化。如前所述，可以通常选择栅电极151的高度151h，以在器件100的后续的工艺期间提供足够的离子阻断效应。此后，可掩膜晶体管150a，例如，由硬掩膜结合抵抗掩膜，而晶体管150b的栅电极151亦可封装，例如适当的覆盖层和侧壁间隔物的基础上(未显示)，以在选择性外延生长技术的基础上在有源区103b形成相应的腔(cavities)和随后的沉积硅/锗合金105。接下来，可移除掩膜层，和可暴露栅电极151和可继续进一步的工艺，比如通过形成偏移间隔元件，如果需要，可用于第一植入顺序以定义漏极和源极区154的第一部分。此后，间隔结构155是由沉积适当的层堆迭形成，如蚀刻停止衬垫，如二氧化硅之后是硅氮化物材料，其可通过行之有效的CVD(化学气相沉积)技术来完成。此后，通过各向异性刻蚀工艺，图案化层堆栈，在此期间，氮化硅材料最好是从水平部分移除，而通常可靠的暴露水平器件区，也在相应的蚀刻工艺期间和在后续蚀刻和清洗工艺期间，暴露栅电极151的侧壁的部分151s。其次，可以进行进一步植入顺序，以对漏极和源极区154取得所需的掺杂剖面。此后，进行适当的退火工艺以激活掺杂剂，并再结晶植入诱导损伤。此后，该器件100准备执行硅化工艺，其通常包括相应的清洗工艺，从而进一步暴露侧壁部分151s。
图1b示意说明在进一步制造阶段的半导体器件100，其中漏极和源极区154的部分形成金属硅化物区155，而栅电极151也形成金属硅化物157。在先进的技术，经常使用镍和铂获得金属硅化物156，157，其中，由于在栅电极151的多晶体材料和在漏极和源极区154的晶体材料的不同的扩散行为，其中可得到显着不同的“转化率”，特别是在侧壁部分151s金属可能增加地扩散到栅电极151，从而增加硅化率。因此，金属硅化物157可向下延伸到栅极绝缘层152，至少局部在栅电极151内，从而造成相应的阈值电压变化，因为金属硅化物的功函数(work function)可能与相应掺杂的多晶硅材料的相应的功函数不同。硅化工艺后，可继续进一步的处理，例如，通过沉积应变诱导材料层，例如，氮化硅的形式，使用的沉积参数而定，以高压缩和拉伸应力沉积。例如，N沟道晶体管150a的上面可形成拉伸应力氮化硅材料，而晶体管150b的上面可形成压缩应力氮化硅材料，从而由于在沟道区域153建立的相应的额外应变，适当地提高这些晶体管的整体性能。此后，沉积和图案化层间电介质材料，如二氧化硅之类，以获得相应的接触开口，并在后来以导电材料如钨填充，从而提供接触元件连接到栅电极151和漏极和源极区154。正如前面所讨论的，延伸到漏极和源极区154的接触单元可以定义，再加上栅电极151和中间介质材料，相应的寄生电容，其可影响整个沟道可控性，通常称为边缘电容。因此，虽然减少器件尺寸可结合先进的应变诱导机制，晶体管150a，150b，由于适度的高边缘电容，可能遭受了不那幺明显的性能增益，而可观察到一定程度的阈值的变异。
鉴于上述情况，本发明系关于形成晶体管元件的半导体器件和技术，而可避免或至少减少一个或更多的上述问题。
发明内容
一般而言，本发明系关于半导体器件和其制造技术，其中凹槽式晶体管配置的基础，可获得N沟道晶体管和p沟道晶体管的提高的晶体管性能，至少在一种晶体管，而另外栅电极的高度可移除，以减少接触元件和栅电极之间的边缘电容。在同时，栅电极的减少高度可导致相应的硅化工艺增加可控性，从而大大降低完全硅化多晶硅栅电极材料的概率，因此可导致减少的阈值变异。本发明所披露的栅极的高度的减少，以及至少一晶体管的漏极和源极区的凹槽式，非掩膜蚀刻机制的基础可完成，因而并没有太大的整体工艺的复杂性。另一方面，在一些实施例，在一种多余高度的适当数量的晶体管可提供半导体合金，以即使在另一种晶体管的漏极和源极区凹槽式之后，可实质平面晶体管配置。由于凹槽式漏极和源极配置，相应的高应力电介质材料的整体应变诱导效应可能会提高，因为应力介质材料可在对应沟道区域153的高度水平。此外，对硅化工艺增加表面面积可在漏极和源极区提供，从而降低了漏极和源极端之间的整体串联电阻。
所披露半导体器件包括第一晶体管的漏极和源极区形成在半导体材料，其中相比于由第一晶体管的栅极绝缘层的表面定义的高度水平，漏极和源极区有凹槽式表面部分在较低的高度水平。半导体器件还包括栅极绝缘层上形成的栅电极，其包括掺硅材料形成在栅极绝缘层上和其包括金属硅化物形成在掺杂硅材料上。此外，提供间隔结构，以具有高度高于栅电极的高度和金属硅化物区形成在漏极和源极区。
所披露的方法包括于晶体管的栅电极的侧壁上形成间隔结构，暴露晶体管的和栅电极于蚀刻环境，以至少从栅电极选择性去除材料至间隔结构。该方法还包括：去除材料后，在漏极和源极区和栅电极形成硅化物金属材料。最后，该方法包括栅电极和漏极和源极区上形成应变诱导层。
进一步披露的方法包括形成蚀刻工艺，以从第一晶体管的第一栅电极和第二晶体管的第二栅电极和第一和/或第二晶体管的漏极和源极区移除材料，而通过间隔结构保护第一和第二闸电极的侧壁。此外，该方法包括在第一和第二闸电极和在存在间隔结构的漏极和源极区形成金属硅化物，其中，金属硅化物终止于第一和第二栅电极的掺杂硅材料。
附图说明
通过配合下列图式参考实施方式和权利要求书而可完整了解本发明，其中相同的组件符号图式中相似的组件。
图1a和1b示意说明根据传统技艺的半导体器件的横截面视图，半导体器件包括N沟道晶体管和P沟道晶体管，在不同制造阶段形成金属硅化物和应变诱导机制；
图2a-2c示意说明根据本发明实施例的半导体器件的横截面视图，半导体器件包括在不同制造阶段不同型式晶体管，其中结合降低栅电极结构的高度形成凹槽式漏极和源极配置；
图2d和2e示意说明根据本发明进一步实施例的半导体器件的横截面视图，其中漏极和源极区的凹槽式和降低栅极高度可在一定程度上耦合；及
图2f示意说明根据本发明进一步实施例的在进一步的制造阶段的半导体器件的横截面视图。
具体实施方式
下列实施方式在本质上仅为例示，并非用来限制本发明的实施例或这些实施例的应用和使用.如在此所使用者，用语“例示”意指“用作为范例、例子或说明”。在此所描述并作为例示的任何实作不需被解读为相较于其其实作为较佳或有利者。再者，本发明无意受到前述技术领域、背景技术、发明内容或下列实施方式中提到的任何明示或暗示的理论所限制。
一般而言，本发明系关于半导体器件和工艺技术，以(例如)选择地提供凹槽式晶体管配置，而在同一时间使栅电极高度降低，而由于使用创建完全硅化栅电极结构的概率，提供降低阈值的变异。由于，例如，一种类型的器件(如N沟道晶体管)的凹槽式漏极和源极配置，对高应力电介质材料(如介电蚀刻停止层，层间电介质材料等等)以后的沉积可提供增强表面形貌。也就是说，即使在其他器件区域需要减少层的厚度，由于沉积工艺限制的共形沉积能力，凹槽式漏极和源极配置可使该高应力介质材料与沟道区域更紧密。因此，在大致对应沟道区域的高度水平的高度水平，与沟道区域紧密的介质材料的数量可能会增加，其与普遍增强横向应力传递相结合，可对相邻沟道区域的更高的应变提供，从而有助于提高载流子迁移率和从而晶体管的推动电流能力。此外，凹槽式漏极和源极配置还可提供硅化工艺中使用的增加表面积，可因此导致晶体管的接触面积减少薄膜电阻。在同时，虽然硅化工艺之前创建其降低高度，闸电极的实质完整硅化可抑制，而可减少任何阈值变异，同时相比传统的技艺，也保持边缘电容在较低水平。另一方面，凹槽式程度，如果有的话，以应变诱导半导体合金形式形成在漏极和源极区的多余材料的数量的基础上，在P沟道晶体管可调整，从而使栅极的高度有效减少，其中，之前提供的多余的材料的基础上，可调整漏极和源极区的终于取得的水平。因此，半导体合金的应变诱导效应可实质维持，而同时对降低晶体管变异和减少边缘电容也可以提供降低栅极高度与金属硅化物形成的增强可控性。
将参考图2a-2f详细进一步说明实施例，其中如果合适，还参考图1a和1b。
图2a示意说明半导体器件200的横截面视图，半导体器件200包括衬底201，其上可形成半导体层203。提供埋式绝缘层202时，半导体层203与衬底201结合可至少在器件200的一些器件区域中形成SOI配置。在其他情况下，图2a所示的层202可为实质晶体材料，如衬底201的上部分。此外，如浅沟隔离之类的隔离结构204可以分别对晶体管250a，250b定义相应的有源区203a，203b。例如，晶体管250a可为N沟道晶体管，而晶体管250b可为P沟道晶体管。在所示制造阶段，晶体管250a，250b可包括栅电极251栅极绝缘层252和形成在栅电极251的侧壁的部分的间隔结构255，从而暴露上侧壁部分251s。此外，漏极和源极区254可形成于有源区203a，203b中，其可侧向包围各自的沟道区域253。在一些如图2a所示的实施例中，如果沟道区域253内需要相应的压缩应变，则晶体管250b可以包括应变诱导半导体合金205，如硅/锗合金，硅/锗/锡合金，硅/锡合金之类的。
在相应的制造技术的基础上，可形成半导体器件200，也参照如器件100所描述。因此，如前所述，在相应的蚀刻和清洗工艺以制备半导体器件200在漏极和源极区254和栅电极251接收金属硅化物时，侧壁部分251s可已经暴露，传统其可在硅化工艺导致一定程度的金属“回绕”，因而可导致中度高扩散率和硅化率。因此，如前所述，增加的硅化率助于晶体管特性的相应的变异。
图2b示意图说明在先进制造阶段的半导体器件200。如图所示，该器件200暴露在蚀刻环境206，其在适当的化学蚀刻的基础上，在一实施例可建立等离子环境，以对硅材料(有关二氧化硅，氮化硅，等等)，获取高度蚀刻选择性。例如，根据完善的技术，间隔结构255可由氮化硅材料组成，可能与以二氧化硅为基础的蚀刻衬垫255a组合。在此种情况下，完善的高选择性蚀刻配方可使用于建立工艺206。举例来说，可使用类似的工艺配方，如图案化栅电极251时通常采用的。因此，在蚀刻工艺206中，栅电极251的材料可选择性移除到间隔结构255，而在同时关于隔离结构204和间隔结构255，可选择性移除漏极和源极区254。因此，相应的凹槽206r，形成于漏极和源极区254中，至少在晶体管250a，而在晶体管250b中，取决于半导体合金205的初始厚度，可得到实质的平面配置，如图所示，而在另一些情况下，一定程度的多余高度仍可维持或可产生凹槽，然而相比于凹槽206r，带有不太明显的深度。凹槽206r可定义为器件区域，其中表面206s可有部分例如中心部分，其高度水平相比栅极绝缘层252和沟道区域253之间的接口的高度水平较低。在蚀刻工艺206，栅电极251的初始高度也降低，以获得降低的栅极高度251r，其可以选择因此间隔结构255可以延伸栅电极251上。因此，有关于仍形成接触元件，降低栅极高度251r使降低的边缘电容，而在同时，在硅化工艺期间可使用的栅电极251的表面面积，可受到间隔结构255限制，从而也降低了整体的硅化率。因此，在以后的生产阶段沉积应力介质材料的基础上，实施有效的应变诱导机制的增强的表面形貌可提供蚀刻工艺206，至少在晶体管250a，硅化工艺的增强的可控性也可提供，其中由于减少边缘电容，另外的降低高度251R提供增强的晶体管性能。另一方面，可以执行工艺206作为非掩模工艺，从而不过度于总体工艺复杂性，例如，在另外的光刻步骤和其他类似方面。蚀刻工艺206可包括额外的清洗配方，例如，湿式化学蚀刻工艺的基础上，为以后的硅化工艺，准备漏极和源极区254和栅电极251的暴露部分。
图2c示意图说明在先进制造阶段的半导体器件200。如图所示，金属硅化物区域256(如镍/铂硅化物区域)形成于晶体管250a，250b的漏极和源极区。由于至少晶体管250a的漏极和源极区254的凹槽式，比图1b所示的传统配置，可获得区域256的增加表面面积，从而提高晶体管250a的整体电导率。此外，还有金属硅化物256可定义凹槽式的配置，也就是说，至少表面部分256s可在相比栅极绝缘层252和沟道区域253之间的接口的高度水平较低的高度水平。
应当明白，任何位置信息将视为相对位置说明，其中使用衬底201作为参考。沟道区域253和金属硅化物区域256形成在衬底201“上面”，但其中与栅极绝缘层252和沟道区域253之间的接口相比，表面部分256s则“较低”。
此外，栅电极251包括金属硅化物区域257，其可通过掺杂多晶硅材料251b从栅极绝缘层252隔开。应当明白，由于定义相应的漏极和源极区254的之前的植入工艺，多晶硅材料251d的掺杂程度可能在晶体管250a，250b会有所不同。因此，各自晶体管250a，250b的阈值特性可取决于相应掺硅区域251b。因此，虽然栅电极251的总高度可降低，但可形成定义良好的金硅化物属部分(如区域257)，也保持硅基材料(如材料251b)，以降低实质完全silicidizing初始硅基栅电极材料的可能性，传统其可导致重大的栅极阈值的变异。
可在行之有效的工艺的基础上，形成金属硅化物区域256和257，在工艺中，可沉积适当的耐火金属(如镍，铂之类)，并且可以通过执行适当的热处理将该耐火金属转换成金属硅化物。此后，行之有效的选择性蚀刻技术的基础上，可移除任何未反应的金属材料，其中如果需要的话，将紧跟附加热处理，用以稳定总体特征。在硅化工艺中，间隔结构255可以可靠地覆盖栅电极251的侧壁，从而避免任何重大的金属“环绕式”，以便可完成硅化工艺的增强的可控性和统一性。因此，可以高度可控的方式，获得金属硅化物区域257所需的厚度。
图2d根据进一步实施例示意说明半导体器件200，其中漏极和源极区254的凹槽式程度可脱钩栅电极251的减少高度的一定程度。在一实施例，在实质对应于如图2a所示半导体器件200的生产阶段中，可执行蚀刻工艺206a(如等离子蚀刻工艺)，以获得实质的各向异性蚀刻行为，从而在晶体管250a的漏极和源极区254中实质定义凹槽206r的期望程度，而对晶体管大程度的凹槽式不期望时，可对晶体管250b中的半导体合金205提供高效多余材料。例如，在行之有效的高选择性的蚀刻配方的基础上，可以执行蚀刻工艺206a，如先前所描述的。应该明白，取决于凹槽206r的期望程度，也可在栅电极251中获得凹槽206g的相应程度。
图2e示意说明暴露在进一步蚀刻环境206b时的半导体器件200，蚀刻环境206b可设计为选择性湿式化学蚀刻环境，以较好移除栅电极251中的材料，而实质保持晶体管250a的凹槽206r的期望程度。例如，通过氢氧化四甲基铵(TMAH)可设立蚀刻环境206b，TMAH对蚀刻暴露光阻材料是行之有效的材料。然而，在高浓度和约50-80℃的升高温度中，TMAH可以有效的蚀刻硅材料，其中在氧化硅，氮化硅和之类的方面可实现高选择性。此外，相比于多晶硅材料，在有高度N-掺杂的晶体硅材料中的TMAH的蚀刻率可能会显着放缓。因此，栅电极251的高度可有效减少，而在晶体管250a的漏极和源极区254的凹槽206r的显着增加是可以避免的。另一方面，在工艺206b中，p-掺杂半导体合金205也可移除，其中可以选择以前提供的多余的高度，可取得在晶体管250b凹槽的期望程度或实质平面配置或多余的高度的降低程度。也就是说，在形成半导体合金205的相应的选择性外延生长工艺的期间，可提供半导体合金材料的相应的多余的量，以便考虑到工艺步骤206a和206b组成的蚀刻顺序，以对晶体管250b的漏极和源极区254获得所需的形貌。因此，在蚀刻工艺206b的基础上，凹槽206r的最终闸栅极高度251r和深度可实质彼此脱钩，以鉴于缩短相应的pn结等等，提供进一步降低边缘电容而不降低在漏极和源极区254形成金属硅化物区域的相应的硅化工艺的可靠性。
此后，进一步的处理可继续下去，就像以前参照图2c的描述。
图2f示意图说明进一步的先进制造阶段的半导体器件200。如图所示，层间电介质材料211形成在晶体管250a，250b上，例如，以二氧化硅材料的形式，其中也可对晶体管250a和晶体管250b分别提供应变诱导部分210a和应变诱导部分210b。例如，如前所述，可提供层210a，210b，作为有理想的内应力水平的氮化硅材料，从而分别提高晶体管250a，250b的性能。在所示的实施例中，晶体管250a可为N沟道晶体管，因此以拉伸应力材料(可能与蚀刻停止材料之类的组合)的形式，可提供层210a，如根据相应的工艺需要的。另一方面，以压缩应力硅氮化物材料(或任何其他适当的材料)的形式，可提供层210b，从而提高晶体管250b的性能。因此，由于至少晶体管250a的漏极和源极区254的凹槽式配置，相应的应力分量可以更有效地作用于沟道区域253，如前所述，从而在沟道区域253内提供较高的应变水平，即使例如关于器件200之类的整体包装密度，层210a一般要用减少的厚度。另一方面，晶体管250b可有材料205和层210b的联合的应变效应。但是，对层210a，210b可以使用任何其他配置，其取决于器件的整体技术。例如，在一些实施例，层210a，210b可提供相同的内应力水平，从而大为降低整个工艺的复杂性。在此情况下，可使用高应力水平，如拉应力，以提高晶体管250a的性能，而可由材料205补偿或过补偿晶体管250b中的相应的应力作用。在实施例中，在之前的制造工艺中，可保持材料205的多余的高度，从而进一步降低层210b的效应。在其他情况下，可沉积拉伸应力材料，例如，通过离子注入之类，随后晶体管250b上可选择地放宽(relaxed)。
此后，层间电介质材料211可依据行之有年的工艺技术沉积和可平坦化。其次，可执行相应的光刻和蚀刻工艺，以获得相应的接触开口，其中要形成显示为虚线的接触元件212。为了这个目的，也可采用行之有年的工艺技术。因此，由于其高度降低，相应的接触元件212可产生栅电极251减少的边缘电容，而尽管如此，对晶体管250a，250b的良好定义的阈值行为可提供部分251b。
因此，本发明提供半导体器件和其形成技术，其中许多提高性能机制可以实现，而避免或至少大为减少任何结合的负面缺陷。也就是说，可实现凹槽式漏极和源极配置，而不会过度增加工艺的复杂性，在同一蚀刻顺序也可实现栅极高度的减少。另一方面，在漏极和源极区的凹槽式，栅极高度的减少致随后的硅化工艺的统一性和可靠性提高。因此，由于凹槽式漏极和源极配置，可以实现降低边缘电容结合降低阈值变异和提高晶体管的性能。
虽然已在上述实施方式提出至少示范实施例，但应了解到有大量的变化例存在。也应了解到，在此所描述的示范实施例并非意图以任何方式限制本发明的范围、应用性和组构。相反地，上述实施方式将提供本技术领域之人士实施所述实施例的方便蓝图。樱了解到，在不超出权利要求书所界定的范围的情况下，可对组件的功能和配置作出各种改变，此范围包含在提出此专利申请时的已知等效物和预知等效物。

Claims (25)

1.一种半导体器件，包括：
在半导体材料内形成的第一晶体管的漏极和源极区，相较于该第一晶体管的栅极绝缘层的表面定义的高度水平，该漏极和源极区有一凹槽式表面部分置于较低的高度水平；
该栅极绝缘层上形成的栅电极，该栅电极包含该栅极绝缘层上形成的掺硅材料和该掺硅材料上形成的金属硅化物材料；
间隔结构，具有较该栅电极的高度更高的高度；以及
形成于该漏极和源极区内的金属硅化物区域。
2.如权利要求1所述的半导体器件，其还包括包含漏极和源极区的第二晶体管，该漏极和源极区包含应变诱导半导体合金。
3.如权利要求2所述的半导体器件，其中，该第二晶体管的该漏极和源极区的表面相对于该第一晶体管的该漏极和源极区的该凹槽式表面部分置于较高的高度水平。
4.如权利要求3所述的半导体器件，其中，相对于该第二晶体管的栅极绝缘层，该第二晶体管的该漏极和源极区的该表面非凹槽式。
5.如权利要求1所述的半导体器件，还包括形成于该第一晶体管的该漏极和源极区上面的第一应变诱导介电层，其中，该第一应变诱导介电层在该第一晶体管的沟道区域诱导应变。
6.如权利要求5所述的半导体器件，还包括形成于该第二晶体管的该漏极和源极区上面的第二应变诱导介电层，其中，该第一和第二应变诱导介电层诱导不同类型的应变。
7.如权利要求2所述的半导体器件，其中，该第一晶体管是N沟道晶体管，而该第二晶体管是P沟道晶体管。
8.一种方法，包括：
于晶体管的栅电极的侧壁上形成间隔结构；
将该晶体管的漏极和源极区和该栅电极暴露于蚀刻环境，以至少从该栅电极选择性地移除材料至该间隔结构；
移除该材料后，于该漏极和源极区和该栅电极中形成金属硅化物材料；以及
于該栅电极和漏极和該源极区上面形成应变诱导层。
9.如权利要求8所述的方法，其中，将漏极和源极区和该栅电极暴露于该蚀刻环境还包括移除该漏极和源极区的材料，以形成凹槽式漏极和源极配置。
10.如权利要求8所述的方法，其中，将漏极和源极区和该栅电极暴露于该蚀刻环境还包括于等离子环境的基础上建立该蚀刻环境。
11.如权利要求8所述的方法，其中，将漏极和源极区和该栅电极暴露于该蚀刻环境还包括于湿式化学配方的基础上建立该蚀刻环境。
12.如权利要求11所述的方法，其中，该湿式化学蚀刻配方包含氢氧化四甲基铵。
13.如权利要求12所述的方法，还包括使用不同的蚀刻配方，进行至少一个进一步蚀刻工艺。
14.如权利要求8所述的方法，还包括形成该间隔结构之前，于第二晶体管的漏极和源极区形成半导体合金。
15.如权利要求14所述的方法，其中，将该第一晶体管的该漏极和源极区和该栅电极与该第二晶体管的漏极和源极区和该栅电极暴露于该蚀刻环境后，形成该半导体合金，该半导体合金带有多余的高度，以确定该第二晶体管漏极和源极区的目标高度水平。
16.如权利要求15所述的方法，其中，该目标高度水平对应于实质非凹槽式漏极和源极配置。
17.如权利要求8所述的方法，还包括于该栅电极结构和该漏极和源极区上面形成应变诱导电介质层。
18.如权利要求8所述的方法，其中，形成该金属硅化物，以不延伸到该栅电极结构的栅极绝缘层。
19.一种方法，包括：
执行蚀刻工艺，以从第一晶体管的第一栅电极和第二晶体管的第二栅电极和该第一和第二晶体管的至少之一的漏极和源极区移除材料，但通过间隔结构保护该第一和第二栅电极的侧壁；以及
在该间隔结构的存在下，在该第一和第二闸电极和该漏极和源极区中形成金属硅化物，该金属硅化物在该第一和第二闸电极的掺硅材料中终止。
20.如权利要求19所述的方法，其中，该蚀刻工艺是在等离子环境的基础上进行。
21.如权利要求19所述的方法，其中进行该蚀刻工艺包括进行湿式化学蚀刻工艺。
22.如权利要求21所述的方法，其中该湿式化学蚀刻工艺是在氢氧化四甲基铵的基础上进行。
23.如权利要求19所述的方法，进行该蚀刻工艺之前，进一步包括在该第二晶体管的该漏极和源极区中形成半导体合金，其中，提供该半导体合金多余的材料，以维持该第二晶体管中实质非凹槽式漏极和源极配置。
24.如权利要求19所述的方法，进一步包括于该第一晶体管上面形成第一应变诱导介电层，及在该第二晶体管上面形成第二应变诱导介电层。
25.如权利要求24所述的方法，其中，进行该蚀刻工艺以便在该第一晶体管中产生凹槽式漏极和源极配置。
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