CN102132398B - 用于互连的自对准阻挡层 - Google Patents

用于互连的自对准阻挡层 Download PDF

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Publication number
CN102132398B
CN102132398B CN200980112816.0A CN200980112816A CN102132398B CN 102132398 B CN102132398 B CN 102132398B CN 200980112816 A CN200980112816 A CN 200980112816A CN 102132398 B CN102132398 B CN 102132398B
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metal
deposited
copper
manganese
depositing
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CN102132398A (zh
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R·G·戈登
H·金
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Harvard University
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Harvard University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/052—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein
    • H10W20/0526—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by treatments not introducing additional elements therein by thermal treatment thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/16—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/049—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by diffusing alloying elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • H10W20/0552—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition by diffusing metallic dopants to react with dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/0888—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures wherein via-level dielectrics are compositionally different than trench-level dielectrics

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  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
CN200980112816.0A 2008-03-21 2009-03-20 用于互连的自对准阻挡层 Expired - Fee Related CN102132398B (zh)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US3865708P 2008-03-21 2008-03-21
US61/038,657 2008-03-21
US4323608P 2008-04-08 2008-04-08
US61/043,236 2008-04-08
US7446708P 2008-06-20 2008-06-20
US61/074,467 2008-06-20
PCT/US2009/037826 WO2009117670A2 (en) 2008-03-21 2009-03-20 Self-aligned barrier layers for interconnects

Publications (2)

Publication Number Publication Date
CN102132398A CN102132398A (zh) 2011-07-20
CN102132398B true CN102132398B (zh) 2015-01-28

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US (2) US7932176B2 (https=)
JP (1) JP5820267B2 (https=)
KR (2) KR101649714B1 (https=)
CN (1) CN102132398B (https=)
WO (1) WO2009117670A2 (https=)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4783561B2 (ja) * 2004-09-27 2011-09-28 株式会社アルバック 銅配線の形成方法
EP1909320A1 (en) * 2006-10-05 2008-04-09 ST Microelectronics Crolles 2 SAS Copper diffusion barrier
JP5820267B2 (ja) 2008-03-21 2015-11-24 プレジデント アンド フェローズ オブ ハーバード カレッジ 配線用セルフアライン（自己整合）バリア層
JP5280267B2 (ja) * 2009-03-27 2013-09-04 株式会社日本総合研究所 製造方法および車両
JP5507909B2 (ja) * 2009-07-14 2014-05-28 東京エレクトロン株式会社 成膜方法
AU2010310750B2 (en) * 2009-10-23 2015-02-26 President And Fellows Of Harvard College Self-aligned barrier and capping layers for interconnects
CN103400857B (zh) 2009-11-27 2016-12-28 株式会社半导体能源研究所 半导体装置和及其制造方法
US8138084B2 (en) 2009-12-23 2012-03-20 Intel Corporation Electroless Cu plating for enhanced self-forming barrier layers
US20110266676A1 (en) * 2010-05-03 2011-11-03 Toshiba America Electronic Components, Inc. Method for forming interconnection line and semiconductor structure
US9926639B2 (en) 2010-07-16 2018-03-27 Applied Materials, Inc. Methods for forming barrier/seed layers for copper interconnect structures
US8492289B2 (en) 2010-09-15 2013-07-23 International Business Machines Corporation Barrier layer formation for metal interconnects through enhanced impurity diffusion
JP5857970B2 (ja) 2010-11-02 2016-02-10 宇部興産株式会社 （アミドアミノアルカン）金属化合物、及び当該金属化合物を用いた金属含有薄膜の製造方法
US8492897B2 (en) 2011-09-14 2013-07-23 International Business Machines Corporation Microstructure modification in copper interconnect structures
US9190323B2 (en) * 2012-01-19 2015-11-17 GlobalFoundries, Inc. Semiconductor devices with copper interconnects and methods for fabricating same
WO2013153777A1 (ja) * 2012-04-11 2013-10-17 東京エレクトロン株式会社 半導体装置の製造方法、半導体装置、半導体製造装置
US9048294B2 (en) 2012-04-13 2015-06-02 Applied Materials, Inc. Methods for depositing manganese and manganese nitrides
US9076661B2 (en) 2012-04-13 2015-07-07 Applied Materials, Inc. Methods for manganese nitride integration
US9054109B2 (en) * 2012-05-29 2015-06-09 International Business Machines Corporation Corrosion/etching protection in integration circuit fabrications
US8710660B2 (en) * 2012-07-20 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid interconnect scheme including aluminum metal line in low-k dielectric
CN102768988B (zh) * 2012-07-25 2014-10-15 上海华力微电子有限公司 一种有效判定铜扩散阻挡层阻挡能力的方法
JP5969306B2 (ja) 2012-08-08 2016-08-17 東京エレクトロン株式会社 Ｃｕ配線の形成方法
US8765602B2 (en) 2012-08-30 2014-07-01 International Business Machines Corporation Doping of copper wiring structures in back end of line processing
JP6117588B2 (ja) 2012-12-12 2017-04-19 東京エレクトロン株式会社 Ｃｕ配線の形成方法
JP6030439B2 (ja) * 2012-12-27 2016-11-24 東京エレクトロン株式会社 マンガン含有膜の形成方法、処理システム、および電子デバイスの製造方法
JP2014141739A (ja) 2012-12-27 2014-08-07 Tokyo Electron Ltd 金属マンガン膜の成膜方法、処理システム、電子デバイスの製造方法および電子デバイス
US9209134B2 (en) * 2013-03-14 2015-12-08 Intermolecular, Inc. Method to increase interconnect reliability
US9184093B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Integrated cluster to enable next generation interconnect
CN104103575B (zh) * 2013-04-10 2017-12-29 中芯国际集成电路制造(上海)有限公司 铜互连线的形成方法
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
JP6257217B2 (ja) 2013-08-22 2018-01-10 東京エレクトロン株式会社 Ｃｕ配線構造の形成方法
US9362228B2 (en) * 2013-10-22 2016-06-07 Globalfoundries Inc. Electro-migration enhancing method for self-forming barrier process in copper metalization
US9043743B2 (en) * 2013-10-22 2015-05-26 International Business Machines Corporation Automated residual material detection
US9275952B2 (en) 2014-01-24 2016-03-01 International Business Machines Corporation Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects
US9343357B2 (en) * 2014-02-28 2016-05-17 Qualcomm Incorporated Selective conductive barrier layer formation
FR3025396A1 (fr) 2014-09-02 2016-03-04 St Microelectronics Tours Sas Procede de fabrication d'un element de connexion electrique
US9728502B2 (en) * 2014-11-10 2017-08-08 Samsung Electronics Co., Ltd. Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the same
JP2016167545A (ja) * 2015-03-10 2016-09-15 東京エレクトロン株式会社 ビアホール底のクリーニング方法および半導体装置の製造方法
JP2017050304A (ja) 2015-08-31 2017-03-09 東京エレクトロン株式会社 半導体装置の製造方法
US9842805B2 (en) 2015-09-24 2017-12-12 International Business Machines Corporation Drive-in Mn before copper plating
JP6559046B2 (ja) * 2015-11-04 2019-08-14 東京エレクトロン株式会社 パターン形成方法
US20160083405A1 (en) * 2015-11-30 2016-03-24 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Tantalum- or vanadium-containing film forming compositions and vapor deposition of tantalum- or vanadium-containing films
JP2017135237A (ja) * 2016-01-27 2017-08-03 東京エレクトロン株式会社 Ｃｕ配線の製造方法およびＣｕ配線製造システム
US10049974B2 (en) 2016-08-30 2018-08-14 International Business Machines Corporation Metal silicate spacers for fully aligned vias
US10229851B2 (en) 2016-08-30 2019-03-12 International Business Machines Corporation Self-forming barrier for use in air gap formation
US9786760B1 (en) 2016-09-29 2017-10-10 International Business Machines Corporation Air gap and air spacer pinch off
US11024538B2 (en) * 2016-12-31 2021-06-01 Intel Corporation Hardened plug for improved shorting margin
US10760156B2 (en) 2017-10-13 2020-09-01 Honeywell International Inc. Copper manganese sputtering target
CN108047274B (zh) * 2017-12-15 2019-08-20 江南大学 一种铜互连阻挡层材料用吡啶基Mn(Ⅱ)化合物
US10204829B1 (en) 2018-01-12 2019-02-12 International Business Machines Corporation Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers
US11035036B2 (en) 2018-02-01 2021-06-15 Honeywell International Inc. Method of forming copper alloy sputtering targets with refined shape and microstructure
US11152294B2 (en) 2018-04-09 2021-10-19 Corning Incorporated Hermetic metallized via with improved reliability
US11133216B2 (en) 2018-06-01 2021-09-28 International Business Machines Corporation Interconnect structure
WO2020061437A1 (en) 2018-09-20 2020-03-26 Industrial Technology Research Institute Copper metallization for through-glass vias on thin glass
WO2020171940A1 (en) 2019-02-21 2020-08-27 Corning Incorporated Glass or glass ceramic articles with copper-metallized through holes and processes for making the same
US10818589B2 (en) 2019-03-13 2020-10-27 International Business Machines Corporation Metal interconnect structures with self-forming sidewall barrier layer
JP7161767B2 (ja) * 2019-04-22 2022-10-27 気相成長株式会社 形成材料、形成方法、及び新規化合物
KR20220053482A (ko) * 2020-10-22 2022-04-29 에이에스엠 아이피 홀딩 비.브이. 바나듐 금속을 증착하는 방법, 구조체, 소자 및 증착 어셈블리
CN112687617B (zh) * 2020-12-24 2022-07-22 中国电子科技集团公司第十三研究所 绝缘子针的制备方法及绝缘子针

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6413815B1 (en) * 2001-07-17 2002-07-02 Macronix International Co., Ltd. Method of forming a MIM capacitor
CN1726303A (zh) * 2002-11-15 2006-01-25 哈佛学院院长等 使用脒基金属的原子层沉积
CN1945825A (zh) * 2005-10-03 2007-04-11 恩益禧电子股份有限公司 半导体器件及其制作方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060534A (en) 1996-07-11 2000-05-09 Scimed Life Systems, Inc. Medical devices comprising ionically and non-ionically crosslinked polymer hydrogels having improved mechanical properties
US6951682B1 (en) 1998-12-01 2005-10-04 Syntrix Biochip, Inc. Porous coatings bearing ligand arrays and use thereof
KR100383759B1 (ko) 2000-06-15 2003-05-14 주식회사 하이닉스반도체 반도체 소자의 구리 금속 배선 형성 방법
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
KR100563817B1 (ko) 2003-12-30 2006-03-28 동부아남반도체 주식회사 반도체 소자의 구리 배선 형성 방법
JP4478038B2 (ja) 2004-02-27 2010-06-09 株式会社半導体理工学研究センター 半導体装置及びその製造方法
DE102004019241A1 (de) 2004-04-16 2005-11-03 Cellmed Ag Injizierbare vernetzte und unvernetzte Alginate und ihre Verwendung in der Medizin und in der ästhetischen Chirurgie
US7879710B2 (en) 2005-05-18 2011-02-01 Intermolecular, Inc. Substrate processing including a masking layer
EP1909320A1 (en) * 2006-10-05 2008-04-09 ST Microelectronics Crolles 2 SAS Copper diffusion barrier
JP4236201B2 (ja) * 2005-08-30 2009-03-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4272191B2 (ja) * 2005-08-30 2009-06-03 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
WO2007066277A2 (en) 2005-12-07 2007-06-14 Nxp B.V. A method of forming a layer over a surface of a first material embedded in a second material in a structure for a semiconductor device
KR101351286B1 (ko) * 2005-12-20 2014-02-17 시바 홀딩 인크 옥심 에스테르 광개시제
JP2007173511A (ja) * 2005-12-22 2007-07-05 Sony Corp 半導体装置の製造方法
JP4741965B2 (ja) * 2006-03-23 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007308789A (ja) 2006-04-19 2007-11-29 Tokyo Electron Ltd 成膜装置及び成膜方法
JP2008013848A (ja) 2006-06-08 2008-01-24 Tokyo Electron Ltd 成膜装置及び成膜方法
US20080032064A1 (en) 2006-07-10 2008-02-07 President And Fellows Of Harvard College Selective sealing of porous dielectric materials
JP5145225B2 (ja) * 2006-07-14 2013-02-13 株式会社アルバック 半導体装置の製造方法
KR101629965B1 (ko) * 2007-04-09 2016-06-13 프레지던트 앤드 펠로우즈 오브 하바드 칼리지 구리 배선용 코발트 질화물층 및 이의 제조방법
DE102007035837A1 (de) * 2007-07-31 2009-02-05 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einer Kornorientierungsschicht
US7884475B2 (en) * 2007-10-16 2011-02-08 International Business Machines Corporation Conductor structure including manganese oxide capping layer
US20090117731A1 (en) * 2007-11-01 2009-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnection structure and method for making the same
US7555191B1 (en) 2008-01-30 2009-06-30 Joshua John Edward Moore Self-locking unidirectional interposer springs for optical transceiver modules
US7651943B2 (en) * 2008-02-18 2010-01-26 Taiwan Semicondcutor Manufacturing Company, Ltd. Forming diffusion barriers by annealing copper alloy layers
JP5820267B2 (ja) * 2008-03-21 2015-11-24 プレジデント アンド フェローズ オブ ハーバード カレッジ 配線用セルフアライン（自己整合）バリア層

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077774A (en) * 1996-03-29 2000-06-20 Texas Instruments Incorporated Method of forming ultra-thin and conformal diffusion barriers encapsulating copper
US6203613B1 (en) * 1999-10-19 2001-03-20 International Business Machines Corporation Atomic layer deposition with nitrate containing precursors
US6413815B1 (en) * 2001-07-17 2002-07-02 Macronix International Co., Ltd. Method of forming a MIM capacitor
CN1726303A (zh) * 2002-11-15 2006-01-25 哈佛学院院长等 使用脒基金属的原子层沉积
CN1945825A (zh) * 2005-10-03 2007-04-11 恩益禧电子股份有限公司 半导体器件及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2008-13848A 2008.01.24 *

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US20090263965A1 (en) 2009-10-22
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