CN102024721A - 形成qfn集成电路封装的可焊接侧表面端子的方法 - Google Patents

形成qfn集成电路封装的可焊接侧表面端子的方法 Download PDF

Info

Publication number
CN102024721A
CN102024721A CN2010102486162A CN201010248616A CN102024721A CN 102024721 A CN102024721 A CN 102024721A CN 2010102486162 A CN2010102486162 A CN 2010102486162A CN 201010248616 A CN201010248616 A CN 201010248616A CN 102024721 A CN102024721 A CN 102024721A
Authority
CN
China
Prior art keywords
encapsulation
terminal
indivedual
bottom side
scolder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2010102486162A
Other languages
English (en)
Other versions
CN102024721B (zh
Inventor
肯尼思·J·许宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxim Integrated Products Inc
Original Assignee
Maxim Integrated Products Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maxim Integrated Products Inc filed Critical Maxim Integrated Products Inc
Publication of CN102024721A publication Critical patent/CN102024721A/zh
Application granted granted Critical
Publication of CN102024721B publication Critical patent/CN102024721B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48105Connecting bonding areas at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48175Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/48177Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明揭示一种形成集成电路(IC)封装的方法,其包含:(a)从所述IC封装的端子的侧表面移除氧化物;(b)大致覆盖所述IC封装的所述端子的底侧;以及(c)在覆盖所述IC封装的所述端子的所述底侧的同时,在所述IC封装的端子的所述侧表面上形成焊料涂层。所述端子的所述侧表面上的所述焊料涂层保护所述端子免受因老化和后续过程所致的氧化。另外,所述端子的所述侧表面上的所述焊料涂层大致改善所述IC封装到印刷电路板(PCB)或其它安装件的可焊接性。此进一步促进使用较不昂贵且较不复杂的方法对焊料附接的检验。

Description

形成QFN集成电路封装的可焊接侧表面端子的方法
相关申请案交叉参考
本申请案请求对2009年8月6日提出申请且标题为“形成四边无引线框架(QFN)集成电路封装的可焊接侧表面端子的方法(Method of Forming Solderable Side-SurfaceTerminals of Quad No-lead Frame(QFN)Integrated Circuit Packages)”的第61/231,945号临时专利申请案的权益,所述申请案以引用方式并入本文中。
技术领域
本发明一般来说涉及集成电路(IC)封装,且特定来说涉及一种形成四边无引线框架(QFN)IC封装或类似物的可焊接侧表面端子的方法。
背景技术
在制造四边无引线框架(QFN)或薄QFN(TQFN)集成电路(IC)封装的典型过程中,所支持半导体裸片的阵列电连接到共用引线框架,且通常由注入模制的化合物囊封。然后,所述经囊封结构经历单片化过程,其中将所述结构切片,以便形成个别IC封装,每一封装囊封对应半导体裸片及其它相关元件。如下文更详细论述,所述单片化过程产生将暴露于环境中的封装端子的不受保护侧。因此,氧化物可在所述端子侧上形成,此可在所述IC封装到印刷电路板(PCB)上的随后组装期间导致所述IC端子的不良可焊接性。参照以下实例更好地对此进行解释。
图1A图解说明实例性QFN IC封装阵列100在单片化制造步骤之前的透明正视图。在此实例中,为便于解释,仅显示两个(2)邻近QFN封装101-1及101-2。每一QFN封装(101-1或101-2)可包含通过粘合剂层(108-1或108-2)牢固地安置于热垫(110-1或110-2)上的半导体裸片(104-1或104-2)。每一半导体裸片(104-1或104-2)包括通过相应线接合(112-1或112-2)电耦合到铜(Cu)引线框架120的接触垫(106-1或106-2)。在集成阵列100中,邻近半导体裸片的接触垫经由对应的线接合连接到引线框架120的同一端子。在单片化之前,使用(举例来说)电镀过程在引线框架120的端子中的每一者的底侧上形成可焊接镀层130(Sn基镀层)的薄涂层。在单片化期间,在邻近QFN封装之间的中点处沿大致垂直线将阵列100切片,如切割虚线所图解说明。可使用冲压或锯割工具执行阵列100的切割。
图1B图解说明实例性QFN IC封装101-1在单片化制造步骤的完成之后的透明正视图。注意,QFN IC封装101-1的端子120-1的底侧大致由安置于其上的可焊接涂层130-1覆盖。此保护端子120-1的底侧以免由于QFN IC封装101-1的老化及/或随后处理而氧化。然而,可焊接涂层130-1不存在于个别QFN IC封装的切割或分离发生的端子120-1的侧上。相应地,不保护端子120-1的侧免受因老化及随后处理所致的氧化。因此,端子120-1的侧易于氧化且暴露于其它污染物。端子120-1的侧表面122-1由点阴影表示,以便表示氧化及污染的表面,如图1C中最佳所示。此类表面通常具有不良可焊接性性质,此可使QFN封装到PCB上的组装困难且不可靠。所述不良可焊接性性质可导致焊料球的形成及其它缺陷在所述IC封装的侧端子上形成。
发明内容
本发明的一方面涉及一种形成集成电路(IC)封装的方法,所述方法包含:(a)从所述IC封装的端子的侧表面移除氧化物;(b)大致覆盖所述IC封装的所述端子的底侧;以及(c)在覆盖所述IC封装的所述端子的所述底侧的同时,在所述IC封装的所述端子的所述侧表面上形成焊料涂层。所述端子的所述侧表面上的所述焊料涂层保护所述端子免受因老化和后续过程所致的氧化。另外,所述端子的所述侧表面上的所述焊料涂层大致改善所述IC封装到印刷电路板(PCB)或其它安装件的可焊接性。此进一步促进使用较不昂贵且较不复杂的方法对焊料附接的检验。
结合附图考虑以下对本发明的详细描述,将显而易见本发明的其它方面、优点及新颖特征。
附图说明
图1A图解说明实例性QFN IC封装阵列在单片化制造步骤之前的透明正视图。
图1B图解说明实例性QFN IC封装中的一者在单片化制造步骤的完成之后的透明正视图。
图1C图解说明实例性QFN IC封装中的一者在单片化制造步骤的完成之后的非透明侧视图。
图2图解说明形成IC封装的实例性方法的流程图及所述实例性IC封装在根据本发明的方面的方法的各个阶段处的侧视图。
图3图解说明形成IC封装的另一实例性方法的流程图及所述实例性IC封装在根据本发明的另一方面的方法的各个阶段处的侧视图。
图4图解说明处理多个IC封装的实例性方法的流程图及所述IC封装在根据本发明的另一方面的方法的各个阶段处的侧视图。
图5图解说明处理多个IC封装的另一实例性方法的流程图及所述IC封装在根据本发明的另一方面的方法的各个阶段处的侧视图。
具体实施方式
图2图解说明形成IC封装的实例性方法200的流程图及实例性IC封装101-1在根据本发明的方面的方法的各个阶段处的侧视图。尽管使用QFN或TQFN型IC封装来图解说明本文中所描述方法的概念,但应理解,方法200可应用于其它类型的IC封装。方法200的开始点为IC封装101-1已经历单片化过程,且已给端子120-1的底侧涂覆可焊接材料的薄层130-1。
根据方法200,IC封装101-1且具体来说其端子120-1的经切割侧表面122-1经受助溶剂215(及/或其它溶液及/或处理)以从端子120-1的侧表面122-1大致移除氧化层及/或其它污染物(步骤210)。步骤210的目的是针对随后的焊料涂覆操作准备铜暴露表面122-1。
然后,将IC封装101-1的底侧牢固地安置于覆盖物或密封物225(例如,顺从性垫片,其由橡胶化弹性材料、高温硅酮或其它材料制成)上(步骤220)。步骤220的目的是保护端子120-1的底侧上的焊料涂层130-1以免暴露于随后的侧端子焊料涂覆过程及其它相关化学品及环境条件。可采用装置(例如,夹子)将IC封装101-1牢固地附接到覆盖物225,如分别施加到所述IC封装的顶部及覆盖物225的底部的负性力(-F)及正性力(+F)所表示。所述装置应以非机械破坏方式将IC封装101-1固定到覆盖物225,以使得其不会对所述IC封装的顶部表面形成明显划痕。所述固定装置还应承受与随后的焊料涂覆步骤相关联的环境条件,其可经受高达220℃到260℃的温度。举例来说,所述固定装置可由可承受此类温度的弹性材料制成。
在已将覆盖物225固定到IC封装101-1的底侧之后,端子120-1的侧表面经受焊料浴235以便在其上形成薄的低表面张力焊料涂层140-1(例如,Sn基焊料)(步骤230)。所述薄焊料涂层140-1保护端子120-1的侧免受氧化及因暴露于环境而产生的其它有害影响。另外,焊料涂层140-1提供IC封装101-1的端子120-1的额外可焊接表面。此大致改善IC封装101-1到PCB上的组装。薄焊料涂层140-1的可接受标准可为端子120-1的侧表面的至少50%由所述焊料涂层覆盖。
所述焊料涂覆过程可涉及首先执行在纯氮环境中将IC封装101-1慢慢预加热到大致接近焊料浴235的温度的温度,然后使IC封装101-1经受所述焊料浴。此减小IC封装101-1上的热应力。另外,在已完成焊料涂层130-1之后,再允许IC封装101-1慢慢冷却以便减小IC封装101-1上的热应力。
在所述焊料涂覆过程完成之后,从IC封装101-1移除所述固定装置及覆盖物225,且使所述IC封装经受清洁过程(例如,用DI水清洗)以便从所述IC封装移除残余助溶剂、焊料及/或其它污染物(步骤240)。另外,可在使所述IC封装101-1经历激光标记步骤及最终电测试之后将其装运到最终用户以最终组装到产品上。
图3图解说明形成IC封装的另一实例性方法300的框图及实例性IC封装101-1在根据本发明的另一方面的方法的各个阶段处的侧视图。此外,尽管使用QFN或TQFN型IC封装来图解说明本文中所描述的方法的概念,但应理解,方法300可应用于其它类型的IC封装。类似地,方法300的开始点为IC封装101-1已经历单片化过程,且已给端子120-1的底侧涂覆可焊接材料的薄层130-1。
根据方法300,将IC封装101-1的底侧牢固地安置于覆盖物或密封物225(例如,顺从性垫片,其由橡胶化弹性材料、高温硅酮或其它材料制成)上(步骤310)。步骤310的目的是保护端子120-1的底侧上的焊料涂层130-1以免暴露于随后的处理(例如,助溶剂施加及焊料涂覆过程)及其它相关化学品及环境条件。可采用装置(例如,夹子)将IC封装101-1牢固地附接到覆盖物225,如分别施加到所述IC封装的顶部及覆盖物225的底部的负性力(-F)及正性力(+F)所表示。所述装置应以非机械破坏方式将IC封装101-1固定到覆盖物225,以使得其不会对所述IC封装的顶部表面形成明显划痕。所述固定装置还应承受与随后的过程相关联的环境条件,其可经受高达220℃到260℃的温度。举例来说,所述固定装置可由可承受此类温度的弹性材料制成。
然后,根据方法300,IC封装101-1且具体来说其端子120-1的侧表面122-1经受助溶剂215(及/或其它溶液及/或处理)以从端子120-1的侧表面122-1大致移除氧化层及/或其它污染物(步骤320)。步骤320的目的是针对随后的焊料涂覆操作准备表面122-1。在此情况下,覆盖物225保护焊料涂层130-1及IC封装101-1的底侧免受所述助溶剂施加过程。
在从端子120-1的侧表面122-1移除所述氧化物及污染物之后,端子120-1的所述侧表面经受焊料浴235以便在其上形成薄的低表面张力焊料涂层140-1(例如,Sn基焊料)(步骤330)。所述薄焊料涂层140-1保护端子120-1的侧免受氧化及因暴露于环境而产生的其它有害影响。另外,焊料涂层140-1提供IC封装101-1的端子120-1的额外可焊接表面。此大致改善IC封装101-1到PCB上的组装。薄焊料涂层140-1的可接受标准可为端子120-1的侧表面的至少50%由所述焊料涂层覆盖。
所述焊料涂覆过程可涉及首先执行在纯氮环境中将IC封装101-1慢慢预加热到大致接近焊料浴235的温度的温度,然后使IC封装101-1经受所述焊料浴。此减小IC封装101-1上的热应力。另外,在已完成焊料涂层130-1之后,再允许IC封装101-1慢慢冷却以便减小IC封装101-1上的热应力。
在所述焊料涂覆过程完成之后,从IC封装101-1移除所述固定装置及覆盖物225,且使所述IC封装经受清洁过程(例如,用DI水清洗)以便从所述IC封装移除残余助溶剂、焊料及/或其它污染物(步骤340)。另外,可在使所述IC封装101-1经历激光标记步骤及最终电测试之后将其装运到最终用户以最终组装到产品上。
图4图解说明处理多个IC封装的实例性方法400的流程图及所述IC封装在根据本发明的另一方面的方法的各个阶段处的侧视图。此方法400特别适于同时处理多个(例如,两个或两个以上)IC封装。尽管使用QFN或TQFN型IC封装来图解说明本文中所描述方法的概念,但应理解,方法400可应用于其它类型的IC封装。类似地,方法400的开始点为IC封装101-1已经历单片化过程,且已给其端子底侧涂覆可焊接薄层。
根据方法400,多个IC封装101-1且具体来说其端子侧表面经受助溶剂215(及/或其它溶液及/或处理)以从所述端子的所述侧表面大致移除氧化层及/或其它污染物(步骤410)。步骤410的目的是针对随后的焊料涂覆操作准备铜暴露端子表面。
然后,形成IC封装101-1及覆盖物或密封物225的堆叠(框420)。通过此堆叠布置,将每一IC封装101-1的底侧牢固地安置于覆盖物或密封物225(例如,顺从性垫片,其由橡胶化弹性材料、高温硅酮等制成)上。步骤420的目的是保护所述端子的底侧上的焊料涂层以免暴露于随后的侧端子焊料涂覆过程及其它相关化学品及环境条件。可采用装置(例如,夹子)(如由分别施加到所述堆叠的顶部及底部IC封装的负性力(-F)及正性力(+F)所表示)来牢固地维持所述堆叠布置。所述装置应以非机械破坏方式牢固地维持所述堆叠布置,以使得其不会对所述顶部及底部IC封装形成明显划痕。所述固定装置还应承受与随后的焊料涂覆步骤相关联的环境条件,其可经受高达220℃到260℃的温度。举例来说,所述固定装置可由可承受此类温度的弹性材料制成。
在已形成所述堆叠布置之后,IC封装101-1的端子的侧表面经受焊料浴235以便在其上形成薄的低表面张力焊料涂层(例如,Sn基焊料)(步骤430)。所述薄焊料涂层保护所述端子的侧免受氧化及因暴露于环境而产生的其它有害影响。另外,所述焊料涂层提供IC封装101-1的所述端子的额外可焊接表面。此大致改善IC封装101-1到PCB上的组装。所述薄焊料涂层的可接受标准可为每一IC封装端子的侧表面的至少50%由所述焊料涂层覆盖。
所述焊料涂覆过程可涉及首先执行在纯氮环境中将IC封装101-1慢慢预加热到大致接近焊料浴235的温度的温度,然后使IC封装101-1经受所述焊料浴。此减小IC封装101-1上的热应力。另外,在已完成所述焊料涂层之后,再允许IC封装101-1慢慢冷却以便减小所述IC封装上的热应力。
在所述焊料涂覆过程完成之后,拆除所述堆叠布置,且使IC封装101-1经受清洁过程(例如,用DI水245清洗)以便从所述IC封装移除残余助溶剂、焊料及/或其它污染物(步骤440)。另外,可在使所述IC封装101-1经历激光标记步骤及最终电测试之后将其装运到最终用户以最终组装到产品上。
图5图解说明处理多个IC封装的另一实例性方法的流程图及所述IC封装在根据本发明的另一方面的方法的各个阶段处的侧视图。此方法500也特别适于同时处理多个(例如,两个或两个以上)IC封装。尽管使用QFN或TQFN型IC封装来图解说明本文中所描述方法的概念,但应理解,方法500可应用于其它类型的IC封装。类似地,方法500的开始点为IC封装101-1已经历单个化过程,且已给其端子底侧涂覆可焊接薄层。
根据方法500,形成IC封装101-1堆叠及覆盖物或密封物225(框510)。通过此堆叠布置,将每一IC封装101-1的底侧牢固地安置于覆盖物或密封物225(例如,顺从性垫片,其由橡胶化弹性材料、高温硅等制成)上。步骤510的目的是保护所述端子的底侧上的焊料涂层以免暴露于随后的助溶剂施加及焊料涂覆过程及其它相关化学品及环境条件。可采用装置(例如,夹子)(如由分别施加到顶部及底部IC封装的负性力(-F)及正性力(+F)所表示)来牢固地维持所述堆叠布置。所述装置应以非机械破坏方式牢固地维持所述堆叠布置,以使得其不会对所述顶部及底部IC封装形成明显划痕。所述固定装置还应承受与随后的焊料涂覆步骤相关联的环境条件,其可经受高达220℃到260℃的温度。举例来说,所述固定装置可由可承受此类温度的弹性材料制成。
在形成所述堆叠布置之后,使多个IC封装101-1且具体来说其端子侧表面经受助溶剂215(及/或其它溶液及/或处理)以从所述端子的所述侧表面大致移除氧化层及/或其它污染物(步骤520)。步骤520的目的是针对随后的焊料涂覆操作准备铜暴露端子表面。
在步骤520之后,使IC封装101-1的端子的侧表面经受焊料浴235以便在其上形成薄的低表面张力焊料涂层(例如,Sn基焊料)(步骤530)。所述薄焊料涂层保护所述端子的侧免受氧化及因暴露于环境而产生的其它有害影响。另外,所述焊料涂层提供IC封装101-1的所述端子的额外可焊接表面。此大致改善IC封装101-1到PCB上的组装。所述薄焊料涂层的可接受标准可为每一IC封装端子的侧表面的至少50%由所述焊料涂层覆盖。
所述焊料涂覆过程可涉及首先执行在纯氮环境中将IC封装101-1慢慢预加热到大致接近焊料浴235的温度的温度,然后使IC封装101-1经受所述焊料浴。此减小IC封装101-1上的热应力。另外,在已完成所述焊料涂层之后,再允许IC封装101-1慢慢冷却以便减小所述IC封装上的热应力。
在所述焊料涂覆过程完成之后,拆除所述堆叠布置,且使IC封装101-1经受清洁过程、(例如,用DI水245清洗)以便从所述IC封装移除残余助溶剂、焊料及/或其它污染物(步骤540)。另外,可在使所述IC封装101-1经历激光标记步骤及最终电测试之后将其装运到最终用户以最终组装到产品上。
尽管已结合各种实施例描述了本发明,但应理解本发明可进行进一步修改。本申请案打算涵盖本发明的任何变化形式、使用或修改,所述变化形式、使用或修改一般来说遵循本发明的原理且包括与本发明背离但归属于与本发明相关的技术内的已知及习惯实践范围内的此等变化形式、使用或修改。

Claims (30)

1.一种形成集成电路(IC)封装的方法,其包含:
a)从所述IC封装的端子的侧表面移除氧化物;
b)大致覆盖所述IC封装的所述端子的底侧;以及
c)在覆盖所述IC封装的所述端子的所述底侧的同时,在所述IC封装的所述端子的所述侧表面上形成焊料涂层。
2.根据权利要求1所述的方法,其中所述端子的所述底侧包含可焊接涂层。
3.根据权利要求1所述的方法,其中大致覆盖所述端子的所述底侧包含将所述IC封装置于垫片上。
4.根据权利要求3所述的方法,其中所述垫片包含顺从性或弹性材料。
5.根据权利要求3所述的方法,其中所述垫片包含橡胶或硅酮材料。
6.根据权利要求1所述的方法,其中大致覆盖所述端子的所述底侧包含将所述IC封装的底侧牢固地附接到覆盖物。
7.根据权利要求6所述的方法,其中将所述IC封装的所述底侧牢固地附接到所述覆盖物包含使用机械装置抵靠着所述覆盖物偏置所述IC封装。
8.根据权利要求7所述的方法,其中所述机械装置包含夹子。
9.根据权利要求1所述的方法,其中从所述IC封装的所述端子的所述侧表面移除氧化物包含使所述端子的所述侧表面暴露于助溶剂。
10.根据权利要求1所述的方法,其中在步骤b)之前执行步骤a)。
11.根据权利要求1所述的方法,其中在步骤b)之后执行步骤a)。
12.根据权利要求1所述的方法,其中在大致覆盖所述端子的所述底侧的同时,执行从所述端子的所述侧表面移除氧化物。
13.根据权利要求1所述的方法,其中在所述IC封装的所述端子的所述侧表面上形成所述焊料涂层包含:
将所述IC封装预加热到与焊料浴的温度大致相同的温度;以及
使所述IC封装的所述端子的所述侧表面经受所述焊料浴以形成所述焊料涂层。
14.根据权利要求13所述的方法,其中在所述IC封装的所述端子的所述侧表面上形成所述焊料涂层进一步包含允许所述IC封装从所述焊料浴的大致温度冷却。
15.根据权利要求1所述的方法,其进一步包含清洁所述IC封装以从中移除助溶剂残余物。
16.根据权利要求1所述的方法,其进一步包含清洁所述IC封装以从中移除焊料残余物。
17.根据权利要求1所述的方法,其进一步包含激光标记所述IC封装。
18.根据权利要求1所述的方法,其进一步包含对所述IC封装执行电测试。
19.根据权利要求1所述的方法,其中所述IC封装包含四边无引线框架(QFN)IC封装。
20.根据权利要求1所述的方法,其中所述IC封装包含薄四边无引线框架(TQFN)IC封装。
21.根据权利要求1所述的方法,其进一步包含在执行步骤a)、b)和c)之前执行单片化过程以形成所述IC封装。
22.一种处理多个IC封装的方法,其包含:
从经附接IC封装阵列形成多个个别IC封装;以及
在所述个别IC封装的端子的侧表面上形成焊料涂层。
23.根据权利要求22所述的方法,其中从经附接IC封装阵列形成多个个别IC封装包含沿着连接到经附接IC封装的邻近行的一个或一个以上引线框架切割所述阵列。
24.根据权利要求22所述的方法,其进一步包含在所述经附接IC封装的每一端子的底侧上形成可焊接镀层。
25.根据权利要求22所述的方法,其进一步包含从所述个别IC封装的端子的侧表面移除氧化物。
26.根据权利要求22所述的方法,其进一步包含以交替方式形成所述个别IC封装与覆盖物的堆叠。
27.根据权利要求26所述的方法,其进一步包含使所述堆叠经受用以从所述经堆叠个别IC封装的端子的侧表面移除氧化物的过程。
28.根据权利要求27所述的方法,其中使所述堆叠经受包含将助溶剂施加到所述堆叠。
29.根据权利要求26所述的方法,其中在所述个别IC封装的端子的侧表面上形成焊料涂层包含使所述堆叠经受焊料浴。
30.一种处理多个IC封装的方法,其包含:
以交替方式形成个别IC封装与覆盖物的堆叠;以及
使所述堆叠经受焊料浴以在所述个别IC封装的端子的侧表面上形成焊料涂层。
CN201010248616.2A 2009-08-06 2010-08-06 形成qfn集成电路封装的可焊接侧表面端子的方法 Active CN102024721B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US23194509P 2009-08-06 2009-08-06
US61/231,945 2009-08-06
US12/688,158 US8709870B2 (en) 2009-08-06 2010-01-15 Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages
US12/688,158 2010-01-15

Publications (2)

Publication Number Publication Date
CN102024721A true CN102024721A (zh) 2011-04-20
CN102024721B CN102024721B (zh) 2015-07-01

Family

ID=43535115

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010248616.2A Active CN102024721B (zh) 2009-08-06 2010-08-06 形成qfn集成电路封装的可焊接侧表面端子的方法

Country Status (3)

Country Link
US (2) US8709870B2 (zh)
CN (1) CN102024721B (zh)
DE (1) DE102010033550B4 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409785A (zh) * 2016-11-30 2017-02-15 天水华天科技股份有限公司 一种薄型阵列塑料封装件及其生产方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070669B2 (en) 2012-11-09 2015-06-30 Freescale Semiconductor, Inc. Wettable lead ends on a flat-pack no-lead microelectronic package
US8535982B1 (en) 2012-11-29 2013-09-17 Freescale Semiconductor, Inc. Providing an automatic optical inspection feature for solder joints on semiconductor packages
US8809119B1 (en) 2013-05-17 2014-08-19 Stats Chippac Ltd. Integrated circuit packaging system with plated leads and method of manufacture thereof
US9048228B2 (en) 2013-09-26 2015-06-02 Stats Chippac Ltd. Integrated circuit packaging system with side solderable leads and method of manufacture thereof
US9472528B2 (en) 2014-06-05 2016-10-18 Freescale Semiconductor, Inc. Integrated electronic package and method of fabrication
US10804185B2 (en) 2015-12-31 2020-10-13 Texas Instruments Incorporated Integrated circuit chip with a vertical connector

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240588A (en) * 1991-08-27 1993-08-31 Nec Corporation Method for electroplating the lead pins of a semiconductor device pin grid array package
US6116497A (en) * 1995-05-24 2000-09-12 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Process and device for the wave or vapor-phase soldering of electronic units
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant
CN101110369A (zh) * 2006-07-20 2008-01-23 矽品精密工业股份有限公司 半导体封装件及其制法
CN101261964A (zh) * 2007-03-06 2008-09-10 日立金属株式会社 功能元件封装

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2756485A (en) * 1950-08-28 1956-07-31 Abramson Moe Process of assembling electrical circuits
BE562490A (zh) * 1956-03-05 1900-01-01
US3020175A (en) * 1958-06-12 1962-02-06 Gen Dynamics Corp Chemical cleaning of printed circuits
DE1894359U (de) * 1963-09-30 1964-06-11 Siemens Ag Geraeteeinheit mit mehreren, bauelemente tragenden schalteinheiten.
US4139726A (en) * 1978-01-16 1979-02-13 Allen-Bradley Company Packaged microcircuit and method for assembly thereof
US4708281A (en) * 1982-02-16 1987-11-24 Rca Corporation Apparatus and method for applying solder flux to a printed circuit board
US4795694A (en) * 1986-06-20 1989-01-03 Siemens Aktiengesellschaft Manufacture of fine structures for semiconductor contacting
US4801065A (en) * 1987-09-30 1989-01-31 Harris Corporation Chip carrier soldering pallet
JPH0680605B2 (ja) * 1987-11-28 1994-10-12 株式会社村田製作所 電子部品チップ保持治具および電子部品チップのメタライズ面への金属コーティング方法
JPH02277753A (ja) * 1989-04-20 1990-11-14 Senju Metal Ind Co Ltd はんだメッキ方法およびその装置
JP2821229B2 (ja) * 1990-03-30 1998-11-05 株式会社日立製作所 電子回路装置
US5240169A (en) * 1991-12-06 1993-08-31 Electrovert Ltd. Gas shrouded wave soldering with gas knife
US5855323A (en) * 1996-11-13 1999-01-05 Sandia Corporation Method and apparatus for jetting, manufacturing and attaching uniform solder balls
KR100574215B1 (ko) * 1997-04-17 2006-04-27 세키스이가가쿠 고교가부시키가이샤 도전성 미립자
US6281573B1 (en) * 1998-03-31 2001-08-28 International Business Machines Corporation Thermal enhancement approach using solder compositions in the liquid state
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6143981A (en) * 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6271060B1 (en) * 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device
US6409878B1 (en) * 2000-04-18 2002-06-25 Advanced Micro Devices, Inc. Automatic decapsulation system utilizing an acid resistant, high heat endurance and flexible sheet coupled to a rubber gasket and a method of use
JP3664045B2 (ja) * 2000-06-01 2005-06-22 セイコーエプソン株式会社 半導体装置の製造方法
US6395129B1 (en) * 2000-11-27 2002-05-28 Advanced Micro Devices, Inc. Process to decapsulate a FBGA package
JP4034073B2 (ja) * 2001-05-11 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
US6583500B1 (en) * 2002-02-11 2003-06-24 Texas Instruments Incorporated Thin tin preplated semiconductor leadframes
JP2003243807A (ja) * 2002-02-14 2003-08-29 Nec Kansai Ltd 配線基板及びその製造方法
JP4416373B2 (ja) * 2002-03-08 2010-02-17 株式会社日立製作所 電子機器
TW200418149A (en) * 2003-03-11 2004-09-16 Siliconware Precision Industries Co Ltd Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same
US6823585B2 (en) * 2003-03-28 2004-11-30 International Business Machines Corporation Method of selective plating on a substrate
US7101792B2 (en) * 2003-10-09 2006-09-05 Micron Technology, Inc. Methods of plating via interconnects
JP4619223B2 (ja) * 2004-12-16 2011-01-26 新光電気工業株式会社 半導体パッケージ及びその製造方法
US7625780B2 (en) * 2005-03-15 2009-12-01 Regents Of The University Of Minnesota Fluidic heterogeneous microsystems assembly and packaging
US20080285251A1 (en) * 2005-04-07 2008-11-20 Jiangsu Changiang Electronics Technology Co., Ltd. Packaging Substrate with Flat Bumps for Electronic Devices and Method of Manufacturing the Same
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
WO2009028463A1 (ja) * 2007-08-24 2009-03-05 Nec Corporation スペーサ及びその製造方法
US7932587B2 (en) 2007-09-07 2011-04-26 Infineon Technologies Ag Singulated semiconductor package
US7851897B1 (en) * 2008-06-16 2010-12-14 Maxim Integrated Products, Inc. IC package structures for high power dissipation and low RDSon
US20100081237A1 (en) * 2008-09-30 2010-04-01 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device
KR101208028B1 (ko) * 2009-06-22 2012-12-04 한국전자통신연구원 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지
CN101587933B (zh) * 2009-07-07 2010-12-08 苏州晶方半导体科技股份有限公司 发光二极管的晶圆级封装结构及其制造方法
TWI492392B (zh) * 2010-08-27 2015-07-11 Ind Tech Res Inst 半導體元件模組封裝結構及其串接方式
US8076181B1 (en) * 2010-10-22 2011-12-13 Linear Technology Corporation Lead plating technique for singulated IC packages

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5240588A (en) * 1991-08-27 1993-08-31 Nec Corporation Method for electroplating the lead pins of a semiconductor device pin grid array package
US6116497A (en) * 1995-05-24 2000-09-12 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Process and device for the wave or vapor-phase soldering of electronic units
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant
CN101110369A (zh) * 2006-07-20 2008-01-23 矽品精密工业股份有限公司 半导体封装件及其制法
CN101261964A (zh) * 2007-03-06 2008-09-10 日立金属株式会社 功能元件封装

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409785A (zh) * 2016-11-30 2017-02-15 天水华天科技股份有限公司 一种薄型阵列塑料封装件及其生产方法

Also Published As

Publication number Publication date
CN102024721B (zh) 2015-07-01
DE102010033550A1 (de) 2011-05-05
DE102010033550B4 (de) 2019-05-16
US20110033977A1 (en) 2011-02-10
US9159586B1 (en) 2015-10-13
US8709870B2 (en) 2014-04-29

Similar Documents

Publication Publication Date Title
CN102024721B (zh) 形成qfn集成电路封装的可焊接侧表面端子的方法
US8809121B2 (en) Singulation of IC packages
CN105405823A (zh) 具有可检查的焊接点的半导体装置
KR20050016130A (ko) 반도체 장치 및 그 제조 방법
TW201626473A (zh) 具有改良接觸引腳之平坦無引腳封裝
CN113035722A (zh) 具有选择性模制的用于镀覆的封装工艺
CN102468194A (zh) 半导体器件封装方法及半导体器件封装
KR101673649B1 (ko) 반도체 디바이스 및 그 제조 방법
KR101197189B1 (ko) 반도체 패키지 및 그 제조방법
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
US20130049180A1 (en) Qfn device and lead frame therefor
EP3319122B1 (en) Semiconductor device with wettable corner leads
KR100871379B1 (ko) 반도체 패키지의 제조방법
CN102738022A (zh) 组装包括绝缘衬底和热沉的半导体器件的方法
KR20090123684A (ko) 플립 칩 패키지의 제조 방법
US7220619B2 (en) Process of cutting electronic package
US11233003B2 (en) Surface mount semiconductor device with a plurality of lead frames
US11227820B2 (en) Through hole side wettable flank
JP2013074108A (ja) 半導体パッケージの製造方法
KR101905244B1 (ko) 반도체 디바이스 및 그 제조 방법
US20150097278A1 (en) Surface mount semiconductor device with additional bottom face contacts
US20140357023A1 (en) Semiconductor device package with cap element
JP5149694B2 (ja) 半導体装置及びその製造方法
JP6418530B2 (ja) 半導体装置の製造方法及び製造用治具
WO2014178652A1 (ko) 기판 프레임 제조 방법 및 이를 포함하는 반도체 소자 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: American California

Applicant after: Maxim Integrated Products Inc.

Address before: American California

Applicant before: Maxim Integrated Products

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: MAXIM INTEGRATED PRODUCTS, INC. TO: MAXIM INTEGRATED PRODUCTS INC.

C14 Grant of patent or utility model
GR01 Patent grant