CN101903992B - 用于平面独立栅或环栅晶体管的改进的制造方法 - Google Patents
用于平面独立栅或环栅晶体管的改进的制造方法 Download PDFInfo
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- CN101903992B CN101903992B CN2008801218961A CN200880121896A CN101903992B CN 101903992 B CN101903992 B CN 101903992B CN 2008801218961 A CN2008801218961 A CN 2008801218961A CN 200880121896 A CN200880121896 A CN 200880121896A CN 101903992 B CN101903992 B CN 101903992B
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- 238000004519 manufacturing process Methods 0.000 title description 13
- 238000000034 method Methods 0.000 claims abstract description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 19
- 238000003475 lamination Methods 0.000 claims description 19
- 238000005516 engineering process Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 7
- 230000008439 repair process Effects 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract 1
- 238000007781 pre-processing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 153
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 238000012545 processing Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000003550 marker Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP07291587.9 | 2007-12-21 | ||
EP07291587 | 2007-12-21 | ||
PCT/IB2008/055418 WO2009081345A1 (fr) | 2007-12-21 | 2008-12-18 | Procédé de fabrication amélioré pour des transistors à grille indépendante ou à grille enveloppante |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101903992A CN101903992A (zh) | 2010-12-01 |
CN101903992B true CN101903992B (zh) | 2012-06-27 |
Family
ID=40427392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2008801218961A Expired - Fee Related CN101903992B (zh) | 2007-12-21 | 2008-12-18 | 用于平面独立栅或环栅晶体管的改进的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7923315B2 (fr) |
EP (1) | EP2235745A1 (fr) |
CN (1) | CN101903992B (fr) |
WO (1) | WO2009081345A1 (fr) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2995720B1 (fr) * | 2012-09-18 | 2014-10-24 | Commissariat Energie Atomique | Procede de realisation d'un dispositif a effet de champ a double grille a grilles independantes |
US9136343B2 (en) * | 2013-01-24 | 2015-09-15 | Intel Corporation | Deep gate-all-around semiconductor device having germanium or group III-V active layer |
US9391163B2 (en) | 2014-10-03 | 2016-07-12 | International Business Machines Corporation | Stacked planar double-gate lamellar field-effect transistor |
US9281379B1 (en) | 2014-11-19 | 2016-03-08 | International Business Machines Corporation | Gate-all-around fin device |
US9496338B2 (en) * | 2015-03-17 | 2016-11-15 | International Business Machines Corporation | Wire-last gate-all-around nanowire FET |
KR102476143B1 (ko) * | 2016-02-26 | 2022-12-12 | 삼성전자주식회사 | 반도체 장치 |
US10008497B2 (en) * | 2016-11-29 | 2018-06-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device and a semiconductor device |
CN106847822B (zh) * | 2017-03-08 | 2018-11-16 | 长江存储科技有限责任公司 | 3d nand存储器件、制造方法以及台阶校准方法 |
KR102400558B1 (ko) * | 2017-04-05 | 2022-05-20 | 삼성전자주식회사 | 반도체 소자 |
US10170304B1 (en) | 2017-10-25 | 2019-01-01 | Globalfoundries Inc. | Self-aligned nanotube structures |
EP3731281A1 (fr) * | 2019-04-24 | 2020-10-28 | Nxp B.V. | Dispositif semiconducteur latéral doté d'une source surélevée et d'un drain et procédé de fabrication correspondant |
US11362096B2 (en) | 2019-12-27 | 2022-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device structure and method for forming the same |
DE102020110792B4 (de) * | 2019-12-27 | 2022-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtungsstruktur mit Finnenstruktur und mehreren Nanostrukturen und Verfahren zum Bilden derselben |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3460863B2 (ja) * | 1993-09-17 | 2003-10-27 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH118390A (ja) * | 1997-06-18 | 1999-01-12 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
FR2845201B1 (fr) * | 2002-09-27 | 2005-08-05 | St Microelectronics Sa | Procede de formation de portions d'un materiau compose a l'interieur d'une cavite et circuit electrique incorporant des portions de materiau compose ainsi obtenues |
KR100481209B1 (ko) * | 2002-10-01 | 2005-04-08 | 삼성전자주식회사 | 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법 |
FR2853454B1 (fr) * | 2003-04-03 | 2005-07-15 | St Microelectronics Sa | Transistor mos haute densite |
KR100550343B1 (ko) * | 2003-11-21 | 2006-02-08 | 삼성전자주식회사 | 다중 채널 모오스 트랜지스터를 포함하는 반도체 장치의제조 방법 |
KR100625177B1 (ko) * | 2004-05-25 | 2006-09-20 | 삼성전자주식회사 | 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법 |
KR100618831B1 (ko) * | 2004-06-08 | 2006-09-08 | 삼성전자주식회사 | 게이트 올 어라운드형 반도체소자 및 그 제조방법 |
FR2897201B1 (fr) * | 2006-02-03 | 2008-04-25 | Stmicroelectronics Crolles Sas | Dispositif de transistor a doubles grilles planaires et procede de fabrication. |
FR2928029B1 (fr) * | 2008-02-27 | 2011-04-08 | St Microelectronics Crolles 2 | Procede de fabrication d'un dispositif semi-conducteur a grille enterree et circuit integre correspondant. |
-
2008
- 2008-12-18 EP EP08865008A patent/EP2235745A1/fr not_active Withdrawn
- 2008-12-18 US US12/809,876 patent/US7923315B2/en active Active
- 2008-12-18 CN CN2008801218961A patent/CN101903992B/zh not_active Expired - Fee Related
- 2008-12-18 WO PCT/IB2008/055418 patent/WO2009081345A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
CN101903992A (zh) | 2010-12-01 |
US7923315B2 (en) | 2011-04-12 |
WO2009081345A1 (fr) | 2009-07-02 |
US20110014769A1 (en) | 2011-01-20 |
EP2235745A1 (fr) | 2010-10-06 |
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