CN101882625A - 使用晶片级封装的光传感器 - Google Patents

使用晶片级封装的光传感器 Download PDF

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CN101882625A
CN101882625A CN2010100004362A CN201010000436A CN101882625A CN 101882625 A CN101882625 A CN 101882625A CN 2010100004362 A CN2010100004362 A CN 2010100004362A CN 201010000436 A CN201010000436 A CN 201010000436A CN 101882625 A CN101882625 A CN 101882625A
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wafer
path
silicon
optical sensor
silicon wafer
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A·V·萨莫伊洛
A·伯格蒙特
C-C·卢
P·霍尔纳斯珀
J·P·龙
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Abstract

本发明提供用于制造微型低功率光传感器的系统、器件和方法。使用本发明，例如二极管的光敏部件是制造在硅晶片的前侧上的。从晶片前侧到晶片后侧的连接性是由穿硅通路提供的。焊料凸起置于晶片后侧，以提供到印刷电路板的耦合。在本发明中描述的技术还可应用于其他类型的半导体器件，例如发光二极管、图像传感器、压力传感器和流量传感器。

Description

使用晶片级封装的光传感器
技术领域
本发明总地涉及半导体光传感器，并且更具体地，涉及使用各种半导体制造技术和晶片级封装技术来制造微型低功率光传感器。
背景技术
光传感器在现代社会中无所不在。一些应用使用具有光学检测的反射光来进行位置感测；这些应用包括条码读取器、激光打印机和自动对焦显微镜。其他应用(例如数码相机、蜂窝电话和膝上型计算机)使用光学传感器来量测环境光的量，并且通过将屏幕光强度调整为环境光量的函数来使设备功耗最小化。此外，环境光传感器集成在膝上型计算机中来将屏幕背光调整为观看者舒服的水平。光传感器还可以被用在工业应用中。
通常通过在半导体晶片前侧上制造光敏元件(例如二极管)来实现光传感器。为了提供电或光学接入(access)，传统的途径是使用导线结合到晶片前侧。然而，该途径需要大量半导体空间(real estate)和扇出电阻(fan out resistance)，导致高成本和高功耗的方案。
最近以来，用于光传感器的晶片级封装(“WLP”)已经提供了优于常规途径的更小尺寸、更高性能和一些成本降低。同样，已经作出努力来利用穿硅通路(“TSV”)、通路钝化层沉积、盘氧化层开口(pad oxide opening)、通路填充、再分布层(“RDL”)、焊料凸起成形和切片，以便于减小尺寸并提高性能。用于制造TSV的蚀刻工艺已经包括湿法蚀刻、RIE(反应离子蚀刻)和DRIE(深反应离子蚀刻)。这些努力已经提供了一些改进，但是半导体技术仍旧受到成本和功率效率的挑战。所需要的是这样的光传感器方案，所述光传感器在尺寸、成本、功耗以及可靠性方面提供显著的改进。
发明内容
本发明提供与微型低功率光传感器相关的系统、器件和方法。使用本发明，光敏部件(例如二极管)是制造在硅晶片的前侧上。从晶片前侧到晶片后侧的连接性是由TSV提供的。焊料凸起置于晶片后侧，以提供到印刷电路板(“PCB”)的耦合。该技术通过消除芯片之外连接的扇出来提供传感器微型化，并且实现优选的芯片尺寸封装。另外，对具有特定尺寸的焊料凸起的选择可以消除对底填充(例如填充传感器芯片和PCB之间的空间)的需求，并且可以导致成本有效并可靠的方案。
本发明可以以各种不同的制造工艺和技术实现。例如，TSV可以以包括DRIE先通路(via first)、DRIE后通路(via last)、后通路湿法蚀刻和两步通路结构的实施方案制造。为了进一步便利WLP，晶片的前侧可以用保护衬底或保护带来保护。
在本发明中描述的技术还可以应用于其他类型的半导体器件，例如发光二极管、图像传感器、压力传感器和流量传感器。
已经在该发明内容章节总地描述了本发明的某些特征和优点；然而，在本文中给出了另外的特征、优点和实施方案，或者查看了这里的附图、说明书和权利要求书的本领域普通技术人员将清楚另外的特征、优点和实施方案。因此，应该理解，本发明的范围应当不受该发明内容章节中所公开的特定实施方案的限制。
附图说明
现在将参照本发明的实施方案，本发明的实施例可以在附图中被图示。这些附图意图是图示说明性的而非限制性的。尽管本发明是在这些实施方案的上下文中进行描述的，但是应该理解，并非意图将本发明的范围限于这些特定实施方案。
图1根据本发明的各个实施方案图示半导体光传感器的先通路DRIE实现的横截面。
图2根据本发明的各个实施方案图示半导体光传感器的先通路DRIE实现的制造方法。
图3根据本发明的各个实施方案图示半导体光传感器的后通路DRIE实现的横截面。
图4根据本发明的各个实施方案图示半导体光传感器的后通路DRIE和后通路湿法蚀刻实现的制造方法。
图5根据本发明的各个实施方案图示半导体光传感器的后通路湿法蚀刻实现的横截面。
图6根据本发明的各个实施方案图示半导体光传感器的两步穿硅通路实现的横截面。
图7根据本发明的各个实施方案图示半导体光传感器的两步穿硅通路实现的制造方法。
具体实施方式
本发明的实施方案提供与微型低功率光传感器相关的系统、器件和方法。本发明以互补金属氧化物半导体(CMOS)光电二极管传感器的高效集成、针对电连接性而使用TSV以及对具有某些特性的焊料凸起的选择实现成本和可靠性益处。对于电连接性，本发明采用将管芯(die)前侧的光敏光电二极管和其他器件连接到后侧的TSV。在管芯的后侧，设置有焊料凸起来便利与印刷电路板或其他器件的连接。使用为晶片凸起(wafer bumping)而特别定尺寸的焊料凸起消除了对底填充(例如填充芯片和PCB之间的空间)的需要，并且导致成本有效且可靠的方案。另外，为了确保对传感器的光学接入，本发明采用可以置于光敏元件之上的光学滤波器来选择需要的电磁谱部分(例如可见光)，以便于模拟人眼对环境光的感知。
本发明可以实现在各种半导体实施方案中。一般的蚀刻工艺包括湿法蚀刻、反应离子蚀刻(RIE)和深反应离子蚀刻(DRIE)。湿法蚀刻是以液体蚀刻剂进行的化学工艺，并且强烈地依赖于晶片暴露的晶面。RIE是在微制造中使用的蚀刻技术。它使用化学反应性的等离子体来移除沉积在晶片上的物质。等离子体是在低压(真空)下通过电磁场产生的。来自于等离子体的高能离子冲击晶片并且与其进行反应。DRIE是用于在晶片中创建深的陡边孔洞和沟道的高度各向异性蚀刻工艺，其中典型的纵横比为5∶1或更大。
第一实施方案100在图1中示出，并且被称为先通路DRIE方法，因为通路是制造在硅晶片112的前(第一)侧的。实施方案100包括CMOS二极管111、CMOS介电质110，以及CMOS金属102。在CMOS元件之上的层是光学滤波器114，具有如之前描述的性质。DRIE通路105包括通路金属104，所述通路金属104通过通路介电质103与硅晶片隔离。为了便利后(第二)侧上的处理，保护衬底109通过粘黏层101附着到前侧。在某些实施方案中，通路金属104是电镀的金属，其需要通路金属阻挡/晶种层115。在其他实施方案中，通路金属104和通路金属阻挡/晶种层115被物理气相沉积(PVD)金属层替代。
晶片的后侧包括隔离层Iso.1 107，该隔离层提供晶片和后续沉积的RDL层106之间的绝缘。在RDL层106和晶片112之上是另一隔离层Iso.2 108，并且焊料凸起113被这样设置，即使得其耦合到RDL层106。在某些实施方案中，RDL 106是电镀的金属，其需要RDL阻挡/晶种层116。在其他实施方案中，RDL 106和RDL阻挡/晶种层116被PVD金属层替代。
在某些实施方案中，凸起113的直径大致为150至350微米。当晶片级封装工艺使用该尺寸范围内的凸起时，可以有两种积极结果。首先，可以消除或者减少现有技术对晶片112和印刷电路板之间底填充的要求。排除底填充要求可以导致工艺复杂性和成本的显著降低。第二，焊料凸起与印刷电路板的连接可以是非常可靠的。因此，利用具有本发明的部件的终端用户产品(例如蜂窝电话)可以是非常可靠的，并且因此可以容易地通过要求的温度循环测试、振动测试和坠落测试。
如图1中图示的，二极管111耦合到CMOS金属102，该CMOS金属102耦合到通路金属104，通路金属104耦合到RDL层106，RDL层106耦合到焊料凸起113。通常，焊料凸起113耦合到金属电路板。因此，使用TSV可以提供从二极管111至印刷电路板的空间高效连接性。
图2中图示出用于制造具有DRIE先通路TSV的光传感器的方法200。该工艺以CMOS工艺202开始，其中CMOS元件被制造在晶片的前侧，所述CMOS元件例如二极管111、CMOS介电质110和CMOS金属102。随后，通过用DRIE蚀刻在硅晶片前侧进行图形化(pattern)以产生DRIE通路105来形成TSV，如步骤203中注明的。TSV以步骤204到208中通路介电质103的沉积以及图形化镀覆通路金属104而完成。通路金属104允许从前侧CMOS金属层102到晶片后侧的传导性。在下一步骤209，光学滤波器层沉积在晶片前侧上。在下一步骤210，保护衬底109借由粘黏剂101附着，其中粘黏剂101的图形化是可选的。
在保护衬底结合210之后，由保护衬底109和硅晶片112构成的晶片堆叠(wafer stack)通过两步薄化工艺211从硅晶片后侧被薄化下去。第一步骤是利用附着到保护衬底109顶部的常规背磨胶带(back grind tape)来进行的粗研磨。第二步骤是用于使通路底部暴露而不损伤TSV的电气和机械完整性的精细抛光或蚀刻。
可光成像的介电隔离层Iso.1 107沉积和通路开口的程序(sequence)通过光刻图形化和通路介电蚀刻在晶片后(第二)侧上进行。经由工艺步骤212，介电隔离层Iso.1107在晶片堆叠后侧上被涂覆、图形化和固化。经由工艺步骤212，Iso.107的图形还充当通路开口RIE蚀刻期间的蚀刻掩模。厚的Iso.107提供RDL 106和硅晶片112之间的电气隔离，并且还提供用来耐受通过焊料凸起传递的应力的机械强度。
经由工艺步骤213-215，RDL层106镀覆在RDL阻挡/晶种116上，并且以厚的光致抗蚀剂模被图形化。在移除光致抗蚀剂模和过量的RDL阻挡/晶种116之后(经由工艺步骤216)，经由工艺步骤217，介电隔离层Iso.2 108在晶片堆叠的后侧被镀覆、图形化和固化。接下来，焊料凸起113沉积到RDL 106。本领域技术人员清楚多种凸起工艺和技术。在该实施方案中移除保护衬底109是可选的，取决于是将晶片单个化(singulate)为管芯还是将晶片和保护衬底单个化为管芯。参照工艺步骤219、220和221。
将保护载体结合到晶片的操作便利了晶片的薄化工艺，并且使得TSV蚀刻工艺更容易。晶片通常被薄化到50至300微米。然而，当该技术与现有技术的前侧晶片结合方法一起使用时，由于与晶片结合和在制造结束时移除结合的晶片以便于出于光感测目的而使传感器初始前表面暴露相关联的步骤，招致额外的成本。
第二实施方案300在图3中示出，并且被称为后通路DRIE方法，因为通路是在晶片的后(第二)侧上制造的。如图3中图示的，DRIE通路305提供从硅晶片112前侧至后侧的连接性。注意，DRIE通路305结构相对于图1中图示的DRIE通路105来说是相反的。然而，实施方案300具有很多与实施方案100相同的结构元件，并且这些元件为光传感器提供与之前的实施方案相同的功能性。经由图1和图3，这些元件包括101-104、106-114、116。
制造具有DRIE后通路TSV的光传感器的方法400在图4中图示出。该工艺以CMOS工艺202开始，其中CMOS元件制造在晶片的前侧，所述CMOS元件例如二极管111、CMOS介电质110和CMOS金属102。在下一步骤204，在结合到保护衬底109之前，在晶片前侧上沉积光学滤波器层。经由图4中的步骤205，保护层109通过粘黏剂101附着。
在保护衬底结合之后，由保护衬底和硅晶片构成的晶片堆叠从硅晶片后侧被薄化下去。该方法406包括以可选的抛光或蚀刻利用附着到保护衬底顶部的常规背磨胶带来进行研磨，以更好地控制堆叠厚度和表面状况。
为了制造实施方案300，在步骤416选择DRIE蚀刻。经由步骤414，在硅晶片后侧上在DRIE中图形化和蚀刻TSV。经由步骤407的通路介电质303沉积和通路开口的程序经由步骤408以光致抗蚀剂图形化和通路介电质RIE蚀刻来进行。特殊的光致抗蚀剂覆层是可选的，以提高在整个倾斜的通路侧壁上的一致性。接下来，经由步骤409，Iso.1307在硅晶片112后侧上被涂覆、图形化和固化。随后，RDL 306被施加以RDL阻挡/晶种304。在某些实施方案中，RDL 306是电镀的金属，其需要RDL阻挡/晶种层304。在其他实施方案中，RDL 306和RDL阻挡/晶种层304被PVD金属层替代。
经由步骤410-413，RDL 306通过DRIE通路305将前侧CMOS金属层102耦合到晶片后侧。在移除光致抗蚀剂模和过量RDL阻挡/晶种层之后，介电隔离层Iso.2308在晶片堆叠的后侧被镀覆、图形化和固化。如对于方法200来说的，对硅晶片进行焊料凸起操作，以便利与印刷电路板或其他器件的耦合。类似于第一实施方案100，在经由步骤219、220和221对晶片进行单一化之前，选择移除或者不移除保护衬底109。
第三实施方案500在图5中示出，并且被称为后通路湿法蚀刻方法。如对于实施方案300来说的，通路制造在晶片后侧上。然而，取代于使用DRIE蚀刻工艺，实施方案500使用湿法蚀刻工艺。如图5中图示的，湿法蚀刻通路505以与如图3中图示的DRIE通路305等同的方式提供从硅晶片112前侧至后侧的连接性。另外，实施方案500具有很多与实施方案100和300相同的结构元件，并且这些元件为光传感器提供与其他实施方案相同的功能性。这些实施方案包括图1的101、102、109-104和图3的303、304、306-308。
用于制造实施方案500的方法通过方法400在图4中图示出。这与用于制造实施方案300的方法相同，除了通路是经由步骤415通过湿法蚀刻工艺来形成的。在该步骤中，TSV在湿法蚀刻容器中被图形化和蚀刻于硅晶片后侧上。
第四实施方案600在图6中示出，并且被称为双侧通路或两步通路方法，其中存在两个TSV；一个TSV是从前侧制造的，而另一个TSV是从硅晶片112的后侧制造的。如图6中图示的，DRIE通路部分614位于硅晶片112的前侧，而伴体(companion)DRIE通路部分605位于硅晶片112的后侧。DRIE通路部分605和614耦合在一起，其中它们各自的通路金属层处于硅晶片12的中间部分。另外，如图6中注明的，实施方案600具有与实施方案100、300和500相同的结构元件，并且这些元件为光传感器提供与其他实施方案相同的功能性。这些实施方案包括图1的101、102、109-104和图3的306-308。
用于制造具有双侧通路的光传感器的方法700在图7中图示出。该工艺以CMOS工艺202开始，其中CMOS元件沉积在晶片前侧上，所述CMOS元件例如二极管111、CMOS介电质110和CMOS金属102。随后，如在步骤703-708中注明的，通过用DRIE蚀刻在硅晶片前侧上进行图形化和蚀刻而产生DRIE通路部分614来形成TSV。TSV的第一部分以通路介电质603的沉积以及镀覆通路金属604完成。在下一步骤204，光学滤波器层沉积在晶片前侧上。随后，经由步骤205，保护衬底109借由粘黏剂101附着。在结合保护衬底109之后，经由步骤406，由保护衬底109和硅晶片112构成的晶片堆叠从硅晶片后侧被薄化下去。以可选的抛光或蚀刻利用附着到保护衬底顶部的常规背磨胶带来进行研磨，以更好地控制堆叠厚度和表面状况。
经由步骤709-710，TSV的第二部分被图形化和DRIE蚀刻605在硅晶片的后侧上。如步骤709中注明的，通过在硅晶片后侧上进行图形化以及用DRIE蚀刻进行蚀刻以产生DRIE通路而形成DRIE通路605。以光致抗蚀剂图形化和通路介电质RIE蚀刻进行通路介电质沉积617和通路开口的程序。在涂覆、图形化和固化介电隔离层Iso.1 307之后，经由步骤713-715，RDL被镀覆，以将通路金属层604耦合到晶片后侧。在某些实施方案中，RDL 306是需要RDL阻挡/晶种层616的电镀金属。在其他实施方案中，RDL 306和RDL阻挡/晶种层616被PVD金属层替代。在移除光致抗蚀剂模和过量RDL阻挡/晶种层之后，介电隔离层Iso.2 308在晶片堆叠的后侧被镀覆、图形化和固化。如对于方法200和400来说的，对硅晶片112进行凸起操作，以便利与印刷电路板或其他器件的耦合。如在步骤219、220和221中注明的，在该实施方案中移除保护衬底是可选的。
在前述实施方案中，保护衬底109以粘黏层101附着。特殊加压的晶片保持器或前侧保护衬底是可选的，以在蚀刻期间保护电路。本领域技术人员很清楚晶片保持器和保护层。可替换的方法包括将保护带附着到晶片前侧以保护前侧器件。对于该方法，发生相对小量的硅研磨。剩余硅晶片的量在大致400微米直至典型730微米的全初始晶片厚度的范围内。
其他实施方案可以包括在除硅晶片外的物质(例如锗晶片)上制造光传感器。这对于本领域技术人员来说将是显而易见的，即用于焊料凸起和“穿硅通路”的类似技术可以应用于其他实施方案。另外，光敏部件可以是除硅二极管之外的结构。
用于本发明的可替换应用可以包括发光二极管、流量传感器、压力传感器和图像传感器应用。相对于流量和压力传感器，将在半导体晶片上集成能够检测正被按压的状况的机制；例如均匀施加于表面之上的力，以每单元面积的力来度量。
已经出于清楚和理解的目的描述了对本发明的前述描述。并非意图将本发明限制为所公开的精确形式。在所附权利要求书的范围和等同性范围内，各种修改是可能的。

Claims (21)

1.一种集成的光传感器，包括：
具有第一侧和相对的第二侧的半导体晶片；
制造在所述晶片的所述第一侧上的光检测二极管；
定位在所述晶片的所述第二侧上用于将所述晶片连接到印刷电路板的焊料凸起；以及
在所述晶片的所述第一侧和所述第二侧之间的通路，所述通路包括在所述光检测二极管和所述焊料凸起之间导电的金属层。
2.如权利要求1所述的集成的光传感器，其中所述晶片是硅晶片，而所述通路是穿硅通路。
3.如权利要求2所述的集成的光传感器，其中所述穿硅通路是从所述硅晶片的所述第一侧向所述第二侧图形化并深反应离子蚀刻的。
4.如权利要求2所述的集成的光传感器，其中所述穿硅通路是通过从所述硅晶片的所述第二侧向所述第一侧进行深反应离子蚀刻而形成的。
5.如权利要求3所述的集成的光传感器，其中所述穿硅通路是通过从所述硅晶片的所述第二侧向所述第一侧进行湿法蚀刻而形成的。
6.如权利要求3所述的集成的光传感器，其中所述穿硅通路是通过以下步骤制造的两步穿硅通路，所述步骤包括：
使用第一深反应离子蚀刻在所述硅晶片的所述第一侧形成第一通路部分；
使用第二深反应离子蚀刻在所述硅晶片的所述第二侧形成第二通路部分；以及
在所述第一通路部分的第一表面和所述第二通路部分的第二表面上沉积所述通路金属层，所述通路金属层提供所述二极管和所述焊料凸起之间的电连接。
7.如权利要求1所述的集成的光传感器，其中所述硅晶片的所述第一侧通过向所述硅晶片的所述第一侧附着保护衬底或者通过向所述硅晶片的所述第一侧附着保护带而受到保护。
8.如权利要求1所述的集成的光传感器，其中所述硅晶片的所述第一侧具有位于所述二极管之上的光学滤波器层，所述光学层选择性地过滤电磁谱。
9.如权利要求1所述的集成的光传感器，还包括多个二极管，所述多个二极管集成在所述硅晶片上以形成光传感器。
10.一种用于制造集成的光传感器的方法，所述方法包括以下步骤：
在硅晶片的第一侧上制造光检测二极管；
在所述晶片的所述第一侧和第二侧之间形成穿硅通路；
在所述穿硅通路的表面上沉积通路金属层，所述通路金属层提供所述二极管和所述晶片的所述第二侧之间的电连接性；以及
在所述硅晶片的所述第二侧上沉积焊料凸起，所述焊料凸起通过所述通路金属层电耦合到所述二极管。
11.如权利要求10所述的制造光传感器的方法，其中所述穿硅通路是从所述硅晶片的所述第一侧向所述第二侧图形化并深反应离子蚀刻的。
12.如权利要求10所述的制造光传感器的方法，其中所述穿硅通路是通过从所述硅晶片的所述第二侧向所述第一侧进行深反应离子蚀刻而形成的。
13.如权利要求10所述的制造光传感器的方法，其中所述穿硅通路是通过从所述硅晶片的所述第二侧向所述第一侧进行湿法蚀刻而形成的。
14.如权利要求10所述的制造光传感器的方法，其中所述穿硅通路是通过以下步骤制造的两步穿硅通路，所述步骤包括：
使用第一深反应离子蚀刻在所述硅晶片的所述第一侧形成第一通路部分；
使用第二深反应离子蚀刻在所述硅晶片的所述第二侧形成第二通路部分；以及
在所述第一通路部分的第一表面和所述第二通路部分的第二表面上沉积所述通路金属层，所述通路金属层提供所述二极管和所述焊料凸起之间的电连接。
15.如权利要求10所述的制造光传感器的方法，还包括将所述晶片结合到保护衬底或者保护带的步骤。
16.一种集成的半导体器件，包括：
具有第一侧和相对的第二侧的晶片；
制造在所述晶片的所述第一侧上的半导体元件；
定位在所述晶片的所述第二侧上用于将所述晶片连接到板的焊料凸起；以及
在所述晶片的所述第一侧和所述第二侧之间的通路，所述通路包括沉积在所述通路表面上并且在所述半导体元件和所述焊料凸起之间导电的金属层。
17.如权利要求16所述的集成的半导体器件，还包括压力传感器。
18.如权利要求16所述的集成的半导体器件，还包括图像传感器。
19.如权利要求16所述的集成的半导体器件，还包括流量传感器。
20.如权利要求16所述的集成的半导体器件，还包括发光二极管。
21.如权利要求16所述的集成的半导体器件，其中所述焊料凸起具有150-350微米的直径。
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