CN101872756B - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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Publication number
CN101872756B
CN101872756B CN2010101941593A CN201010194159A CN101872756B CN 101872756 B CN101872756 B CN 101872756B CN 2010101941593 A CN2010101941593 A CN 2010101941593A CN 201010194159 A CN201010194159 A CN 201010194159A CN 101872756 B CN101872756 B CN 101872756B
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China
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copper alloy
wiring
barrier metal
alloy wiring
semiconductor device
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Chinese (zh)
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CN101872756A (zh
Inventor
古泽健志
儿玉大介
松本雅弘
宫崎博史
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L15/00—Washing or rinsing machines for crockery or tableware
    • A47L15/42—Details
    • A47L15/4285—Water-heater arrangements
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L15/00—Washing or rinsing machines for crockery or tableware
    • A47L15/0076—Washing or rinsing machines for crockery or tableware of non-domestic use type, e.g. commercial dishwashers for bars, hotels, restaurants, canteens or hospitals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • A—HUMAN NECESSITIES
    • A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
    • A47L—DOMESTIC WASHING OR CLEANING; SUCTION CLEANERS IN GENERAL
    • A47L2501/00—Output in controlling method of washing or rinsing machines for crockery or tableware, i.e. quantities or components controlled, or actions performed by the controlling device executing the controlling method
    • A47L2501/06—Water heaters

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN2010101941593A 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法 Active CN101872756B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006005956A JP5014632B2 (ja) 2006-01-13 2006-01-13 半導体装置および半導体装置の製造方法
JP2006-005956 2006-01-13

Related Parent Applications (1)

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CN2007100022053A Division CN101000905B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法

Publications (2)

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CN101872756A CN101872756A (zh) 2010-10-27
CN101872756B true CN101872756B (zh) 2013-01-02

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CN2010101941593A Active CN101872756B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
CN2011100673949A Active CN102157489B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
CN2007100022053A Active CN101000905B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法

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CN2011100673949A Active CN102157489B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法
CN2007100022053A Active CN101000905B (zh) 2006-01-13 2007-01-12 半导体装置以及半导体装置的制造方法

Country Status (5)

Country Link
US (3) US7700487B2 (https=)
JP (1) JP5014632B2 (https=)
KR (1) KR20070076465A (https=)
CN (3) CN101872756B (https=)
TW (1) TWI440135B (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5014632B2 (ja) * 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
DE102007004867B4 (de) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erhöhen der Zuverlässigkeit von kupferbasierten Metallisierungsstrukturen in einem Mikrostrukturbauelement durch Anwenden von Aluminiumnitrid
US20090001584A1 (en) * 2007-06-26 2009-01-01 Sang-Chul Kim Semiconductor device and method for fabricating the same
JP2010087094A (ja) * 2008-09-30 2010-04-15 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
JP5622433B2 (ja) * 2010-04-28 2014-11-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6300533B2 (ja) * 2014-01-15 2018-03-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US10756208B2 (en) 2014-11-25 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated chip and method of forming the same
US11164970B2 (en) 2014-11-25 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact field plate
US9590053B2 (en) * 2014-11-25 2017-03-07 Taiwan Semiconductor Manufacturing Co., Ltd. Methodology and structure for field plate design
US10411068B2 (en) 2015-11-23 2019-09-10 Intel Corporation Electrical contacts for magnetoresistive random access memory devices
US9799605B2 (en) * 2015-11-25 2017-10-24 International Business Machines Corporation Advanced copper interconnects with hybrid microstructure
US9704804B1 (en) * 2015-12-18 2017-07-11 Texas Instruments Incorporated Oxidation resistant barrier metal process for semiconductor devices
US10923393B2 (en) * 2018-09-24 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors
US11227794B2 (en) * 2019-12-19 2022-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure
US12230552B2 (en) * 2021-11-18 2025-02-18 Qualcomm Incorporated Recess structure for padless stack via
WO2024015181A1 (en) 2022-07-13 2024-01-18 Applied Materials, Inc. Oxidation barriers with cvd soak processes
CN115274594B (zh) * 2022-09-19 2022-12-16 合肥晶合集成电路股份有限公司 一种半导体结构及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1412845A (zh) * 2001-10-19 2003-04-23 日本电气株式会社 半导体器件及其制造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0547760A (ja) * 1991-08-12 1993-02-26 Hitachi Ltd 半導体集積回路装置、その製造方法およびその製造に用いるスパツタターゲツト
JP2701730B2 (ja) * 1994-02-24 1998-01-21 日本電気株式会社 半導体装置およびその製造方法
US6285082B1 (en) * 1995-01-03 2001-09-04 International Business Machines Corporation Soft metal conductor
DE69637333T2 (de) * 1995-06-27 2008-10-02 International Business Machines Corp. Kupferlegierungen für Chipverbindungen und Herstellungsverfahren
JPH11186273A (ja) * 1997-12-19 1999-07-09 Ricoh Co Ltd 半導体装置及びその製造方法
JP3040745B2 (ja) * 1998-01-12 2000-05-15 松下電子工業株式会社 半導体装置及びその製造方法
JP3840650B2 (ja) * 1998-01-21 2006-11-01 株式会社トリケミカル研究所 配線用銅合金膜形成材料および配線用銅合金膜形成方法
JP3149846B2 (ja) * 1998-04-17 2001-03-26 日本電気株式会社 半導体装置及びその製造方法
TW408443B (en) * 1998-06-08 2000-10-11 United Microelectronics Corp The manufacture method of dual damascene
KR100329153B1 (ko) * 1998-07-08 2002-03-21 구마모토 마사히로 단자 및 커넥터용 구리합금 및 그 제조방법
KR100385042B1 (ko) * 1998-12-03 2003-06-18 인터내셔널 비지네스 머신즈 코포레이션 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법
JP2000208517A (ja) * 1999-01-12 2000-07-28 Fujitsu Ltd 半導体装置の製造方法
JP2000349085A (ja) * 1999-06-01 2000-12-15 Nec Corp 半導体装置及び半導体装置の製造方法
CN1425196A (zh) * 1999-11-24 2003-06-18 霍尼韦尔国际公司 导电互连
JP4686008B2 (ja) * 2000-05-31 2011-05-18 株式会社東芝 スパッタリングターゲットとそれを用いたＣｕ膜および電子デバイス
JP2002075995A (ja) 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100385227B1 (ko) * 2001-02-12 2003-05-27 삼성전자주식회사 구리 다층 배선을 가지는 반도체 장치 및 그 형성방법
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
JP2004014626A (ja) * 2002-06-04 2004-01-15 Applied Materials Inc シード膜及びその形成方法、Ｃｕ配線及びその形成方法、半導体装置及びその製造方法、並びに半導体装置の製造装置。
JP4647184B2 (ja) * 2002-12-27 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2004349609A (ja) * 2003-05-26 2004-12-09 Renesas Technology Corp 半導体装置およびその製造方法
JP4527393B2 (ja) * 2003-12-26 2010-08-18 株式会社神戸製鋼所 半導体装置用Ｃｕ系合金配線及びその製造方法
JP4832807B2 (ja) * 2004-06-10 2011-12-07 ルネサスエレクトロニクス株式会社 半導体装置
US8188600B2 (en) * 2004-06-24 2012-05-29 Nec Corporation Semiconductor device and method of fabricating the same
JP2006165115A (ja) * 2004-12-03 2006-06-22 Toshiba Corp 半導体装置
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
JP4589835B2 (ja) * 2005-07-13 2010-12-01 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
JP2007053133A (ja) * 2005-08-15 2007-03-01 Toshiba Corp 半導体装置及びその製造方法
JP5014632B2 (ja) * 2006-01-13 2012-08-29 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1412845A (zh) * 2001-10-19 2003-04-23 日本电气株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
US8097948B2 (en) 2012-01-17
US7816268B2 (en) 2010-10-19
JP5014632B2 (ja) 2012-08-29
US7700487B2 (en) 2010-04-20
CN101000905A (zh) 2007-07-18
CN102157489A (zh) 2011-08-17
TWI440135B (zh) 2014-06-01
CN101000905B (zh) 2011-05-18
CN101872756A (zh) 2010-10-27
US20100151673A1 (en) 2010-06-17
US20070167010A1 (en) 2007-07-19
US20100327449A1 (en) 2010-12-30
JP2007189061A (ja) 2007-07-26
KR20070076465A (ko) 2007-07-24
TW200735275A (en) 2007-09-16
CN102157489B (zh) 2013-02-06

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