CN101814476B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN101814476B
CN101814476B CN201010117406.XA CN201010117406A CN101814476B CN 101814476 B CN101814476 B CN 101814476B CN 201010117406 A CN201010117406 A CN 201010117406A CN 101814476 B CN101814476 B CN 101814476B
Authority
CN
China
Prior art keywords
via hole
metal wiring
buffer layer
stress buffer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010117406.XA
Other languages
English (en)
Chinese (zh)
Other versions
CN101814476A (zh
Inventor
近江俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Publication of CN101814476A publication Critical patent/CN101814476A/zh
Application granted granted Critical
Publication of CN101814476B publication Critical patent/CN101814476B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201010117406.XA 2009-02-19 2010-02-12 半导体装置 Expired - Fee Related CN101814476B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-036590 2009-02-19
JP2009036590A JP5249080B2 (ja) 2009-02-19 2009-02-19 半導体装置

Publications (2)

Publication Number Publication Date
CN101814476A CN101814476A (zh) 2010-08-25
CN101814476B true CN101814476B (zh) 2014-08-27

Family

ID=42559187

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010117406.XA Expired - Fee Related CN101814476B (zh) 2009-02-19 2010-02-12 半导体装置

Country Status (5)

Country Link
US (1) US20100207271A1 (https=)
JP (1) JP5249080B2 (https=)
KR (1) KR20100094943A (https=)
CN (1) CN101814476B (https=)
TW (1) TWI501364B (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102012935B1 (ko) 2012-06-13 2019-08-21 삼성전자주식회사 전기적 연결 구조 및 그의 제조방법
KR20140041975A (ko) 2012-09-25 2014-04-07 삼성전자주식회사 범프 구조체 및 이를 포함하는 전기적 연결 구조체
US8772151B2 (en) 2012-09-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme
KR102122456B1 (ko) 2013-12-20 2020-06-12 삼성전자주식회사 실리콘 관통 비아 플러그들을 갖는 반도체 소자 및 이를 포함하는 반도체 패키지
KR102212559B1 (ko) 2014-08-20 2021-02-08 삼성전자주식회사 반도체 발광소자 및 이를 이용한 반도체 발광소자 패키지
JP6565238B2 (ja) * 2015-03-17 2019-08-28 セイコーエプソン株式会社 液体噴射ヘッド
CN109309057A (zh) * 2017-07-26 2019-02-05 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
DE102018120491A1 (de) * 2018-08-22 2020-02-27 Osram Opto Semiconductors Gmbh Optoelektronisches bauteil und verfahren zur herstellung eines optoelektronischen bauteils
KR102824211B1 (ko) * 2019-12-27 2025-06-26 삼성전자주식회사 반도체 패키지
KR102765303B1 (ko) 2019-12-31 2025-02-07 삼성전자주식회사 반도체 패키지
WO2025115631A1 (ja) * 2023-11-30 2025-06-05 ローム株式会社 半導体素子および半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film

Family Cites Families (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
JPS60117633A (ja) * 1983-11-30 1985-06-25 Toshiba Corp 半導体装置
US5134460A (en) * 1986-08-11 1992-07-28 International Business Machines Corporation Aluminum bump, reworkable bump, and titanium nitride structure for tab bonding
KR910006967B1 (ko) * 1987-11-18 1991-09-14 가시오 게이상기 가부시기가이샤 반도체 장치의 범프 전극 구조 및 그 형성 방법
US5719448A (en) * 1989-03-07 1998-02-17 Seiko Epson Corporation Bonding pad structures for semiconductor integrated circuits
US5027253A (en) * 1990-04-09 1991-06-25 Ibm Corporation Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards
US5136364A (en) * 1991-06-12 1992-08-04 National Semiconductor Corporation Semiconductor die sealing
JPH06204344A (ja) * 1992-12-25 1994-07-22 Hitachi Denshi Ltd 半導体装置の製造方法
JP2596331B2 (ja) * 1993-09-08 1997-04-02 日本電気株式会社 半導体装置およびその製造方法
JP3217624B2 (ja) * 1994-11-12 2001-10-09 東芝マイクロエレクトロニクス株式会社 半導体装置
JP3660799B2 (ja) * 1997-09-08 2005-06-15 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US5943597A (en) * 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
US6077726A (en) * 1998-07-30 2000-06-20 Motorola, Inc. Method and apparatus for stress relief in solder bump formation on a semiconductor device
JP3408172B2 (ja) * 1998-12-10 2003-05-19 三洋電機株式会社 チップサイズパッケージ及びその製造方法
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US6756295B2 (en) * 1998-12-21 2004-06-29 Megic Corporation Chip structure and process for forming the same
US6479900B1 (en) * 1998-12-22 2002-11-12 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6011314A (en) * 1999-02-01 2000-01-04 Hewlett-Packard Company Redistribution layer and under bump material structure for converting periphery conductive pads to an array of solder bumps
KR100411679B1 (ko) * 1999-03-16 2003-12-18 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자기기
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
US6387734B1 (en) * 1999-06-11 2002-05-14 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
US6391780B1 (en) * 1999-08-23 2002-05-21 Taiwan Semiconductor Manufacturing Company Method to prevent copper CMP dishing
JP3387083B2 (ja) * 1999-08-27 2003-03-17 日本電気株式会社 半導体装置及びその製造方法
US6803302B2 (en) * 1999-11-22 2004-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a mechanically robust pad interface
JP2001196413A (ja) * 2000-01-12 2001-07-19 Mitsubishi Electric Corp 半導体装置、該半導体装置の製造方法、ｃｍｐ装置、及びｃｍｐ方法
US6555908B1 (en) * 2000-02-10 2003-04-29 Epic Technologies, Inc. Compliant, solderable input/output bump structures
JP3651765B2 (ja) * 2000-03-27 2005-05-25 株式会社東芝 半導体装置
US6300234B1 (en) * 2000-06-26 2001-10-09 Motorola, Inc. Process for forming an electrical device
US6560862B1 (en) * 2001-02-06 2003-05-13 Taiwan Semiconductor Manufacturing Company Modified pad for copper/low-k
TW594993B (en) * 2001-02-16 2004-06-21 Sanyo Electric Co Semiconductor device and manufacturing process therefor
JP2003031575A (ja) * 2001-07-17 2003-01-31 Nec Corp 半導体装置及びその製造方法
JP2003031576A (ja) * 2001-07-17 2003-01-31 Nec Corp 半導体素子及びその製造方法
US20030116845A1 (en) * 2001-12-21 2003-06-26 Bojkov Christo P. Waferlevel method for direct bumping on copper pads in integrated circuits
US6844631B2 (en) * 2002-03-13 2005-01-18 Freescale Semiconductor, Inc. Semiconductor device having a bond pad and method therefor
JP2003318324A (ja) * 2002-04-26 2003-11-07 Sony Corp 半導体装置
KR20040061970A (ko) * 2002-12-31 2004-07-07 동부전자 주식회사 반도체소자의 패드 형성방법
TWI225899B (en) * 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
US7244671B2 (en) * 2003-07-25 2007-07-17 Unitive International Limited Methods of forming conductive structures including titanium-tungsten base layers and related structures
TWI224377B (en) * 2003-11-14 2004-11-21 Ind Tech Res Inst Wafer level chip scale packaging structure and method of fabrication the same
JP3973624B2 (ja) * 2003-12-24 2007-09-12 富士通株式会社 高周波デバイス
US7176583B2 (en) * 2004-07-21 2007-02-13 International Business Machines Corporation Damascene patterning of barrier layer metal for C4 solder bumps
DE102004047730B4 (de) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen
CN101138084B (zh) * 2004-10-29 2010-06-02 弗利普芯片国际有限公司 具有覆在聚合体层上的隆起的半导体器件封装
US20060128072A1 (en) * 2004-12-13 2006-06-15 Lsi Logic Corporation Method of protecting fuses in an integrated circuit die
JP4777644B2 (ja) * 2004-12-24 2011-09-21 Ｏｋｉセミコンダクタ株式会社 半導体装置およびその製造方法
TWI245345B (en) * 2005-02-17 2005-12-11 Touch Micro System Tech Method of forming a wear-resistant dielectric layer
JP4097660B2 (ja) * 2005-04-06 2008-06-11 シャープ株式会社 半導体装置
US7427565B2 (en) * 2005-06-30 2008-09-23 Intel Corporation Multi-step etch for metal bump formation
JP2007073681A (ja) * 2005-09-06 2007-03-22 Renesas Technology Corp 半導体装置およびその製造方法
US7566650B2 (en) * 2005-09-23 2009-07-28 Stats Chippac Ltd. Integrated circuit solder bumping system
US7518211B2 (en) * 2005-11-11 2009-04-14 United Microelectronics Corp. Chip and package structure
US7947978B2 (en) * 2005-12-05 2011-05-24 Megica Corporation Semiconductor chip with bond area
JP4998270B2 (ja) * 2005-12-27 2012-08-15 富士通セミコンダクター株式会社 半導体装置とその製造方法
KR100703559B1 (ko) * 2005-12-28 2007-04-03 동부일렉트로닉스 주식회사 듀얼다마신 구조를 가지는 반도체 소자 및 그 제조방법
KR100870820B1 (ko) * 2005-12-29 2008-11-27 매그나칩 반도체 유한회사 이미지 센서 및 그의 제조방법
JP2006165595A (ja) * 2006-02-03 2006-06-22 Seiko Epson Corp 半導体装置及びその製造方法
JP2007220647A (ja) * 2006-02-14 2007-08-30 Samsung Sdi Co Ltd 有機電界発光表示装置及びその製造方法
JP4247690B2 (ja) * 2006-06-15 2009-04-02 ソニー株式会社 電子部品及その製造方法
DE102006040115A1 (de) * 2006-08-26 2008-03-20 X-Fab Semiconductor Foundries Ag Verfahren und Anordnung zur hermetisch dichten vertikalen elektrischen Durchkontaktierung von Deckscheiben der Mikrosystemtechnik
US7915737B2 (en) * 2006-12-15 2011-03-29 Sanyo Electric Co., Ltd. Packing board for electronic device, packing board manufacturing method, semiconductor module, semiconductor module manufacturing method, and mobile device
CN100590859C (zh) * 2007-01-16 2010-02-17 百慕达南茂科技股份有限公司 具有环状支撑物的凸块结构及其制造方法
TW200836275A (en) * 2007-02-16 2008-09-01 Chipmos Technologies Inc Packaging conductive structure and method for manufacturing the same
JP4668938B2 (ja) * 2007-03-20 2011-04-13 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7645701B2 (en) * 2007-05-21 2010-01-12 International Business Machines Corporation Silicon-on-insulator structures for through via in silicon carriers
TWM328763U (en) * 2007-05-21 2008-03-11 Univ Nat Taiwan Structure of heat dissipation substrate
US20080308935A1 (en) * 2007-06-18 2008-12-18 Samsung Electronics Co., Ltd. Semiconductor chip package, semiconductor package including semiconductor chip package, and method of fabricating semiconductor package
JP4585557B2 (ja) * 2007-08-13 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR100896883B1 (ko) * 2007-08-16 2009-05-14 주식회사 동부하이텍 반도체칩, 이의 제조방법 및 이를 가지는 적층 패키지
US7935408B2 (en) * 2007-10-26 2011-05-03 International Business Machines Corporation Substrate anchor structure and method
JP5656341B2 (ja) * 2007-10-29 2015-01-21 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置およびその製造方法
JP5512082B2 (ja) * 2007-12-17 2014-06-04 株式会社東芝 半導体装置の製造方法及び半導体装置
KR100929464B1 (ko) * 2007-12-21 2009-12-02 주식회사 동부하이텍 반도체칩, 이의 제조 방법 및 반도체칩 적층 패키지
US7985671B2 (en) * 2008-12-29 2011-07-26 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6451681B1 (en) * 1999-10-04 2002-09-17 Motorola, Inc. Method of forming copper interconnection utilizing aluminum capping film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平6-204344A 1994.07.22

Also Published As

Publication number Publication date
US20100207271A1 (en) 2010-08-19
TWI501364B (zh) 2015-09-21
JP5249080B2 (ja) 2013-07-31
TW201112366A (en) 2011-04-01
CN101814476A (zh) 2010-08-25
JP2010192747A (ja) 2010-09-02
KR20100094943A (ko) 2010-08-27

Similar Documents

Publication Publication Date Title
CN101814476B (zh) 半导体装置
US10446504B2 (en) Chip package and method for forming the same
US10157811B2 (en) Chip package and method for forming the same
US8294275B2 (en) Chip package and method for forming the same
TWI515838B (zh) 電子元件封裝體及其製造方法
US9337097B2 (en) Chip package and method for forming the same
TWI551199B (zh) 具電性連接結構之基板及其製法
CN101211877A (zh) 半导体装置
US20170207194A1 (en) Chip package and method for forming the same
CN106252308A (zh) 晶片封装体与其制备方法
CN106169454A (zh) 晶片封装体及其制造方法
CN108364924B (zh) 半导体装置以及半导体装置的制造方法
US20110204487A1 (en) Semiconductor device and electronic apparatus
US12198997B2 (en) Semiconductor package comprising first molding layer and second molding layer with different thermal expansion coefficients
KR101059625B1 (ko) 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
JP5430848B2 (ja) 半導体素子、半導体装置、及びそれらの製造方法
JP4722690B2 (ja) 半導体装置およびその製造方法
JP7335036B2 (ja) 半導体パッケージの製造方法
WO2023163223A1 (ja) 半導体装置及び半導体装置の製造方法
TW202322290A (zh) 半導體裝置及其製造方法
CN114093827A (zh) 半导体装置和半导体装置的制造方法
JP4903123B2 (ja) 半導体装置の製造方法
JP2011034988A (ja) 半導体装置
JP2011171350A (ja) 半導体装置およびその製造方法
JP2011142247A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160324

Address after: Chiba County, Japan

Patentee after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba County, Japan

Patentee before: Seiko Instruments Inc.

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: DynaFine Semiconductor Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140827

Termination date: 20220212