CN100590859C - 具有环状支撑物的凸块结构及其制造方法 - Google Patents
具有环状支撑物的凸块结构及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 239000011241 protective layer Substances 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 101
- 238000000034 method Methods 0.000 claims description 67
- 239000000758 substrate Substances 0.000 claims description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims description 57
- 238000000059 patterning Methods 0.000 claims description 41
- 238000001020 plasma etching Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 13
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract 3
- 238000000576 coating method Methods 0.000 abstract 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000002362 mulch Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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Abstract
本发明公开了一种具有环状支撑物的凸块结构,其适于配置于一基板上。此基板具有至少一接垫与一保护层,其中保护层具有至少一开口,且开口暴露出接垫的一部分。此具有环状支撑物的凸块结构包括一球底金属层、一凸块以及一环状支撑物,其中球底金属层配置于保护层上,并覆盖保护层所暴露出的接垫。凸块配置于接垫上方的球底金属层上,且凸块的底面的直径小于凸块的顶面的直径,凸块的底部的直径小于开口的直径。此外,环状支撑物配置于凸块的周围,并与凸块接触,且环状支撑物的材质为光阻材料。此凸块结构不易出现底切效应。
Description
技术领域
本发明是有关于一种凸块结构及其制造方法,且特别是有关于一种具有环状支撑物的凸块结构及其制造方法。
背景技术
覆晶接合技术(flip chip interconnect technology)乃是一种将芯片(die)连接至一线路板的封装技术,其主要是在芯片的多个接垫上形成多个凸块(bump)。接着将芯片翻转(flip),并利用这些凸块来将芯片的这些接垫连接至线路板上的接合垫(terminal),以使得芯片可经由这些凸块而电性连接至线路板上。通常,凸块具有若干种类型,例如焊料凸块、金凸块、铜凸块、导电高分子凸块、高分子凸块等。
图1A为现有的金凸块的剖面图,而图1B为现有的金凸块的俯视图。请参考图1A与图1B,现有的金凸块结构适于配置在一芯片110上,而此芯片110上已形成有多个铝接垫120(图1A与图1B仅绘示一个铝接垫)与一保护层130。其中,保护层130具有多个开口130a,其分别暴露各铝接垫120的一部份。此外,现有的金凸块结构包括一球底金属层140与一金凸块150,其中球底金属层140配置开口130a内,并覆盖部分保护层130。金凸块150配置于球底金属层140上。由于此金凸块150覆盖于部分保护层130上方的球底金属层140上,因此金凸块150具有一环状凸起部150a,而这就所谓城墙效应(wall effect)。然而,此环状凸起部150a会影响金凸块150与其他承载器(未绘示)之间的接合强度。此外,由于球底金属层140仅配置于金凸块150的下方,因此当球底金属层140与金凸块150之间或是球底金属层140与保护层130之间产生裂缝时,此种现有的金凸块结构便容易出现底切效应(under cut effect)。
发明内容
本发明的目的在于提供一种具有环状支撑物的凸块结构,以改善底切效应。
本发明的目的在于提供一种具有环状支撑物的凸块结构的制造方法,以改善城墙效应。
本发明提出一种具有环状支撑物的凸块结构,其适于配置于一基板上。此基板具有至少一接垫与一保护层,其中保护层具有至少一开口,且开口暴露出接垫的一部分。此具有环状支撑物的凸块结构包括一球底金属层、一凸块以及一环状支撑物,其中球底金属层配置于保护层上,并覆盖保护层所暴露出的接垫。凸块配置于接垫上方的球底金属层上,且凸块的底面的直径小于凸块的顶面的直径,凸块的底部的直径小于开口的直径。此外,环状支撑物配置于凸块的周围,并与凸块接触,且环状支撑物的材质为光阻材料。
在本发明一实施例中,凸块包括一头部与一颈部,其中颈部连接头部与球底金属层,且头部的直径大于颈部的直径。
在本发明一实施例中,凸块的直径自底面往顶面逐渐增加。
在本发明一实施例中,环状支撑物的直径小于等于凸块的顶面的直径。
在本发明一实施例中,环状支撑物的直径自凸块的顶面往底面逐渐减小。
在本发明一实施例中,凸块包括金凸块。
本发明提出一种具有环状支撑物的凸块结构的制造方法,其包括下列步骤。首先,提供一基板,基板具有多个接垫与一保护层,其中保护层具有多个第一开口,且各第一开口暴露出接垫的一部分。接下来,在保护层上形成一球底金属材料层,以覆盖保护层与保护层所暴露出的接垫。之后,在球底金属材料层形成一图案化光阻层,其中图案化光阻层具有多个第二开口,分别暴露出接垫上方的球底金属材料层,且位于图案化光阻层的底面的各第二开口的直径小于位于图案化光阻层的顶面的各第二开口的直径。再来,在第二开口内形成多个凸块。然后,移除部分图案化光阻层,以在各凸块的周围形成一环状支撑物。接着,以环状支撑物与凸块为掩膜,图案化球底金属材料层,以形成多个球底金属层。
在本发明一实施例中,形成图案化光阻层的方法包括使用一光掩膜,以使得各开口的直径自图案化光阻层的底面往顶面逐渐增加。
在本发明一实施例中,光掩膜包括一半调式光掩膜。
在本发明一实施例中,形成图案化光阻层的方法包括使用一半调式光掩膜,以使各第二开口具有一头部与一颈部。颈部连接头部与球底金属材料层,其中头部的直径大于颈部的直径。
在本发明一实施例中,移除部分图案化光阻层的方法包括以凸块为掩膜进行一干蚀刻制程。
在本发明一实施例中,干蚀刻制程包括等离子蚀刻制程。
在本发明一实施例中,移除部分图案化光阻层的方法包括以下步骤。首先,以凸块为掩膜,对于图案化光阻层进行一曝光制程。接下来,对于曝光后的图案化光阻层,进行一显影制程,以移除部分图案化光阻层。
基于上述,由于本发明的凸块结构具有一环状支撑物,因此对比现有技术,此种具有环状支撑物的凸块结构较不易产生底切效应。此外,本发明将凸块形成于保护层的开口内,因此此种凸块结构具有平坦的顶面。
为让本发明的上述特征和优点能更明显易懂,下文特举较佳实施例,并配合附图作详细说明如下。
附图说明
图1A为现有的金凸块的剖面图。
图1B为现有的金凸块的俯视图。
图2A至图2D为本发明第一实施例的一种具有环状支撑物的凸块结构的制造方法的示意图。
图3A至图3D为本发明第二实施例的一种具有环状支撑物的凸块结构的制造方法的示意图。
具体实施方式
【第一实施例】
图2A至图2D为本发明第一实施例的一种具有环状支撑物的凸块结构的制造方法的示意图。请先参考图2A,本实施例的具有环状支撑物的凸块结构的制造方法包括下列步骤。首先,提供一基板210,基板210具有多个接垫220与一保护层230,其中保护层230具有多个第一开口230a,且各第一开口230a暴露出接垫220的一部分。值得注意的是,为了便于说明,本实施例的第一开口230a与接垫220均仅绘示一个。此外,此基板210可以是晶圆或是其他承载器,而接垫220的材质可以是铝、铜或是其他金属。
请继续参考图2A,在保护层230上形成一球底金属材料层310,以覆盖保护层230与保护层230所暴露出的接垫220。此外,形成球底金属材料层310的方法可以是溅镀制程、物理气相沉积制程或是化学气相沉积制程。
之后,在球底金属材料层310上形成一图案化光阻层320,其中图案化光阻层320具有多个第二开口322,分别暴露出接垫220上方的球底金属材料层310,且位于图案化光阻层320的底面的各第二开口322的直径小于位于图案化光阻层320的顶面的各第二开口322的直径。此外,形成图案化光阻层320的方法包括使用一光掩膜(图未示)。举例来说,上述光掩膜例如为一半调式光掩膜,并使用半调式光掩膜使各第二开口322具有一头部322a与一颈部322b,而颈部322b连接头部322a与球底金属材料层310,且头部322a的直径大于颈部322b的直径。此外,颈部322b的直径可小于第一开口230a的直径,以改善城墙效应。
请参考图2B,在第二开口322内形成多个凸块330。换言之,在保护层230所暴露出的接垫220上方的球底金属材料层310上形成凸块330,而凸块330的底面的直径小于凸块330的顶面的直径。在本实施例中,各凸块330包括一头部332与一颈部334,其中颈部334连接头部332与球底金属材料层310。此外,头部332的直径大于颈部334的直径,且颈部334的直径小于第一开口230a的直径。此外,头部332的顶面为平面。另外,形成凸块330的方式可以是电镀制程,而凸块330例如为金凸块、铜凸块。
请参考图2C,移除部分图案化光阻层320,以在各凸块330的周围形成一环状支撑物。依移除部分图案化光阻层320方法的不同,可形成环状支撑物324a或环状支撑物324b。此外,移除部分图案化光阻层320的方法可以是以凸块330为掩膜进行一干蚀刻制程,其中干蚀刻制程例如为等离子蚀刻制程。若使用等离子蚀刻制程来移除部分图案化光阻层320,则可能形成较平整的环状支撑物324a,也就是说,环状支撑物324a的直径小于等于凸块330顶面的直径。
然而,本领域的技术人员当可以其他方式来移除部分图案化光阻层320。举例来说,移除部分图案化光阻层320的方法可包括以下步骤。首先,以凸块330为掩膜,对图案化光阻层320进行一曝光制程。接下来,对曝光后的图案化光阻层320进行一显影制程,以移除部分图案化光阻层320。若使用再次进行曝光制程与显影制程来移除部分图案化光阻层320,则可能形成凹陷的环状支撑物324b,也即环状支撑物324b的直径自凸块330的顶面往凸块330的底面逐渐减小。
请参考图2D,以环状支撑物324a(324b)与凸块330为掩膜,图案化球底金属材料层310,以形成多个球底金属层312。至此,大致完成本实施例的具有环状支撑物的凸块结构的制造流程。此外,当基板210为晶圆时,在完成上述制程之后,也可以对于基板210进行一切割制程,以形成多个芯片结构(未绘示)。以下将就此具有环状支撑物的凸块结构的细部结构进行说明。
请继续参考图2D,本实施例的具有环状支撑物的凸块结构适于配置于一基板210上,基板210具有至少一接垫220与一保护层230,其中保护层230具有一第一开口230a,且第一开口230a暴露出接垫220的一部分。此外,基板210可以是芯片或晶圆。此具有环状支撑物的凸块结构包括一球底金属层312、一凸块330以及一环状支撑物324a(324b),其中球底金属层312配置于保护层230上,并覆盖保护层230所暴露出的接垫220。
凸块330配置于接垫220上方的球底金属层312上,且凸块330的底面的直径小于凸块330的顶面的直径。在本实施例中,上述凸块330包括一头部332与一颈部334,其中颈部334连接头部332与球底金属层312,且头部332的直径大于颈部334的直径。此外,颈部334的直径可小于第一开口230a的直径以防止城墙效应。另外,凸块330的材质例如为金、铜。此外,环状支撑物324a(324b)配置于凸块330的周围,并与凸块330接触,且环状支撑物324a(324b)的材质为光阻材料。
由于本实施例的凸块结构具有一环状支撑物324a(324b),以保护凸块330的颈部334,因此此种具有环状支撑物的凸块结构较不易产生底切效应。此外,凸块330的颈部334形成于第一开口230a内,且颈部334的直径小于第一开口230a的直径,因此此种具有环状支撑物的凸块结构具有平坦的顶面,以改善现有技术所具有的城墙效应。
【第二实施例】
在第二实施例与第一实施例中,相同或相似的元件标号代表相同或相似的元件,且第二实施例与第一实施例大致相同。以下将针对两实施例不同之处详加说明,相同之处便不再赘述。
本实施例的具有环状支撑物的凸块结构与第一实施例中具有环状支撑物的凸块结构的不同处在于,在本实施例中,凸块并不具有头部和颈部,而是使凸块的直径自底面往顶面逐渐增加。
图3A至图3D为本发明第二实施例的一种具有环状支撑物的凸块结构的制造方法的示意图。请先参考图2A,本实施例的具有环状支撑物的凸块结构的制造方法包括下列步骤。首先,提供一基板210。基板210已详细揭示于第一实施例中,在此不多做赘述。
请继续参考图3A,在保护层230上形成一球底金属材料层410,以覆盖保护层230与保护层230所暴露出的接垫220。此外,形成球底金属材料层410的方法可以是溅镀制程或是其他物理气相沉积制程。
之后,在球底金属材料层410形成一图案化光阻层420,其中图案化光阻层420具有多个第二开口422,分别暴露出接垫220上方的球底金属材料层410,且位于图案化光阻层320的底面的各第二开口422的直径小于位于图案化光阻层420的顶面的各第二开口422的直径。在本实施例中,第二开口422的直径自底面往顶面逐渐增加,并可使第二开口422的底面的直径小于第一开口230a。此外,形成图案化光阻层420的方法可以是采用半调式光掩膜。然而,形成图案化光阻层420的方法并不限于上述使用半调式光掩膜的方式,所属技术领域中具有通常知识者也可用其他方式形成图案化光阻层420,例如改变入射光的焦点深度(depth offocus)使图案化光阻层420具有第二开口422。
请参考图3B,在第二开口422内形成多个凸块430。换言之,在保护层230所暴露出的接垫220上方的球底金属材料层410上形成凸块430,而凸块430的底面的直径小于凸块430的顶面的直径。在本实施例中,各凸块430的直径自底面往顶面逐渐增加。凸块430的底面的直径小于第一开口230a的直径,因此凸块430的顶面为平面。另外,形成凸块430的方式可以是电镀制程,而凸块430例如为金凸块、铜凸块。
请参考图3C,移除部分图案化光阻层420,以在各凸块430的周围形成一环状支撑物424a(424b)。移除部分图案化光阻层420的方法请参考第一实施例中移除部分图案化光阻层320的方法。简单而言,若使用等离子蚀刻制程来移除部分图案化光阻层420,则可能形成较平整的环状支撑物424a,也就是说,环状支撑物424a的直径小于等于凸块430顶面的直径。此外,若使用再次进行曝光制程与显影制程来移除部分图案化光阻层420,则可能形成凹陷的环状支撑物424b,也即环状支撑物424b的直径自凸块430的顶面往凸块430的底面逐渐减小。
请参考图3D,以环状支撑物424a(424b)与凸块430为掩膜,图案化球底金属材料层410,以形成多个球底金属层412。至此,大致完成本实施例的具有环状支撑物的凸块结构的制造流程。此外,若基板210为晶圆时,也可以对于基板210进行一切割制程,以形成多个芯片结构(未绘示)。以下将就此具有环状支撑物的凸块结构与第一实施例中具有环状支撑物的凸块结构之不同处加以说明。
请参考图2D及图3D,本实施例中具有环状支撑物的凸块结构和第一实施例中具有环状支撑物的凸块结构之不同处在于,本实施例中的凸块430并不具有如凸块330的头部332与颈部334。凸块430的直径为由凸块430的底面至凸块430的顶面逐渐增加,而环状支撑物424a(424b)的内直径也是由环状支撑物424a(424b)的底面至环状支撑物424a(424b)的顶面逐渐增加。
综上所述,本发明至少具有以下优点:
1.本发明的凸块结构具有一环状支撑物,因此此种具有环状支撑物的凸块结构较不易产生底切效应。
2.本发明将凸块形成于保护层的开口内,因此此种具有环状支撑物的凸块结构具有平坦的顶面。
虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许更动与润饰,因此本发明的保护范围当以权利要求所界定的为准。
Claims (13)
1.一种具有环状支撑物的凸块结构,适于配置于一基板上,该基板具有至少一接垫与一保护层,其中该保护层具有至少一开口,且该开口暴露出该接垫的一部分,该具有环状支撑物的凸块结构包括:
一球底金属层,配置于该保护层上,并覆盖该保护层所暴露出的该接垫;
一凸块,配置于该接垫上方的该球底金属层上,且该凸块的底面的直径小于该凸块的顶面的直径,该凸块的底部的直径小于该开口的直径;以及
一环状支撑物,配置于该凸块的周围,并与该凸块接触,且该环状支撑物的材质为光阻材料。
2.如权利要求1所述的具有环状支撑物的凸块结构,其特征在于,该凸块包括一头部与一颈部,该颈部连接该头部与该球底金属层,且该头部的直径大于该颈部的直径。
3.如权利要求1所述的具有环状支撑物的凸块结构,其特征在于,该凸块的直径自底面往顶面逐渐增加。
4.如权利要求1所述的具有环状支撑物的凸块结构,其特征在于,该环状支撑物的直径小于等于该凸块的顶面的直径。
5.如权利要求4所述的具有环状支撑物的凸块结构,其特征在于,该环状支撑物的直径自该凸块的顶面往底面逐渐减小。
6.如权利要求1所述的具有环状支撑物的凸块结构,其特征在于,该凸块包括金凸块。
7.一种具有环状支撑物的凸块结构的制造方法,包括:
提供一基板,该基板具有多个接垫与一保护层,其中该保护层具有多个第一开口,且各该第一开口暴露出该接垫的一部分;
在该保护层上形成一球底金属材料层,以覆盖该保护层与该保护层所暴露出的该些接垫;
在该球底金属材料层形成一图案化光阻层,其中该图案化光阻层具有多个第二开口,分别暴露出该些接垫上方的该球底金属材料层,且位于该图案化光阻层的底面的各该第二开口的直径小于位于该图案化光阻层的顶面的各该第二开口的直径;
在该些第二开口内形成多个凸块;
移除部分该图案化光阻层,以在各该凸块的周围形成一环状支撑物;以及
以该些环状支撑物与该些凸块为掩膜,图案化该球底金属材料层,以形成多个球底金属层。
8.如权利要求7所述的具有环状支撑物的凸块结构的制造方法,其特征在于,形成该图案化光阻层的方法包括使用一光掩膜,以使得各该开口的直径自该图案化光阻层的底面往顶面逐渐增加。
9.如权利要求8所述的具有环状支撑物的凸块结构的制造方法,其特征在于,该光掩膜包括一半调式光掩膜。
10.如权利要求7所述的具有环状支撑物的凸块结构的制造方法,其特征在于,形成该图案化光阻层的方法包括使用一半调式光掩膜,以使各该第二开口具有一头部与一颈部,该颈部连接该头部与该球底金属材料层,其中该头部的直径大于该颈部的直径。
11.如权利要求7所述的具有环状支撑物的凸块结构的制造方法,其特征在于,移除部分该图案化光阻层的方法包括以该些凸块为掩膜进行一干蚀刻制程。
12.如权利要求11所述的具有环状支撑物的凸块结构的制造方法,其特征在于,该干蚀刻制程包括等离子蚀刻制程。
13.如权利要求7所述的具有环状支撑物的凸块结构的制造方法,其特征在于,移除部分该图案化光阻层的方法包括:
以该些凸块为掩膜,对于该图案化光阻层进行一曝光制程;以及
对于曝光后的该图案化光阻层,进行一显影制程,以移除部分该图案化光阻层。
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US11/693,741 US8030767B2 (en) | 2007-01-16 | 2007-03-30 | Bump structure with annular support |
US13/209,456 US8268717B2 (en) | 2007-01-16 | 2011-08-15 | Manufacturing method of bump structure with annular support |
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Also Published As
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US8268717B2 (en) | 2012-09-18 |
US8030767B2 (en) | 2011-10-04 |
US20110300705A1 (en) | 2011-12-08 |
CN101226908A (zh) | 2008-07-23 |
US20080169559A1 (en) | 2008-07-17 |
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