CN101803020B - 叠层安装结构体和叠层安装结构体的制造方法 - Google Patents

叠层安装结构体和叠层安装结构体的制造方法 Download PDF

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CN101803020B
CN101803020B CN2008801075629A CN200880107562A CN101803020B CN 101803020 B CN101803020 B CN 101803020B CN 2008801075629 A CN2008801075629 A CN 2008801075629A CN 200880107562 A CN200880107562 A CN 200880107562A CN 101803020 B CN101803020 B CN 101803020B
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conductive component
substrate
assembling structure
lamination assembling
parts
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CN101803020A (zh
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中村干夫
近藤雄
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Olympus Corp
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  • Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
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Abstract

本发明提供一种可实现窄间距化、并可确保能安装被安装部件的高度的叠层安装结构体和叠层安装结构体的制造方法。叠层安装结构体具有：多个部件，其在至少一个主面上具有为设置被安装部件并使该被安装部件工作所需要的安装区域、和被安装部件进行工作所需的信号传递用的连接用区域；以及导电部件，其配置在对置的部件之间的连接用区域内，导电部件的截面与连接用区域相同或者比其小，导电部件的端部从一个部件的主面到达另一个部件的主面，导电部件的高度规定了安装区域的间隔。

Description

叠层安装结构体和叠层安装结构体的制造方法
技术领域
本发明涉及叠层安装结构体和叠层安装结构体的制造方法。
背景技术
以往，作为连接叠层的电子电路基板的基板间连接部件，有专利文献1(日本特开2001-144399号公报)记载的基板间连接部件。该基板间连接部件使用弹性体覆盖由具有刚性的导体构成的芯体，并使用具有导电性的材料包覆弹性体的周围。通过这样构成基板间连接部件，具有在修补作业时分离电子电路基板无需加热的效果。
并且，作为其他现有例，提出了下面的现有例：为了实现内置有电子部件且小型高密度的基板，使用树脂将电子部件固定在布线基板主体的贯通孔内，之后通过对树脂进行研磨和钻孔加工来使电子部件的电极露出，然后在布线基板主体的正面、背面形成布线层。
专利文献1：日本特开2001-144399号公报
然而，对于专利文献1记载的基板间连接部件，即使能实现窄间距化，也具有以下问题。即，(1)以将叠层的电子电路基板相互拆装作为前提；(2)在形成多个连接部件的情况下，向凹部的对位和组装困难；(3)未考虑到将多个电子电路基板进行叠层；(4)由于至少需要芯体和弹性体这两种部件，因而小型化困难。
并且，在上述其他现有例中，能内置于基板厚度内的电子部件被限制为高度比基板厚度小的部件，而且必须经由电子部件连接基板主体正、背面的布线层，具有布线层设计上的制约大的问题。在不经由电子部件连接基板主体正、背面的布线层的情况下，可经由通孔来连接，然而需要设置比通孔直径大的电极焊盘(焊接电极)，基板连接部的窄间距化困难，因而对于减小基板主面的面积存在限度。
发明内容
本发明是鉴于上述而作成的，本发明的目的是提供一种可实现窄间距化、并可确保能安装被安装部件的高度的叠层安装结构体和叠层安装结构体的制造方法。并且，本发明的另一目的是提供一种基板的布线自由度高、能实现基板连接部的窄间距化、从而基板主面的面积小的叠层安装结构体。
为了解决上述问题并达到目的，本发明的叠层安装结构体，其特征在于，所述叠层安装结构体具有：多个部件，其在至少一个主面上具有为了设置被安装部件并使该被安装部件工作所需要的安装区域、和所述被安装部件进行工作所需的信号传递用的连接用区域；以及导电部件，其配置在对置的部件之间的连接用区域内，导电部件的截面与连接用区域相同或者比其小，导电部件的端部从一个部件的主面到达另一个部件的主面，导电部件的高度规定了安装区域的间隔，并且，配置于一部件的主面侧的所述导电部件的端部面积大于配置于与一部件对置的另一部件的主面侧的所述导电部件的端部面积。
在本发明的叠层安装结构体中，优选的是，在导电部件的周围设置有加强部件。
在本发明的叠层安装结构体中，期望的是，在安装区域内安装有被安装部件，多个部件间的安装区域的间隔比被安装部件的高度大。
在本发明的叠层安装结构体中，可以构成为：加强部件被填充在对置的部件之间的安装区域内。
在本发明的叠层安装结构体中，优选的是，导电部件是棒状。
在本发明的叠层安装结构体中，期望的是，导电部件是在一个端部被连接的状态下，将另一个端部安装在所述部件上，之后去除所述被连接的部分而形成的。
在本发明的叠层安装结构体中，优选的是，在加强部件的一个端部形成有至少一部分与导电部件电连接的导电图形。
并且，本发明的叠层安装结构体的制造方法，其特征在于，制造方法具有：将被安装部件和多个导电部件分别安装在第1部件上的工序，所述导电部件比所述被安装部件的高度高、且安装于所述第1部件上的一侧的端部的直径大于相反侧的端部的直径、并且处于所述相反侧的端部彼此不连接的状态；以及在第1部件上的导电部件的周围，使导电部件的与第1部件相反侧的端部露出而形成加强部件的加强工序，在安装所述导电部件的工序中，使所述导电部件的另一个端部的面积大于一个端部的面积，将面积较大侧的该端部安装在第1部件上，并且，在加强工序中，对加强部件的与第1部件相反的面进行研磨来使其平坦化，并使导电部件的端部露出。
在本发明的叠层安装结构体的制造方法中，期望的是，制造方法还具有连接工序：将导电部件的一个端部形成为多个所述导电体连接起来的状态。
在本发明的叠层安装结构体的制造方法中，优选的是，制造方法具有：在使导电部件的与第1部件相反侧的端部露出而形成加强部件之后，在所露出的导电部件的端部表面上形成金属膜的工序；以及在导电部件的端部表面的金属膜上形成凸起的工序。
在本发明的叠层安装结构体的制造方法中，可以构成为：第1部件的大小相当于多个模块，制造方法在绝缘材料形成工序之后具有单片化工序。
根据本发明涉及的叠层安装结构体和叠层安装结构体的制造方法，取得这样的效果：能提供一种可实现窄间距化、并可确保能安装被安装部件的高度的叠层安装结构体和叠层安装结构体的制造方法。
附图说明
图1是将实施例1涉及的叠层安装结构体的结构分离为第1基板和第2基板来示出的立体图。
图2是示出实施例1涉及的叠层安装结构体的结构的剖视图。
图3是将实施例2涉及的叠层安装结构体的结构分离为第1基板和第2基板来示出的立体图。
图4是示出实施例2涉及的导电部件和加强部件的关系的放大立体图。
图5是示出实施例3涉及的叠层安装结构体的结构的立体图。
图6是示出实施例4涉及的叠层安装结构体的制造方法流程的流程图。
图7是示出实施例5涉及的叠层安装结构体的制造方法流程的流程图。
图8是示出实施例6涉及的叠层安装结构体的制造方法流程的流程图。
图9的右侧是示出与图8的S1～S6的工序对应的叠层安装结构体的结构的放大立体图，图9的左侧是示出右侧图的单片化后的叠层安装结构体的聚集状态的立体图。
图10是示出与图8的S1～S6的工序对应的叠层安装结构体的结构的侧视图。
图11A是示出变形例涉及的叠层安装结构体的结构的立体图。
图11B是示出变形例涉及的叠层安装结构体的结构的另一立体图。
图11C是示出变形例涉及的叠层安装结构体的结构的又一立体图。
图11D是示出变形例涉及的叠层安装结构体的结构的其他立体图。
图12是示出变形例涉及的叠层安装结构体的制造方法流程的流程图。
标号说明
10：叠层安装结构体；20：第1基板；20a：主面；21：导电部件；21a：端部；22：电极；23：绝缘层；23a：上面；24：布线层；26：电子部件；29：凸起；30：第2基板；32：电极；34：布线层；36：电子部件；40：叠层安装结构体；50：第1基板；51：导电部件；52：电极；56：电子部件；57：加强部件；60：第2基板；66：电子部件；70：叠层安装结构体；80：第1基板；81：导电部件；83：绝缘层；88：布线；90：模块。
具体实施方式
以下，根据附图详细说明本发明涉及的叠层安装结构体和叠层安装结构体的制造方法的实施例。另外，本发明不受该实施例的限定。
在本发明涉及的叠层安装结构体的制造方法中，在将被安装部件安装于电路基板上的同时，将比其中高度最高的部件长的导电部件垂直于基板固定并连接到电路基板上的电极，在导电部件和被安装部件的间隙内填充树脂，之后通过研磨仅使导电部件的头部露出。通过使第2基板与露出的导电部件连接，或者通过印刷在研磨面上形成电路，由此将上、下电路基板以电气和机械方式连接固定，从而形成本发明涉及的叠层安装结构体。以下说明具体的实施例。
实施例1
图1是将本发明涉及的叠层安装结构体的实施例1的结构分离为第1基板20和第2基板30来示出的立体图。图2是示出实施例1涉及的叠层安装结构体10的结构的剖视图。
如图1所示，在第1基板20的主面20a上安装有电子部件26。并且，在第2基板30上安装有电子部件36。第1基板20和第2基板30对置配置。第1基板20和第2基板30可以使用多层基板或电子部件内置基板。
在第1基板20的电子部件26之间设有电极22，在电极22上设置有大致圆柱状的导电部件21。导电部件21的长度全部大致相同，比安装于第1基板20上的电子部件26中最高的高度更大。并且，导电部件21的与其长度方向垂直的正交剖面面积小于等于电极22的面积。
导电部件21在使用圆柱状的部件的情况下，通过从线材上切取，即可容易形成。此时，在使导电部件21的安装于第1基板20上的一侧的端部的直径增大的情况下，可以容易且可靠地进行向第1基板20上的安装。另一方面，导电部件的与第1基板20相反侧的端部也可以在若干导电部件相连接的状态下安装。
优选的是，导电部件21使用电阻低的材料(例如Cu(铜))。并且，优选的是，在导电部件21的表面上实施例如镀金(Au)，用于防止母材的氧化。而且，对导电部件21实施用于容易进行软钎焊的表面处理，导电部件21的一个端部和电极22通过软钎焊而进行导电接合。另外，还可以取代软钎焊，而通过例如使用各向异性导电性材料的ACP施工法或ACF施工法、NCP施工法的接触导电来实现导通。
如图2所示，在第1基板20和第2基板30上分别形成有布线层24、34。在第1基板20上的电子部件26和导电部件21的周围，填充树脂绝缘材料(加强部件)并使其固化来形成绝缘层23。在该绝缘层23中，从第2基板30侧的面(上面)23a仅露出导电部件21的第2基板30侧的端部21a。
在第2基板30的与第1基板20对置的面30a的与导电部件21对置的位置上设置有电极32。第2基板30与绝缘材料23的表面接合，以使第1基板20的导电部件21的端部21a和电极32电连接。另外，可以将导电部件(未图示)设置在第2基板30的露出面上的电极(未图示)处等，也可以进一步增加叠层数。
在实施例1中，由于将上、下电路基板连接起来的导电部件可自由配置在电子部件之间，因而不会成为各基板的布线设计的制约。而且，由于安装导电部件的电极不是通孔电极，因而无需焊接电极，由于能以窄间距配置导电部件，因而可提供基板主面的面积小的叠层安装结构体。并且，由于无需对基板进行贯通孔加工和凹部加工，因而可提供低价格且基板主面的面积小的叠层安装结构体。
实施例2
图3是将本发明涉及的叠层安装结构体的实施例2的结构分离为第1基板50和第2基板60来示出的立体图。图4是示出实施例2涉及的导电部件和加强部件的关系的放大立体图。
在实施例2中，与实施例1的不同点是，在导电部件51的周围，在使安装区域的一部分或全部露出的状态下形成加强部件57。即，实施例1的叠层安装结构体10中的第1基板20、导电部件21、电极22、电子部件26、第2基板30以及电子部件36分别对应于实施例2的叠层安装结构体40中的第1基板50、导电部件51、电极52、电子部件56、第2基板60以及电子部件66。并且，尽管未图示，然而在实施例2的叠层安装结构体40中，也形成有与实施例1的叠层安装结构体10的布线层24、34相同的布线层。
在实施例2中，由于在加强部件形成后电子部件露出，因而可在将要连接第2基板之前进行电子部件的检查，可减少叠层安装结构体的不良品。
如图4例示，在导电部件51的周围，以保留第2基板60侧的端部51a的方式配置加强部件57。作为加强部件57，例如使用当配置在导电部件51的周围时是液状、且在配置后固化的物质。
实施例3
图5是示出本发明涉及的叠层安装结构体的实施例3的结构的立体图。
在实施例3的叠层安装结构体70中，与实施例1的绝缘层23一样，在第1基板80上的电子部件(未图示)和导电部件81的周围形成有由树脂的绝缘材料制成的绝缘层83，并在该绝缘层83中的远离第1基板80的面上形成有布线88，以使其连接导电部件81。即在实施例3中，不载置实施例1的第2基板30和实施例2的第2基板60那样的第2基板，而在绝缘层83上直接形成布线88。另外，布线88的形成方法可以使用采用电镀、溅镀、蒸镀或喷墨、分散的印刷布线。通过采用这样的结构，从而不需要第2基板的基材部分，因此可提供能提高设计的自由度并且叠层高度低且基板主面的面积小的叠层安装结构体。
(变形例)
下面说明叠层安装结构体的变形例。图11A、图11B、图11C和图11D示出变形例涉及的叠层安装结构体的结构。
如上所述，导电部件21的与第1基板20相反侧的端部还可以在若干导电部件21连接起来的状态下进行安装。对于若干导电部件连接起来的状态，可通过使用Cu等的电镀在基板100上形成导电部件21、或者对Cu等导电材料的板100进行冲压加工等来形成(图11A)。
在本例中，将所连接的导电部件21与第1基板20分开制作，并将该导电部件21与第1基板20连接。图11B示出引脚基板接合的状态。然后，如图11C所示，在第1基板20和导电部件21连接起来的部分之间涂布树脂并使其固化。这里，可以先在第1基板20上涂布树脂。
将第1基板20和导电部件21连接起来的部分通过研磨来去除，使各导电部件21露出。在露出的导电部件21的端部形成防止导电部件21氧化的金属膜。最后，如图11D所示，将第2基板30进行叠层，使基板20、30之间连接。由此，形成叠层安装结构体。因此，在电子部件26的高度是例如0.3mm至1mm等较高的情况下，可将比电子部件26的高度长的导电部件21自由配置在第1基板20的主面20a上，可使第1基板20和第2基板30连接。并且，可使连接间距实现窄间距化。
这样，导电部件21在一个端部连接了多个的状态下一并安装在第1基板20上。因此，可容易安装导电部件21。并且，由于可一并制作突起电极，因而能实现更窄的间距。其结果，可容易将叠层安装结构体制造得较小。
接下来，列举实施例4至实施例6来说明本发明涉及的叠层安装结构体的制造方法。
实施例4
图6是示出实施例4涉及的叠层安装结构体的制造方法流程的流程图。实施例4的制造方法可应用于实施例1至实施例3和变形例，假定在实施例4至实施例6的说明中使用实施例1的标号。
首先，将电子部件26安装在第1基板20上(步骤S1)，同时将导电部件21安装在第1基板20的电极22上(步骤S2)。前者的安装可以使用一般的表面安装工序等。并且，在通过例如软钎焊进行后者的安装的情况下，将焊膏和焊剂通过印刷法等供给到电极22上，使用安装装置或夹具将导电部件定位固定在电极22上并进行加热，从而可安装导电部件21。另外，在第1基板20上的电子部件26和导电部件21的安装，可以在安装电子部件26之后安装导电部件21(参照实施例5或实施例6)，反之亦然。
然后，在安装有电子部件26和导电部件21的第1基板20上，按照导电部件21的与第1基板20相反侧(第2基板30侧)的端面21a露出的方式，涂布液状密封树脂等并使其固化，从而在第1基板20上的电子部件26和导电部件21的周围形成绝缘层23。由此，将导电部件21和电子部件26密封(步骤S3)。树脂的固化方法有热固化和双液混合等。在使用与第1基板20的外形和期望的固化后形状一致的模具的情况下，可容易准备好固化后的树脂形状。另外，在将实施例4应用于实施例2的情况下，在步骤S3中，取代树脂密封，而将加强部件配置在导电部件的周围。
之后，经由形成在导电部件21的与第1基板20相反侧的端面上的金属膜状的凸起，将第2基板30与第1基板20叠层连接。另外，在将实施例4应用于实施例3的情况下，不是对第2基板30进行叠层，而是在绝缘层23的与第1基板20相反侧的面23a上直接形成布线。
由于通过以上工序制造叠层安装结构体，因而能以非常少的工序提供基板主面的面积小的叠层安装结构体。
实施例5
图7是示出实施例5涉及的叠层安装结构体的制造方法流程的流程图。在实施例5中，由于电子部件安装(步骤S1)、导电部件安装(步骤S2)以及树脂密封(步骤S3)的各工序与实施例4公用，因而省略关于这些工序的说明。
在树脂密封(步骤S3)之后，按照保持绝缘层23与第1基板20的主面20a平行的方式，对绝缘层23的上面23a进行研磨使其平坦化，并使导电部件21的与第1基板20相反侧的端面21a分别露出(步骤S4)。
然后，在露出的导电部件21的端面21a上形成金属膜(UBM层)(步骤S5)。通过形成金属膜，可防止导电部件21的氧化等，可在后续工序的凸起形成时形成电阻低、且强度高的凸起。
接下来，在形成于露出的导电部件21的端面21a上的金属膜上形成凸起(步骤S6)。作为凸起材质，可使用钎料和Au。
之后，经由形成在导电部件21的端面21a上的金属膜上的凸起29(图9、图10)对第2基板30进行叠层连接。
通过使用这样的方法制造叠层安装结构体，使绝缘层23的上面23a平坦化，而且，可靠地与第1基板20的主面20a处于平行，因而导电部件21的端面21a具有容易连接第2基板30的结构。因此，可提供第1基板20和第2基板30的连接质量高、且基板主面的面积小的叠层安装结构体。
实施例6
图8是示出实施例6涉及的叠层安装结构体的制造方法流程的流程图。图9的右侧是示出与图8的S1～S6的工序对应的叠层安装结构体的结构的放大立体图，左侧是示出右侧图的单片化后的叠层安装结构体的聚集状态的立体图。图10是示出与图8的S1～S6的工序对应的叠层安装结构体的结构的侧视图。
在实施例6中，电子部件安装(步骤S1)、导电部件安装(步骤S2)、树脂密封(步骤S3)、研磨(步骤S4)、UBM层形成(步骤S5)以及凸起形成(步骤S6)的各工序与实施例5公用。在凸起29形成后，在第1基板20内形成多个模块90，通过切割等单片化工序单独进行模块化(步骤S7)。
根据这样的制造方法，可一次制作多个模块，因而可提供模块制造成本低、且基板主面的面积小的叠层安装结构体。
(变形例)
图12是示出变形例涉及的叠层安装结构体的制造方法流程的流程图。关于与前面已经叙述的各实施例的工序相同的内容，附上相同标号，省略重复说明。首先，在本变形例中，首先将电子部件26安装在第1基板20上(步骤S1)。
在基材100上的与设在第1基板20的电子部件26之间的电极对置的位置，通过电镀使Cu生长。由此，形成若干导电部件21的一个端部连接起来的状态(步骤S2a)。
对于将导电部件21的一个端部连接起来的状态，可使用以下等的各种方法：通过电镀在基材100上形成Cu；在Cu等导电材料的板100上进行冲压加工等来形成导电部件21；在将棒状的导电部件21排列于夹具上的状态下，对端面进行电镀。导电部件21的高度(长度)形成为比电子部件26的高度大。
将导电部件21的未连接侧的端部与第1基板20的主面20a的电极通过软钎焊等接合(步骤S2)。在导电部件21的一个端部连接起来的状态下，对其表面实施Au电镀等的情况下，可防止Cu的氧化，能可靠地进行软钎焊。
在第1基板20和导电部件21连接起来的部分之间涂布树脂并使其固化(步骤S3)。这里，可以先在第1基板20上涂布树脂。
将第1基板20和导电部件21连接起来的部分通过研磨来去除，使各导电部件21露出(步骤S4)。导电部件21的周围使用树脂来加强。因此，可稳定地研磨导电部件21。而且，可通过研磨使导电部件21的高度(长度)精密一致。因此，可扩大使用的导电部件21的长度公差。
在电子部件26的高度是例如0.3mm至1mm等较高的情况下，可将比电子部件26的高度长的导电部件21自由配置在第1基板20的主面20a上，可使第1基板20和第2基板30连接。并且，可使连接间距实现窄间距化。
之后，在露出的导电部件21的端部形成防止导电部件21氧化的金属膜。然后，通过连接第2基板30来形成叠层安装结构体。
这样，导电部件21在一个端部连接了多个的状态下一并安装在第1基板20上。因此，可容易安装导电部件21。并且，由于可一并制作突起电极，因而能实现更窄的间距。其结果，可容易将叠层安装结构体制造得小。
如以上说明那样，根据本发明，由于可将连接上、下电路基板的导电部件自由配置在电子部件之间，因而不会成为各基板的布线设计的制约。而且，由于安装导电部件的电极不是通孔电极，因而无需焊接电极，由于能以窄间距配置导电部件，因而可提供基板主面的面积小的叠层安装结构体。
产业上的可利用性
如以上所述，本发明涉及的叠层安装结构体和叠层安装结构体的制造方法对安装结构体的小型化是有用的，特别是适合于内窥镜前端摄像单元的高密度安装。

Claims (2)

1.一种叠层安装结构体的制造方法，其特征在于，所述制造方法具有：
将被安装部件和多个导电部件分别安装在第1部件上的工序，所述导电部件比所述被安装部件的高度高、且安装于所述第1部件上的一侧的端部的直径大于相反侧的端部的直径、并且处于所述相反侧的端部彼此不连接的状态；以及
在所述第1部件上的所述导电部件的周围，使所述导电部件的与所述第1部件相反侧的端部露出而形成加强部件的加强工序，
在安装所述导电部件的工序中，使所述导电部件的另一个端部的面积大于一个端部的面积，将面积较大侧的该端部安装在第1部件上，
并且，在所述加强工序中，对所述加强部件的与所述第1部件相反的面进行研磨而使其平坦化，并使导电部件的端部露出。
2.根据权利要求1所述的叠层安装结构体的制造方法，其特征在于，所述制造方法具有：
在使所述导电部件的与所述第1部件相反侧的端部露出而形成所述加强部件之后，在所露出的所述导电部件的端部表面上形成金属膜的工序；以及
在所述导电部件的端部表面的金属膜上形成凸起的工序。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5449237B2 (ja) * 2011-03-09 2014-03-19 古河電気工業株式会社 基板および基板の製造方法
JP2014123638A (ja) * 2012-12-21 2014-07-03 Murata Mfg Co Ltd 部品モジュール
JP6205228B2 (ja) * 2013-09-30 2017-09-27 オリンパス株式会社 撮像モジュールおよび内視鏡装置
DE102014101366B3 (de) * 2014-02-04 2015-05-13 Infineon Technologies Ag Chip-Montage an über Chip hinausstehender Adhäsions- bzw. Dielektrikumsschicht auf Substrat
KR20150092881A (ko) * 2014-02-06 2015-08-17 엘지이노텍 주식회사 인쇄회로기판, 패키지 기판 및 이의 제조 방법
JP6274135B2 (ja) * 2015-03-12 2018-02-07 株式会社村田製作所 コイルモジュール
JPWO2017010216A1 (ja) * 2015-07-15 2018-04-12 株式会社村田製作所 電子部品
US9825597B2 (en) 2015-12-30 2017-11-21 Skyworks Solutions, Inc. Impedance transformation circuit for amplifier
US10269769B2 (en) 2016-04-18 2019-04-23 Skyworks Solutions, Inc. System in package with vertically arranged radio frequency componentry
US10297576B2 (en) 2016-04-18 2019-05-21 Skyworks Solutions, Inc. Reduced form factor radio frequency system-in-package
US10062670B2 (en) 2016-04-18 2018-08-28 Skyworks Solutions, Inc. Radio frequency system-in-package with stacked clocking crystal
US9918386B2 (en) 2016-04-18 2018-03-13 Skyworks Solutions, Inc. Surface mount device stacking for reduced form factor
TW202329611A (zh) 2016-12-29 2023-07-16 美商天工方案公司 前端系統及相關裝置、積體電路、模組及方法
US10515924B2 (en) 2017-03-10 2019-12-24 Skyworks Solutions, Inc. Radio frequency modules
DE102017212739A1 (de) * 2017-07-25 2019-01-31 Siemens Aktiengesellschaft Halbleiterbauteil sowie Verfahren zu dessen Herstellung
CN109714910B (zh) * 2019-01-29 2020-08-14 维沃移动通信有限公司 一种多层电路板的制造方法、多层电路板和移动终端
JP2022080655A (ja) * 2020-11-18 2022-05-30 株式会社ディスコ ウェーハの製造方法及び積層デバイスチップの製造方法
JP2022080658A (ja) * 2020-11-18 2022-05-30 株式会社ディスコ ウェーハの製造方法及び積層デバイスチップの製造方法
JP2022080657A (ja) * 2020-11-18 2022-05-30 株式会社ディスコ ウェーハの製造方法及び積層デバイスチップの製造方法
JP2022080653A (ja) * 2020-11-18 2022-05-30 株式会社ディスコ ウェーハの製造方法及び積層デバイスチップの製造方法
CN117135829B (zh) * 2023-08-30 2024-05-14 西南石油大学 一种基板自动裁切打磨堆叠卸载一体化机

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241032A (zh) * 1998-06-26 2000-01-12 国际商业机器公司 高集成度芯片上芯片封装

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102149A (ja) * 1991-10-04 1993-04-23 Sharp Corp 半導体装置の製造方法
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
KR100290784B1 (ko) * 1998-09-15 2001-07-12 박종섭 스택 패키지 및 그 제조방법
JP2000323806A (ja) * 1999-05-13 2000-11-24 Matsushita Electric Ind Co Ltd バンプ付セラミック回路基板及びその製造方法
JP3833859B2 (ja) * 1999-10-14 2006-10-18 ローム株式会社 半導体装置およびその製造方法
US7129110B1 (en) * 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US6448106B1 (en) 1999-11-09 2002-09-10 Fujitsu Limited Modules with pins and methods for making modules with pins
JP2001144399A (ja) * 1999-11-17 2001-05-25 Sony Corp 基板間接続部材、電子回路基板、電子回路装置及び電子回路装置の製造方法
JP4320492B2 (ja) * 1999-12-08 2009-08-26 株式会社デンソー 半導体素子の実装構造および半導体素子の実装構造の製造方法
JP2002134653A (ja) * 2000-10-23 2002-05-10 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
JP4380088B2 (ja) * 2001-05-31 2009-12-09 株式会社デンソー 積層回路モジュールの製造方法
JP2006165252A (ja) * 2004-12-07 2006-06-22 Shinko Electric Ind Co Ltd チップ内蔵基板の製造方法
KR100734264B1 (ko) * 2005-06-16 2007-07-02 삼성전자주식회사 집적회로 패키지와 집적회로 모듈
JP4635202B2 (ja) * 2005-07-20 2011-02-23 国立大学法人九州工業大学 両面電極パッケージの製造方法
JP3960479B1 (ja) * 2006-07-07 2007-08-15 国立大学法人九州工業大学 両面電極構造の半導体装置の製造方法
JP4793155B2 (ja) * 2006-07-31 2011-10-12 エプソントヨコム株式会社 プリント基板、プリント基板ユニット、表面実装型高安定圧電発振器、及びプリント基板の加工方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1241032A (zh) * 1998-06-26 2000-01-12 国际商业机器公司 高集成度芯片上芯片封装

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JP特开2001-110829A 2001.04.20
JP特开2001-144399A 2001.05.25

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