CN101689530B - 再生基片的方法、层积晶片制造法和适宜的再生供体基片 - Google Patents

再生基片的方法、层积晶片制造法和适宜的再生供体基片 Download PDF

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CN101689530B
CN101689530B CN2008800213829A CN200880021382A CN101689530B CN 101689530 B CN101689530 B CN 101689530B CN 2008800213829 A CN2008800213829 A CN 2008800213829A CN 200880021382 A CN200880021382 A CN 200880021382A CN 101689530 B CN101689530 B CN 101689530B
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region
substrate
removal
height
modified
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CN101689530A (zh
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塞西尔·奥尔内特
哈里德·拉德万
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Soitec SA
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Soitec SA
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Priority claimed from PCT/EP2008/005107 external-priority patent/WO2009007003A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24488—Differential nonuniformity at margin

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
CN2008800213829A 2007-07-11 2008-06-24 再生基片的方法、层积晶片制造法和适宜的再生供体基片 Active CN101689530B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
EP07290869A EP2015354A1 (en) 2007-07-11 2007-07-11 Method for recycling a substrate, laminated wafer fabricating method and suitable recycled donor substrate
EP07290869.2 2007-07-11
EP08290490A EP2037495B1 (en) 2007-07-11 2008-05-28 Method for recycling a substrate, laminated wafer fabricating method and suitable recycled donor substrate
EP08290490.5 2008-05-28
PCT/EP2008/005107 WO2009007003A1 (en) 2007-07-11 2008-06-24 Method for recycling a substrate, laminated water fabricating method and suitable recycled donor substrate

Publications (2)

Publication Number Publication Date
CN101689530A CN101689530A (zh) 2010-03-31
CN101689530B true CN101689530B (zh) 2013-05-22

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CN2008800213829A Active CN101689530B (zh) 2007-07-11 2008-06-24 再生基片的方法、层积晶片制造法和适宜的再生供体基片

Country Status (7)

Country Link
US (1) US8324075B2 (enExample)
EP (2) EP2015354A1 (enExample)
JP (1) JP5099859B2 (enExample)
KR (1) KR101487371B1 (enExample)
CN (1) CN101689530B (enExample)
AT (1) ATE504083T1 (enExample)
DE (1) DE602008005817D1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8871109B2 (en) 2009-04-28 2014-10-28 Gtat Corporation Method for preparing a donor surface for reuse
FR2999801B1 (fr) * 2012-12-14 2014-12-26 Soitec Silicon On Insulator Procede de fabrication d'une structure
US20140268273A1 (en) * 2013-03-15 2014-09-18 Pixtronix, Inc. Integrated elevated aperture layer and display apparatus
US8946054B2 (en) 2013-04-19 2015-02-03 International Business Machines Corporation Crack control for substrate separation
WO2015084868A1 (en) 2013-12-02 2015-06-11 The Regents Of The University Of Michigan Fabrication of thin-film electronic devices with non-destructive wafer reuse
CN104119815B (zh) * 2014-08-04 2015-08-19 博洛尼家居用品(北京)股份有限公司 一种双面胶带
FR3048548B1 (fr) * 2016-03-02 2018-03-02 Soitec Procede de determination d'une energie convenable d'implantation dans un substrat donneur et procede de fabrication d'une structure de type semi-conducteur sur isolant
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
FR3063176A1 (fr) * 2017-02-17 2018-08-24 Soitec Masquage d'une zone au bord d'un substrat donneur lors d'une etape d'implantation ionique
FR3074608B1 (fr) 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat
KR102287395B1 (ko) * 2019-02-28 2021-08-06 김용석 플렉시블 전자 소자의 제조방법 및 그로부터 제조된 플렉시블 전자 소자
KR102523640B1 (ko) 2022-01-28 2023-04-19 주식회사 이노와이어리스 이동통신 단말 시험용 실드 박스

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596610B1 (en) * 1999-11-29 2003-07-22 Shin-Etsu Handotai Co. Ltd. Method for reclaiming delaminated wafer and reclaimed delaminated wafer
CN1959952A (zh) * 2005-10-18 2007-05-09 S.O.I.Tec绝缘体上硅技术公司 再循环外延施予晶片的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
JP3932369B2 (ja) 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3472197B2 (ja) * 1999-06-08 2003-12-02 キヤノン株式会社 半導体基材及び太陽電池の製造方法
US6664169B1 (en) * 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
EP1158581B1 (en) * 1999-10-14 2016-04-27 Shin-Etsu Handotai Co., Ltd. Method for producing soi wafer
TWI233154B (en) 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
FR2852445B1 (fr) * 2003-03-14 2005-05-20 Soitec Silicon On Insulator Procede de realisation de substrats ou composants sur substrats avec transfert de couche utile, pour la microelectronique, l'optoelectronique ou l'optique
US7402520B2 (en) 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
FR2888400B1 (fr) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Procede de prelevement de couche
EP1777735A3 (fr) * 2005-10-18 2009-08-19 S.O.I.Tec Silicon on Insulator Technologies Procédé de recyclage d'une plaquette donneuse épitaxiée
JP4715470B2 (ja) * 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596610B1 (en) * 1999-11-29 2003-07-22 Shin-Etsu Handotai Co. Ltd. Method for reclaiming delaminated wafer and reclaimed delaminated wafer
CN1959952A (zh) * 2005-10-18 2007-05-09 S.O.I.Tec绝缘体上硅技术公司 再循环外延施予晶片的方法

Also Published As

Publication number Publication date
KR101487371B1 (ko) 2015-01-29
JP2010532928A (ja) 2010-10-14
CN101689530A (zh) 2010-03-31
EP2037495B1 (en) 2011-03-30
US20100181653A1 (en) 2010-07-22
EP2015354A1 (en) 2009-01-14
US8324075B2 (en) 2012-12-04
JP5099859B2 (ja) 2012-12-19
DE602008005817D1 (de) 2011-05-12
ATE504083T1 (de) 2011-04-15
KR20100044142A (ko) 2010-04-29
EP2037495A1 (en) 2009-03-18

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