CN101563773B - 用于将现有硅管芯结合到3d集成叠置体中的方法 - Google Patents

用于将现有硅管芯结合到3d集成叠置体中的方法 Download PDF

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CN101563773B
CN101563773B CN2007800470113A CN200780047011A CN101563773B CN 101563773 B CN101563773 B CN 101563773B CN 2007800470113 A CN2007800470113 A CN 2007800470113A CN 200780047011 A CN200780047011 A CN 200780047011A CN 101563773 B CN101563773 B CN 101563773B
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P·里德
B·布莱克
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Abstract

一种设备，包括第一管芯，第一管芯包括多个导电穿衬底通孔(TSV)；以及多个第二管芯，每个所述第二管芯包括多个耦合到所述第一管芯的TSV的触点，所述多个第二管芯被设置成总体上包括近似等于所述第一管芯的表面面积的表面面积。一种方法，包括在第一管芯上设置多个第二管芯，使得所述多个第二管芯总体上包括近似等于所述第一管芯的表面面积的表面面积；以及将多个第二器件电耦合到多个第一管芯。一种系统包括电子设备，该电子设备包括印刷电路板和模块，该模块包括第一管芯，该第一管芯包括多个TSV；以及设置所述多个第二管芯，以总体上包括近似等于第一管芯的表面面积的表面面积。

Description

用于将现有硅管芯结合到3D集成叠置体中的方法
技术领域
集成电路封装
背景技术
人们正在努力对芯片或管芯进行叠置以提高性能，而不会占据印刷电路板上的更多空间(例如更多表面面积)。这特别受到对复杂手机、智能电话和其它移动装置的需求的驱动。芯片制造商已经在相连集成电路结构或叠置体中组合了动态和静态随机存取存储器(DRAM和SRAM)、闪速存储器和其它存储器，但在历史上一直受到连接芯片的布线(例如引线键合)对空间的更大需求的制约。芯片或管芯叠置技术将两个或更多管芯键合到一起，以形成连接集成电路结构。可以利用沿着叠置体的侧面的互连布线或管芯间界面处的金属通孔将芯片或管芯连接在一起。
一种用于芯片或管芯叠置的通用方法被称为面对面键合。在这种配置中，例如，两个相应管芯的器件侧面被叠置，使其器件侧面彼此面对，且金属通孔电连接管芯间界面处的管芯。在面对面键合的相连集成电路结构的一种表示中，以面对面键合配置将中央处理单元(CPU)或逻辑管芯和存储器管芯(例如SRAM或DRAM管芯)叠置在一起。可以将热沉附着到CPU或逻辑管芯体上，并利用附着到存储器管芯体的凸块技术形成通往封装或电路板的电源和输入/输出(I/O)连接。可以使用穿硅通孔(TSV)来穿过存储器管芯并连接到金属管芯间界面。
在以上范例中，由于穿硅通孔穿过第二管芯(例如存储器管芯)的存储器的有源硅区域，因此必须在电路中分配足够大的区域来允许穿硅通孔通过。由于功率传输的需要，这些通孔通常可能大于(大于10倍的)给定工艺的最小设计规则。通过穿硅通孔供应用于两个管芯的功率。功率需求将要求每个凸块触点大约一个穿硅通孔。在倒装芯片封装中，通常在整个二维管芯上以宽间隔的均匀图案设置凸块，从而允许顶部金属层上存在大量均匀的电源和接地连接。这需要设计第二管芯(例如存储器管芯)中的电路，从而为这些通孔提供与相邻几何结构的适当间距。这意味着，需要对第二管芯进行定制设计，以严格匹配第一管芯的通孔要求。
另一种键合配置是面对背键合配置。以CPU管芯和存储器管芯为例，在面对背键合配置中，可以交换两个管芯的位置。例如，将利用标准凸块技术以典型方式将第一管芯(CPU管芯)信号和电源连接附着到封装。将利用穿硅通孔使第二管芯(例如存储器管芯)的电源和信号连接穿过第一管芯。存储器管芯的功率需求通常比CPU或逻辑管芯低得多，因此，需要穿过第一管芯(例如CPU管芯)的穿硅通孔数量少得多，且不需要在管芯上均匀间隔开。这使得CPU管芯的设计和布局受到第二管芯的三维键合的影响小得多。
附图说明
通过以下详细描述、所附权利要求和附图，各实施例的特征、方案和优点将变得更加透彻明白，附图中：
图1示出了相连集成电路结构的顶部分解图，该结构包括第一管芯和被设置成占据第一管芯的表面区域的多个单个化或未单个化的管芯。
图2示出了图1的结构的顶部侧视图，并示出了与每个第二管芯相关联的键合焊盘。
图3示出了取自线3-3’的侧视图。
图4示出了取自线3-3’的图2的结构，并示出了重新分布层，该重新分布层将第二管芯上的触点与第一管芯上的穿硅通孔电连接。
图5示出了第一管芯表面的实施例。
图6示出了相连集成电路结构的另一个实施例，该相连集成电路结构包括第一管芯和多个第二管芯。
图7示出了形成相连集成电路结构的方法的实施例的流程图。
图8示出了作为台式计算机的一部分的电子组件的示意性侧视图。
具体实施方式
图1-3示出了相连集成电路结构实施例的不同视图，该相连集成电路结构包括第一管芯110以及电连接在管芯110上的若干单个化或未单个化的第二管芯210。管芯110例如是CPU或逻辑管芯。在一个实施例中，管芯210(个体管芯210A、管芯210B、管芯210C和管芯210D的统称)为存储器管芯(例如SRAM、DRAM)或其它管芯或不同管芯(例如逻辑和存储器)的组合。由管芯210代表的多个管芯总体上具有近似等于或匹配第一管芯110的尺寸(表面面积)的管芯尺寸(表面面积)。典型地，作为CPU或逻辑管芯的管芯110可以具有例如400平方毫米(mm2)的表面面积。在该范例中，管芯210(管芯210A、管芯210B、管芯210C、管芯210D)中的每个管芯具有100mm2的表面面积，使得管芯210占据的总表面面积也是400mm2。在管芯210为诸如DRAM的存储器结构时，可以选择管芯，使得管芯总体上构成DRAM密度和管芯尺寸的可接受的匹配。对于密度而言，根据管芯数量为如图所示的四个的当前技术，DRAM管芯尺寸可以是一吉字节(Gb)。或者，对于较小容量的DRAM(例如512千字节(Kb)或256Kb)而言，管芯210的数量可以更大(例如，对于512Kb而言，八个管芯，每个管芯60mm2(480mm2))。
图1示出了管芯210的两个范例。在一个范例中，将管芯210(管芯210A、管芯210B、管芯210C和管芯210D)中的每一个单个化并组装成管芯110上的不同单元。或者，可以将多个管芯划线成单个单元并附着到管芯110。
管芯或晶片形式的存储器管芯(例如SRAM、DRAM)是容易获得的。在引线键合应用中普遍使用这些管芯。代表性地，这些管芯中的每个可以具有4-32个I/O以及电源键合焊盘。通常将这些键合焊盘设置成通过管芯中心的窄的一到两个键合焊盘宽的列。图2示出了管芯210(例如管芯210A、管芯210B、管芯210C和管芯210D)，其具有通过每个管芯中心的两个键合焊盘宽的键合焊盘列220(以鬼线示出，以表示键合焊盘位于所观察管芯的相对表面上)。
在一个实施例中，管芯110可以是多内核处理器。多内核处理器一般具有一个物理处理器中的多个完整执行内核，每个执行内核都在相同频率下运行。每个内核通常共享相同的封装。参考图1，管芯110可以是例如双内核处理器、四内核处理器(如图中所示)或更多内核处理器。
在一个实施例中，以面对背键合配置连接管芯110和管芯210。参考图3，管芯110具有形成于其中的若干穿硅通孔(TSV)130。穿硅通孔130包括穿过其的导电材料，例如铜，用于将封装310上的管芯110和/或触点320连接到管芯210(如图所示的管芯210C和管芯210D)上的触点(例如键合焊盘)。图3示出管芯110，其具有器件侧120，该器件侧120与封装310相邻，并利用延伸穿过管芯110(从器件侧延伸到背侧(表面125))的穿硅通孔130而耦合到封装310。可以将诸如铜等的导电材料的穿硅通孔作为用于制造管芯110的处理步骤的一部分加以形成。通过这种方式，可以对穿硅通孔130进行构图，以与第二管芯的接触焊盘220(参见图2)对准。图3示出了从电触点320(例如键合焊盘上的焊料凸块)延伸到第二管芯210C和210D的键合焊盘220的穿硅通孔130。可以通过设置管芯210，使得每个管芯的器件侧(键合焊盘侧)设置于管芯110的背侧上。图3还示出了连接到管芯210的背侧的热沉410。
在一些实施例中，与管芯110相关联的穿硅通孔将不与管芯210的触点(例如键合焊盘)对准。在这种情况下，可以在管芯110的背侧或管芯210的器件侧上对例如金属(例如铜)层的导电重新分布层进行构图。这种重新分布层可以充当管芯210的触点(例如键合焊盘)与穿硅通孔130之间的互连。图4示出了根据另一实施例的穿过线3-3’的图2的相连集成电路结构。在该范例中，管芯210C和管芯210D的触点220不与延伸在封装310和管芯110之间且穿过管芯110的穿硅通孔130对准。图4示出了在一个实施例中在管芯110的背侧上构图的例如导电材料的重新分布层150，该导电材料例如是铜。图5示出了具有穿过管芯110延伸到背侧表面的穿硅通孔130A和130B的管芯110的背侧表面。图5还示出了从每个穿硅通孔130A横向延伸的经构图的重新分布层150。在该范例中，穿硅通孔130B将与第二管芯210的触点对准。代表性地，重新分布层150可以是利用光刻技术所构图的诸如铜等的导电材料，其中，例如在管芯110的背侧表面上沉积铜材料，随后用掩模界定重新分布层150，并进行蚀刻以将重新分布层构图为从穿硅通孔130A横向延伸到期望位置以与第二管芯210C和210D的触点电接触的指状物。例如，可以通过例如穿硅通孔130B的焊料连接将重新分布层150连接到管芯210的触点。
在必要的情况下，间隔材料可以由(例如)电介质材料和管芯110或管芯210的表面上的重新分布层一起形成，以占据管芯之间的任何空隙。图4示出了与管芯110的表面上的重新分布层150一起形成的间隔材料160。
在参考图1-5的描述中，示出了四个管芯210，例如存储器管芯(例如DRAM或SRAM)，管芯中的每个具有类似的管芯尺寸。要认识到，在其它实施例中，可以将具有不同功能和不同尺寸的管芯彼此叠置。图6示出了例如CPU或逻辑管芯的管芯510的相连集成电路结构的俯视图。设置于管芯510的表面(例如背侧表面)上的是例如DRAM存储器的管芯610A和610B。管芯510的背侧上还有管芯尺寸(截面积)大于管芯610A或管芯610B的管芯620。管芯620例如是SRAM存储器。在该范例中，将管芯610A、管芯610B和管芯620描述为存储器管芯，但要认识到也可以使用其它形式的管芯，例如CPU或逻辑管芯。
图7示出了形成相连集成电路结构的方法的流程图。在本实施例中，将在诸如CPU或逻辑管芯的背侧表面的表面上组装存储器管芯。如上所述，要认识到管芯类型的选择可以变化。
参考图7，在本实施例中，一开始确定相连集成电路结构的存储器要求(方框710)。例如，对于相连集成电路结构而言，期望的存储器要求可以是一吉字节(Gb)的DRAM存储器。
确定了存储器要求之后，然后选择若干存储器管芯，使得多个管芯的表面面积总和大致等于CPU逻辑管芯的表面面积(例如背侧表面面积)(方框720)。例如，在CPU或逻辑管芯的表面面积为400mm2且可获得表面面积为100mm2的1Gb DRAM存储器芯片的情况下，四个DRAM存储器芯片(4×100mm2)近似等于CPU或逻辑管芯的表面面积。
选择存储器管芯之后，检验存储器管芯的触点(电源和I/O触点)，并将图案与CPU逻辑管芯的期望的穿硅通孔的图案相比较。此时，判断是否需要重新分布层(方框730)。如果不需要重新分布层，可以在CPU或逻辑管芯的背侧上对触点进行构图(方框740)。如果需要重新分布层，则在CPU或逻辑管芯的背侧表面上对重新分布层进行构图并为重新分布层建立触点(方框750)。
一旦在CPU管芯的表面(例如背侧表面)上建立了触点，就通过例如焊料连接将多个存储器管芯连接到CPU或逻辑管芯(方框760)。在将存储器管芯连接到CPU或逻辑管芯之后，可以将相连的管芯叠置体连接到包括延伸到存储器管芯的穿硅通孔的衬底封装(方框770)。然后可以施加组装封装衬底时通常使用的热沉并进行任何其它处理技术。
图8示出了包括相连集成电路结构的电子组件的侧视图，该相连集成电路结构可以物理和电连接到印刷线路板或印刷电路板(PCB)。该电子组件可以是电子系统的一部分，该电子系统例如是计算机(例如台式计算机、膝上型电脑、手持式计算机、服务器等)、无线通信装置(例如蜂窝电话、无绳电话、传呼机等)、计算机相关外围设备(例如打印机、扫描仪、监视器等)、娱乐装置(例如，电视、无线电设备、立体声系统、磁带和压缩盘播放器、录像机、MP3(运动图像专家组音频层3播放器等)等)。图8示出了封装是台式计算机的一部分。图8示出了包括物理和电连接到封装衬底810的相连集成电路结构805的电子组件800。封装衬底810可用于将管芯100连接到印刷电路板820，例如母板或其它电路板。
在前面的详细描述中，提到了其具体实施例。不过显然，可以在不脱离如下权利要求的更宽的精神和范围的情况下对其做出各种修改和变化。因此，说明书和附图应被视为例示性的而不是限制性的。

Claims (18)

1.一种集成电路设备，包括：
第一管芯，其包括多个导电穿衬底通孔，所述第一管芯包括表面面积，所述第一管芯包括第一器件侧和第一背侧，所述第一器件侧与封装相邻并耦合到所述封装；以及
多个第二管芯，每个所述第二管芯包括耦合到所述第一管芯的所述穿衬底通孔的多个触点，所述多个第二管芯被设置成总体上包括近似等于或匹配所述第一管芯的表面面积的表面面积，所述多个第二管芯中的每个都包括第二器件侧和第二背侧，所述第二器件侧与所述第一管芯的所述第一背侧相邻并耦合到所述第一管芯的所述第一背侧，
其中所述第一管芯包括多内核处理器，且配置所述多个第二管芯，使得所述多个第二管芯中的每个都设置于所述多内核处理器的相应内核上。
2.根据权利要求1所述的设备，其中以面对背的键合配置耦合所述第一管芯和所述多个第二管芯。
3.根据权利要求2所述的设备，其中所述第一管芯包括CPU或逻辑管芯。
4.根据权利要求3所述的设备，其中所述多个第二管芯包括存储器单元。
5.根据权利要求3所述的设备，其中所述多个第二管芯包括动态随机存取存储器单元。
6.根据权利要求1所述的设备，其中所述第一管芯还包括通过导电重新分布层耦合到所述穿衬底通孔的多个触点，且每个所述第二管芯的所述多个触点耦合到所述第一管芯的所述多个触点。
7.一种用于制造集成电路设备的方法，包括：
在封装上设置第一管芯，所述第一管芯包括第一器件侧和第一背侧，所述第一器件侧与所述封装相邻并耦合到所述封装；
在所述第一管芯上设置多个第二管芯，使得所述多个第二管芯总体上包括近似等于或匹配所述第一管芯的表面面积的表面面积；以及
将多个第二管芯电耦合到所述第一管芯的多个导电穿衬底通孔，所述多个第二管芯中的每个都包括第二器件侧和第二背侧，所述第二器件侧与所述第一管芯的所述第一背侧相邻并耦合到所述第一管芯的所述第一背侧，
其中所述第一管芯包括多内核处理器，所述多个第二管芯包括存储器单元且被配置成使得所述多个第二管芯中的每个都设置于所述多内核处理器的相应内核上。
8.根据权利要求7所述的方法，其中以面对背的键合配置耦合所述第一管芯和所述多个第二管芯。
9.根据权利要求8所述的方法，其中所述第一管芯包括CPU或逻辑管芯。
10.根据权利要求9所述的方法，其中所述多个第二管芯包括存储器单元。
11.根据权利要求9所述的方法，其中所述多个第二管芯包括动态随机存取存储器单元。
12.根据权利要求7所述的方法，其中所述第一管芯包括通过导电重新分布层耦合到所述穿衬底通孔的多个触点，且耦合所述多个第二管芯包括将所述多个第二管芯的触点耦合到所述第一管芯的多个触点。
13.一种集成电路系统，包括：
电子设备，其包括印刷电路板和耦合到所述印刷电路板的模块，所述模块包括：
第一管芯，其包括多个导电穿衬底通孔，所述第一管芯包括表面面积，所述第一管芯包括第一器件侧和第一背侧，所述第一器件侧与封装相邻并耦合到所述封装；以及
多个第二管芯，每个所述第二管芯包括耦合到所述第一管芯的所述穿衬底通孔的多个触点，所述多个第二管芯被设置成总体上包括近似等于或匹配所述第一管芯的表面面积的表面面积，所述多个第二管芯中的每个都包括第二器件侧和第二背侧，所述第二器件侧与所述第一管芯的所述第一背侧相邻并耦合到所述第一管芯的所述第一背侧，
其中所述第一管芯包括多内核处理器，且配置所述多个第二管芯，使得所述多个第二管芯中的每个都设置于所述多内核处理器的相应内核上。
14.根据权利要求13所述的系统，其中以面对背的键合配置耦合所述第一管芯和所述多个第二管芯。
15.根据权利要求14所述的系统，其中所述第一管芯包括CPU或逻辑管芯。
16.根据权利要求15所述的系统，其中所述多个第二管芯包括存储器单元。
17.根据权利要求15所述的系统，其中所述多个第二管芯包括动态随机存取存储器单元。
18.根据权利要求13所述的系统，其中所述第一管芯还包括通过导电重新分布层耦合到所述穿衬底通孔的多个触点，且每个所述第二管芯的所述多个触点耦合到所述第一管芯的所述多个触点。
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CN101563773A (zh) 2009-10-21
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BRPI0722059A2 (pt) 2014-04-01
RU2419179C2 (ru) 2011-05-20
US8110899B2 (en) 2012-02-07
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