CN101416297B - 用于减小场效应晶体管中的接触电阻的外延硅锗 - Google Patents

用于减小场效应晶体管中的接触电阻的外延硅锗 Download PDF

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CN101416297B
CN101416297B CN200780012220.4A CN200780012220A CN101416297B CN 101416297 B CN101416297 B CN 101416297B CN 200780012220 A CN200780012220 A CN 200780012220A CN 101416297 B CN101416297 B CN 101416297B
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channel transistor
groove
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L·什夫伦
J·T·卡瓦利罗斯
S·M·塞亚
C·E·韦伯
J·K·布拉斯克
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Abstract

描述了一种用凹陷部外延SiGe源区和漏区来选择性地减轻n沟道晶体管的沟道应力的方法。这可提高n沟道晶体管的电子迁移率，而不影响p沟道晶体管中的应变。SiGe在形成硅化物时提供较低的电阻。

Description

用于减小场效应晶体管中的接触电阻的外延硅锗
技术领域
本发明涉及场效应晶体管中的硅锗区域。
背景技术
在半导体器件中，通常在半导体区域上形成硅化物金属以减小电阻。在硅化物与半导体如硅之间的界面上，肖特基势垒是电阻的来源。这可通过降低带隙来减小，如在硅锗(SiGe)用作在其中形成硅化物(silicide)和自对准多晶硅化物(salicide)的材料时存在的带隙。在美国专利6949482中描述了SiGe源区和漏区以及硅化物金属镍(nickel silicide metal)的使用。该专利中的带隙图及相关文本描述了在SiGe上使用(特别是)硅化镍的优点。(参见图5、图6和图7及相关文本。)
已知，在单轴压缩应变从(例如)嵌入的SiGe源区和漏区直接施加于晶体管的沟道区时PMOS晶体管中的性能可得到改进。同样已知的是，将单轴拉伸应变施加于沟道时，可在NMOS晶体管中获得性能改善。在2005年12月29日提交的、转让给本申请受让人的“A Tensile Strained NMOS Transistor Using Group III-N Source/DrainRegions”的序号11/323688的申请中描述了这方面的内容。
附图说明
图1是其中形成了隔离沟槽的硅衬底上部的两段横截面正视图。
图2示出具有栅结构以及蚀刻到硅中的与栅结构相邻的凹陷部的图1的结构。
图3示出SiGe源区和漏区在凹陷部中生长后的图2的结构。
图4示出在遮蔽p沟道晶体管后n沟道晶体管的离子注入期间的图3的结构。
图5示出交替处理中的图3的结构，其中在遮蔽步骤之后，隔离沟槽中的部分材料被蚀刻。
图6示出在源区和漏区上形成硅化物后的图5的结构。
图7示出另一实施例，其中对于n沟道晶体管SiGe没有进入凹陷部。
具体实施方式
描述一种用于制造p沟道及n沟道晶体管的方法，其中使用硅锗(SiGe)源区和漏区，并且在这些区域形成硅化物。在以下描述中，阐明例如注入能级等大量具体细节，以达成对本发明的透彻了解。本领域的技术人员当明白，即使没有这些具体细节也可实施本发明。在其它情况下，没有详细描述众所周知的制造过程，以免不必要地影响对本发明的理解。
在图1中，示出单晶硅衬底的上部。示出衬底中标识为10a和10b的两个独立段。将要进行描述，在段10a，在区域15中形成n沟道晶体管。在衬底段10b，在区域16中制造p沟道晶体管。区域15由两个隔离沟槽11和12确定界限。类似地，区域16由两个隔离沟槽13和14确定界限。沟槽11-14是通过在衬底的上部区域进行蚀刻并用介质填充沟槽所形成的浅隔离沟槽。在一些情况下，在蚀刻了沟槽后，生长二氧化硅而在沟槽中形成介质衬垫。然后，这些沟槽可用例如沉积二氧化硅等材料来填充。
在图1中，四个沟槽11-14均只示出一半。将要进行论述，在下面描述的部分实施例中，蚀刻填充沟槽的材料。在一些情况下，在整个沟槽上蚀刻材料，而在其它情况下，在小于沟槽的整个宽度的范围进行蚀刻。附图所示的沟槽宽度不是按比例绘制的，例如就没有与栅结构成比例。为了方便起见，相对于栅结构而言，所图示的沟槽比实际集成电路中窄得多。
在衬底的区域15、16等区域形成栅结构。图2所示的所得到的每个栅结构包括将栅极20与衬底中的沟道区分隔开的栅介质21以及栅极20之上的硬掩模23。侧壁间隔22设在栅极20的两侧。在此没有描述例如n型和p型掺杂剂尖端注入(tip implant)以及侧壁间隔的形成等处理步骤。这些步骤是已知的现有技术。另外，所示的特定栅结构仅作为示例，并不是本发明之关键点。
在形成栅结构后，在n沟道及p沟道晶体管的源区和漏区的部位将凹陷部30蚀刻到硅衬底中。在图2中，凹陷部30大致从栅结构延伸到隔离沟槽。注意，各种情况下的凹陷部30略低于侧壁间隔而延伸，并由隔离沟槽确定界限。
现在，用外延生长来生长n沟道及p沟道晶体管的SiGe源区和漏区。源区和漏区可提升到高于衬底的原高度，如图所示。注意，这些区域直接邻接于隔离沟槽。
凹陷部中SiGe的生长引起n沟道及p沟道晶体管双方的压缩应变沟道区域。在p沟道晶体管的情况下，这种应变是有益的，因为它可改善晶体管中的空穴迁移率。然而，在n沟道晶体管的情况下，同样的应变会使电子迁移率变差。但是，一旦形成了硅化物或自对准多晶硅化物，则n沟道及p沟道晶体管双方都将获益于与SiGe关联的较低的硅化物势垒高度。
图4示出的过程，用以减轻n沟道晶体管的沟道区上的应变而在p沟道晶体管上留下应变。首先，在p沟道晶体管上形成可为光致抗蚀剂41的掩模(masking member)，覆盖这些晶体管的源区和漏区。然后，如图4所示，将离子40注入n沟道晶体管的SiGe源区和漏区，以造成充当SiGe内松弛位的位错缺陷。这减小沟道区上的应变，因而改进沟道区中的电子迁移率。离子轰击可以比较浅，因为n沟道晶体管的沟道区靠近硅表面(直接在栅绝缘体之下)，因此，不需要破坏凹陷部深处的晶体点阵。被注入的离子不是名义上的截流子，因此不影响源区和漏区的半导体属性。例如可使用碳。0.5-1.5Kev的注入能级是足够的，采用的剂量约为1E16-5E16原子/平方厘米。
在这种注入后，以一般方式例如用镍来形成硅化物。与p沟道晶体管的漏区和漏区相比，对n沟道源区和漏区的晶格破坏有助于硅化物的形成。
如图4所示，整个隔离沟槽13包含在掩模下，而只有一半隔离沟槽14处于掩模41下。这表明，掩模与隔离区的对齐对于此实施例不是关键点。重要的是，保护p沟道晶体管的SiGe源区和漏区不受注入。
在一个备选实施例中，通过去除隔离沟槽中的部分或全部材料，来减轻n沟道晶体管中的应力。参照图5，同样将掩模(掩模50)置于p沟道晶体管之上。限定n沟道晶体管的沟槽(如图5的沟槽11和12)至少部分地外露。然后，用各向同性或各向异性蚀刻工序从光路蚀刻掉沟槽中的材料，如二氧化硅。如图5的开口52和53所示，并不需要蚀刻掉沟槽底部的所有材料。只是沟道区中靠近表面的应变需要减轻。
在隔离沟槽将n沟道晶体管与p沟道晶体管分隔开的情况下，蚀刻沟槽的整个宽度可减轻p沟道及n沟道晶体管双方的应变。这将消除在p沟道晶体管中使用SiGe的益处之一，具体说就是由应变沟道导致的较高空穴迁移率。
在这种情况下，掩模应当防止整个沟槽被蚀刻。例如，图5的掩模51保护沟槽11中的材料的一部分。类似地，掩模50保护沟槽14的一部分。具体来说是在使用各向异性蚀刻剂时，掩模50和51分别防止填充沟槽14、11的所有材料被蚀刻掉。因此，如果p沟道晶体管设置在隔离区11的与图5所示的n沟道晶体管相对的一侧，则其沟道中的应变不会被减轻。类似地，开口55会减轻设置在沟槽14的与区域16相对一侧的n沟道晶体管的应变。在p沟道晶体管没有与n沟道晶体管共用隔离沟槽的情况下，或者在由于某种原因可蚀刻整个沟槽的情况下，掩模无需落到沟槽上。这种情况在图5中由沟槽12表示。
如图6所示，一旦应变已经从n沟道晶体管的沟道区减轻了应变，则可在SiGe表面形成硅化物57。随后，例如用层间介质(ILD)重新填充沟槽。沟槽的这种重新填充没有在沟道上建立应变。注意，在图6中，已经用介质58重新填充开口52和53。
在图7中，示出一个附加实施例。不对n沟道晶体管形成凹陷部，而是对硅进行掺杂，如衬底段10a上的n沟道晶体管的源区和漏区62所示。对于p沟道晶体管，对图7的实施例蚀刻例如图2所示的凹陷部。然后，外延生长SiGe，从而形成p沟道晶体管的区域60以及n沟道晶体管的区域63。区域63高于沟道区的高度，因此没有在n沟道晶体管的沟道区上引起应变。如其它实施例中的情况那样，同样在SiGe表面形成硅化物65。从而获得在其它实施例中得到的降低硅/硅化物电阻的优点。
因此，以上描述了用以减轻使用SiGe源/漏区的n沟道晶体管中的应变的各工序。这使得在p沟道及n沟道晶体管双方使用SiGe形成的硅化物的优势得以发挥。

Claims (12)

1.一种制造n沟道及p沟道晶体管的方法，包括：
在硅衬底中形成凹陷部，用于n沟道及p沟道晶体管的与栅结构相邻的源区和漏区；
在所述凹陷部中生长SiGe，以形成所述n沟道及p沟道晶体管的源区和漏区；以及
通过从设于所述n沟道晶体管的源区的一侧和漏区的一侧的隔离沟槽中蚀刻介质材料来减轻所述n沟道晶体管的沟道区中因所述SiGe的生长而导致的应变，但不影响所述p沟道晶体管的沟道区中的应变。
2.如权利要求1所述的方法，其中，不是所有沟槽中的所有介质均被蚀刻。
3.如权利要求1所述的方法，包括在所述源区和漏区上形成金属硅化物。
4.如权利要求3所述的方法，其中，所述金属硅化物包括镍。
5.一种形成n沟道晶体管的方法，包括：
在硅衬底中形成用介质材料填充的隔离沟槽；
在与所述隔离沟槽相邻的所述衬底中形成的凹陷部中生长SiGe外延源区和漏区；
从所述沟槽的至少一部分沟槽中蚀刻所述介质材料，以缓和所述SiGe源区和漏区中的应变；以及
在所述源区和漏区上形成金属硅化物。
6.如权利要求5所述的方法，其中，所述金属硅化物用镍形成。
7.如权利要求6所述的方法，其中，所述沟槽中的所述介质材料是二氧化硅。
8.如权利要求5所述的方法，包括：遮蔽所述沟槽中至少一个沟槽的一部分，使得在所述沟槽的外露部分被蚀刻时所述沟槽的被遮蔽部分不被蚀刻。
9.一种具有n沟道及p沟道晶体管的集成电路，包括：
应变引致装置，用于在所述n沟道及p沟道晶体管双方的源区和漏区中均引起应变；以及
应变减轻装置，用于防止所述n沟道晶体管的源区和漏区中的应变引起所述n沟道晶体管的沟道区上的应变，而不阻止所述p沟道晶体管的沟道区中的应变，所述应变减轻装置包括相对于设于所述p沟道晶体管的源区的一侧和漏区的一侧的隔离沟槽而凹陷的，设于所述n沟道晶体管的源区的一侧和漏区的一侧的隔离沟槽。
10.如权利要求9所述的集成电路，其中，所述应变引致装置是SiGe源区和漏区。
11.如权利要求9所述的集成电路，包括所述n沟道及p沟道晶体管的源区和漏区上的金属硅化物。
12.如权利要求10所述的集成电路，包括所述n沟道及p沟道晶体管的SiGe源区和漏区上的金属硅化物。
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