CN101371357A - 半导体部件的应力缓冲封装 - Google Patents

半导体部件的应力缓冲封装 Download PDF

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Publication number
CN101371357A
CN101371357A CNA2007800029879A CN200780002987A CN101371357A CN 101371357 A CN101371357 A CN 101371357A CN A2007800029879 A CNA2007800029879 A CN A2007800029879A CN 200780002987 A CN200780002987 A CN 200780002987A CN 101371357 A CN101371357 A CN 101371357A
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China
Prior art keywords
stress buffer
stress
pad
passivation layer
soldered ball
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CNA2007800029879A
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CN101371357B (zh
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亨德里克·P·胡切斯坦巴赫
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Koninklijke Philips NV
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Koninklijke Philips Electronics NV
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  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
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Abstract

本发明涉及半导体部件的应力缓冲封装，其中，应力缓冲装置包括各自独立的应力缓冲元件，相互之间不影响应力缓冲效果。此外，本发明还涉及半导体部件的应力缓冲封装的制造方法。

Description

半导体部件的应力缓冲封装
技术领域
本发明涉及根据权利要求1前序部分所述的半导体部件的应力缓冲封装。这里关心的是所谓芯片级封装。电子元件，例如可包括二极管、晶体管、MEMS(微机电元件)或电容，通过焊球而不用附加载体被固定在诸如如印制电路板之类的基底上。芯片级封装特别用于所谓的功率晶体管和ESD(静电放电)二极管，通常与包括电阻器、电容器和/或线圈的无源滤波器组合在一起。芯片级封装还特别用于FM(调频)无线电方面。这是一种带有放大器和调谐器以及可能要求的任何其他电路的半导体，能够全面地执行移动电话的无线电功能。部分地因为在移动电话中可利用的空间小，所以在这种情况下，封装的尺寸是本质要素。
通常，芯片级封装的焊球直接安装在配置有与焊球相对应的电极的母板或印刷电路板上。焊球被焊接在板上以获得电子器件。在所述焊接期间和器件使用期间将产生应力，其原因是板材与例如半导体的硅之间热膨胀的差异。所述应力尤其产生在焊球以及焊球与下面结构之间的交界面上。如果不采取措施，将导致电子器件的可靠性程度不足，特别是热循环和下落测试期间。这就引出前面所描述的应力缓冲封装措施，其中用于吸收应力的应力缓冲装置设置在I/O焊盘与焊球之间。
背景技术
US专利文档US2004/0082101讨论了利用隔离应力吸收树脂层的芯片级封装。相关的封装10如图1所示。应力吸收树脂层12由诸如环氧树脂或聚酰亚胺树脂之类的热硬化树脂制成，弹性模量为0.01-8GPa，因此相对柔韧。在已经将树脂层涂敷到钝化层14上之后，蚀刻一些孔以便暴露所谓的I/O焊盘。然后用柔韧的导电层18填充这些孔。导电层包括铜、铅、锡、镍、钯、银或金中的至少一种粉状材料。最后，将焊球20放置在导电层18上。应力吸收层12和导电层18共同形成应力缓冲装置22。层12由热膨胀系数为40-600ppm/k的弹性材料制成。对于US2004/0082101中所示的所有实施例，得到的是不间断的应力缓冲装置22，至少从热机械的观点来看是这样。由于应力吸收层12和导电层18两者都是柔韧的，所以在一个焊球中产生的应力可以经由应力缓冲装置22传递至相邻的焊球。
US2004/0082101中所讨论的方法包括许多困难和花费大的步骤，例如光刻、刻蚀、等离子表面处理、丝网印刷等等。此外，导电层18包含的材料在制造半导体特别是晶片制作的时候也出现一些问题。材料例如铜或金的使用可能导致硅中的电子电路受到影响。
另一已知的解决办法表示在图2中，该图示出封装30，其中聚酰亚胺应力吸收层设置在钝化层34的顶部上面。在层32中形成开口，该开口从投影上看至少部分地与钝化层中的开口相符。锡球下层金属36(UBM：Under Bump metallization)一部分出现在应力吸收层32上面，一部分则在开口中(为的是与I/O焊盘40接触)。因此，UBM具有倒过来的牛仔帽的形状。UBM未完全填满钝化层和缓冲层的开口，从而形成有凹穴。因此，焊球38部分地呈现在所述凹穴中。在这一解决办法中，包括应力吸收层32和UBM层的应力缓冲装置也是热变形不间断的。事实是与应力吸收层和焊球的材料相比较，UBM层无疑是硬层，这个硬层通常包含镍，并且将通过周围的聚酰亚胺层把所产生的应力传递至相邻的UBM结构。
在所谓热循环期间，存在加热和冷却的变动状态。这一点在例如专利文档GB2135525和EP0064854中做了讨论。BGA封装也是众所周知的。一般已知的事实是热循环的最大问题通常出现在离封装中心(即半导体的中心称为中性点)最远的焊球上。最后，在热循环中板的膨胀大于半导体。因此，在加热时相对于半导体的中心而言，半导体的左边被拉向左，半导体的右边被拉向右。半导体与板之间的动程差在半导体的边缘比中心某些地方大许多。
发明内容
本发明的目的是提供一种包含应力缓冲器的半导体的可靠封装。
通过提供一种封装达到这一目的，其特征在于：应力缓冲装置包括各自独立的应力缓冲元件，其中每个应力缓冲元件基本上吸收包括至少一个焊球的组中形成的应力，使得应力缓冲元件的应力吸收不影响其他应力缓冲元件的应力缓冲效果。
构成本发明基础的主要理念是通过将应力缓冲装置分解为更小的独立元件，特别是为每个焊球提供单独的应力缓冲元件来提高可靠性程度。每个应力缓冲元件吸收在焊球和下面的结构中因电子元件与有关板之间的热膨胀的差异而产生的应力中的至少一大部分，以防止封装中电子连接的过早破裂和功能障碍。
只有应力缓冲元件不相连接，才能得到这种改善的可靠性，这种连接是提供提供钝化层所影响的。这意味着其中优选地，应力缓冲元件的上面和侧面(至少侧面的一部分)不具有与钝化层的界面。
分立的(从热变形的观点来看)应力缓冲元件提供至少两个现有技术未提供的应力释放和变形的附加机构。
如上所述，半导体与板之间移动的差异在半导体的边缘比中心某些位置大。因此一个焊球的应力值大于另一焊球。当应力缓冲装置不分解并且热变形不间断时，可以想象一个焊球速产生的应力被传递至相邻的焊球，在这种情况是应力在不可预测的位置上累积，以致局部形成破裂。这可能产生在例如焊球与相关连接结构之间的界面处。产生在邻近的焊球中的应力可传递至例如处于它们之间的焊球，通过这种方式所述应力将彼此加强。根据本发明的解决办法能防止这样的应力集中的出现。
应力缓冲元件和焊球的组合可视为两个串联的弹簧。所述弹簧本身能依照特定的热循环状态进行最佳的调整，因此提供了第二个有利的机制。所述调节对于从衬底至半导体的每一连接，即对于焊球与应力缓冲元件的每一组合可以不同。
应力缓冲元件的热变形与邻近的应力缓冲元件无关的这个事实本身，就提供了有别于现有技术的根据本发明的解决办法。
还有一个相关的方面是，根据本发明的结构看起来不适于与应力缓冲装置中的重新分布组合使用。这种重新分布轨迹会与钝化层相连，并和与衬底的连接相组合，因此导致重新分布轨迹与接纳焊球的凸起焊盘之间的连接失败。
本发明还涉及根据权利要求6的用于半导体部件的应力缓冲封装，和根据权利要求7的适合于放置焊球的半导体部件的应力缓冲封装。此外，本发明涉及组件，其包括衬底和应力缓冲封装、应力缓冲元件、含有应力缓冲封装的音频电路以及制造半导体部件的应力缓冲封装的方法。
如已陈述过的，如果对每一I/O焊盘提供单独的热变形隔离的应力缓冲元件是有利的。但不排除一个应力缓冲元件用于包含几个彼此相邻地排列的几个焊球的组，或者通过另外的连接层互连多个焊球的应力缓冲元件。这尤其通行于处在半导体的中心线附近的焊球。此外，多个若干热变形还算简单的焊球的这种连接和安置，看起来又使以任何方式重新分布成为可能。
优选地，使用导电材料的应力缓冲元件，其中事实上是将焊球与I/O焊盘的电连接功能与吸收所产生的应力的功能结合起来。因为应力缓冲元件是单个的模型化元件，所以这不会出现任何短路的问题。
优选地，选择应力缓冲装置和焊球，使它们具有可比的弹性、塑性和热膨胀系数。关于杨氏模量，如果两者的模量为10-100GPa则是有利的，更有利的是20-80GPa，还要有利的是25-75GPa。对于塑性值获得的类似效果为：两者的有利值为20-250MPa塑性极限，如果这个值的范围小则更为有利。采用铝合金(E-模量为60Gpa、塑性极限为200MPa)的应力缓冲元件和所谓SAC焊料(具有E-模量为32GPa和塑性极限为20MPa的锡-银-铜焊料)的组合获得了良好的结果，它们两者都具有20-25ppm/k的热膨胀系数。
优选地，应力缓冲元件涂敷有用于焊料的结合材料，例如镍。优选地，镍具有足够厚度，特别是配合使用高-锡焊料如SAC时。事实是这种焊料倾向于慢慢地溶解Ni。一旦Ni层被完全消耗，焊球不再结合，连接寿命也就会终止。使用具有至少0.4μm厚度的Ni层获得了有利的结果，更优选的厚度为0.8μm，越厚越好。注意，在这个连接中，镍的刚性和弹性极限两者大大高于铝(合金)和焊料。例如镍的E-模量为161GPa。
所述Ni层通常掺杂有延缓剂，其阻碍镍的溶解。为此目的，可以在Ni中使用8％的钒。优选地，在NiAu电极的情况下添加5-10％的磷。结合材料需要的层厚取决于焊球的直径和焊料的特定类型，当然也取决于电子器件在使用期间被暴露于怎样的环境。
非常有利的是以这样的方式施加结合层，即不仅出现在每一应力缓冲元件的上面而且在它的侧面，至少在与下面钝化层没有界面的侧面部分。可看到的结果是焊料也能扩展到所述侧面。优选地，这会导致焊料与下层表面之间的收缩角与结合层只出现在应力缓冲元件的上面的情况不同。这一差别，更有利的收缩角很可能对横向即平行于衬底方向上的焊球的变形具有正面的影响。
然而应该理解的是，结合材料覆盖在整个应力缓冲装置上也使元件对腐蚀的抵抗力提高。腐蚀问题经常发生在特别是有Al的地方。用结合材料(因此也用焊料)获得的密封性，提供了在进一步装配期间，例如在清洗步骤以及使用期间，对表面暴露所面临的湿气和各种其他环境因素的极好的抵抗力。
将结合材料施加至上面和侧面两者的有利的方法是采用化学镀技术，如本领域的熟练技术人员本已知道的。另一方面，当以溅射技术施加Ni时，Ni只被施加在应力缓冲元件的上面。
很明显，当使用铝应力缓冲元件时，要保持最小和最大的厚度。当Al层太厚时，缓冲层将太软而会裂开。当太薄时，缓冲层将太硬同样会裂开。合适的范围是1-5μm的厚度。为了清楚起见，要说明的是这里所使用的术语“厚度”应理解为从钝化层的上面延伸的应力缓冲元件部分的厚度。本领域的熟练技术人员明白，所述最小和最大值依赖于所使用的材料。例如Al合金如Al-Mg通常比较硬，要求大得多的厚度。不排除应力缓冲元件包括几个子层，可能是不同的材料。
从所要求的膨胀或变形与至半导体中心线的距离之间的关系的观点来看，因此也是从应力负荷与至半导体中心线的距离之间的关系来看，增强的可靠性可通过使应力缓冲元件的刚度随至半导体中心线距离的减小而减小来进一步提高。当然，这个所谓芯片上变化只能在适当的限度内。这个变形可为具有大于7*7的较大矩阵和/或较大半导体表面的芯片级封装提供解决办法。
如在前面已指出过的，当使用导电的和热变形隔离的应力缓冲元件时，重新分布并非总是可能的。除了前面已经说过的解决办法以外，存在另一种可能，事实上甚至更为简单：如果所述应力缓冲元件不是在机械上与对面的衬底或板连接的话，可以利用应力缓冲元件来重新分布。这意味着这个重新分布部分的末端必须通过其中的开口回接至钝化层下面的金属化部分。
除了用于重新分布(互连)以外，例如这种可能性也适合于限定这种应力缓冲元件中的线圈。Al的厚度使这一层很适合于这个目的。
为完整起见还要注意到，使用镍的锡球下层金属造成焊球与应力缓冲元件之间的机械上硬性的平板。假定根据本发明的解决办法也是基于串联弹簧系统(因此，在这种情况下靠近半导体的弹簧能变形)起作用而没有这种硬板。
特别要注意的是，从WO2005/115679知道了焊接材料，它能与Al结合而不使用另外的结合层。当然，与本发明配合使用这一材料是有利的。如果结合层无论如何要使用的话，那么它的使用或许也是有利的，即提供附加的保护。
根据本发明的应力缓冲封装的重要优点是在钝化层下面的I/O焊盘可以具有小的直径，而不是按比例减小焊球的直径。这将在附图描述中做更详细的说明。与本解决办法相比较，如图2所示，每一I/O焊盘从120*120μm减至10*10μm似乎是可能的。因此这是一种系数大于10的减小。
此外，这种减小使有可能减小每单位半导体的表面积，因此能从单一晶片或批料得到更多的产品。还有，这种减小使得可以设计芯片级封装中焊球下面的有源元件。根据图2实施例的现有技术中使用的大I/O焊盘(在那里是必要的，特别是因为聚酰亚胺的弱结合性)，导致机械应力而或许不能与处于其下面的有源元件结合。I/O焊盘的减小(不与焊球的减小相组合)能使半导体的这个不能利用的部分减小。因此，这个解决办法很适合用于移动电话和其他便携产品。
注意，根据本发明的I/O焊盘直径也将会比US2004/0082101的图1所示的I/O焊盘小。为了通过导电层18获得板与半导体之间的连接合适的低电阻，穿过钝化层的开口直径应该是适当地大。事实是导电粉末最好提供在柔韧、不导电材料中，以便得到所期望的柔韧性，这增加了层18的总电阻。因此，总电阻将低于例如根据本发明的包含铝的应力缓冲元件的电阻。
附图说明
下面将参考附图对本发明进行详细的说明，其中：
图1和图2是根据现有技术的半导体封装截面的一部分的示意图；
图3是根据优选实施例的半导体封装截面的一部分的示意图。
具体实施方式
图1和2示出根据现有技术的封装，前面已进行过讨论。
图3示出半导体52的应力缓冲封装50，在它的上表面包括有多个I/O焊盘54。半导体还包括钝化层56，其保护半导体的有源区并暴露I/O焊盘。优选地，钝化层包括氧化硅。通常在钝化层56上施加硅氮化物的附加钝化层58。
焊球60的作用是将半导体52或另一电气元件电连至板62上配置有电极64的端部。I/O焊盘和焊球通过锡球下层金属70和应力缓冲元件74电连接。锡球下层金属70的外表面形成所谓结合焊盘66，这使得可以放置焊球。
每一应力缓冲元件74由设置在钝化层56和58的开口中的第一部分68，和从钝化层58的表面76延伸的第二部分72构成。第一部分68与上述I/O焊盘接触，而第二部分72通过锡球下层金属70与上述焊球60电连接。第一部分68在平行表面76的方向上的尺寸比第二部分72在相应方向上的尺寸小得多。这一点清楚地表示在图3中。这方面的主要优点是能够使用相对小的I/O焊盘，至少不需要适应焊球的直径。这种现象也称作再钝化。这是有利的，特别是因为I/O焊盘下面的区域一般不能用于有源电路或互连结构，因为I/O焊盘会受应力的影响。当I/O焊盘的尺寸减小时，半导体的更大部分能被有效地利用。
优选地，每一应力缓冲元件74只用一种材料或一种部件构成。然而，这也是可以想像的，用几层组成两部分68和72，就要每一层都适应所要求的特定性能。
焊球60形成与印刷电路板62的电极64的导电连接，以便由此形成电子器件。众所周知的事实是半导体52的硅的热膨胀系数远小于用作PCB(印制电路板)的材料的热膨胀系数。这导致在测试期间和使用期间封装的应力。从两个部件的尺度来看，与这种连接有关的图3中所示器件A和B的膨胀尤其有差别。此外，很明显，膨胀差别在半导体的边缘的焊球大于位于半导体中心的焊球。热应力的问题在后一焊球的情况下所起的作用要小得多。
根据本发明，前述应力被应力缓冲元件74中和。应力的较大部分将被应力缓冲器的部分72吸收。这意味着一个连接结构/焊球中的应力将不会传递给相邻的连接结构/焊球。这与图1的应力缓冲装置22和图2的应力缓冲装置36、32相反。从另一方面来说，连接结构18(图1)和36(图2)在这种情况下将会传递应力。因此，本发明提供许多重要的优点，如前面已描述过的。
如前面已说明的，图3所示的结构可模型化为一组串联弹簧，热膨胀的差别确定弹簧的伸展，层的材料和厚度确定弹簧的特性。在图3中，例如，与锡球下层金属70相对应的相对硬的弹簧是与两个相对软的弹簧相连，所述相对软的弹簧分别与铝的应力缓冲部分74和焊球60相对应。因此每个图只示出两个这样的弹簧组件，但是很明显，实际上(那里使用大批焊球)大批弹簧的组件将沿两个方向并排设置。本发明的特征是一个弹簧组件中的弹簧伸展和张力不影响另一弹簧系统的伸展(stretch)和拉紧(tension)。在图1和2所示的情况下，弹簧组件中的一个弹簧的相对大的伸展和拉紧，能贡献于提高邻近弹簧组件中的伸展和拉紧。
关于如图2所示的已知解决办法，要注意事实上锡球下层金属被固定于结合焊盘40和钝化层34，应力缓冲层32的相对变形只部分地确定锡球下层金属相对于半导体的变形和相对移动。毕竟锡球下层金属经由I/O焊盘固定于半导体，结果帽形锡球下层金属的相对移动和变形减小。
优选地，锡球下层金属70是镍并有厚度d1为0.5-5μm的范围。优选地，通过化学镀工艺涂敷镍。结果，应力缓冲器的部分72的侧面也被覆盖。这从考虑防止对应力缓冲器的腐蚀和考虑得到焊球60的接触角α的有利角度两方面看，都是有利的。
优选地，每一应力缓冲元件74由铝合金构成。实验表明，通过使用包含0.5％铜的铝合金并且应力缓冲器74的部分72的厚度d2为2.5μm，能获得好的结果。优选地，所述厚度d2的范围在1和5μm之间。
优选地，每个焊球配用一个单独的应力缓冲元件，在这种情况下，一个焊球或下面的连接结构中的应力不会传递给相邻的焊球和应力缓冲元件。但是如已指出过的，也可以想像使用与一组相邻的焊球热变形互连的应力缓冲元件，例如通过经提供在它们之间的连接层(图3未示)连接多个个相邻的应力缓冲元件74。从局部较低的热应力来看，这个系统尤其能用于处于半导体中心线附近的焊球。
另一优先选择是，应力缓冲元件74最适合在具有平滑表面的钝化层上起作用。如果不是这样，危险的应力集中可能在应力缓冲元件74的部分72与上钝化层58之间的界面上产生，会导致破坏。由于这个原因，使用所谓化学机械抛光(CMP)技术以获得平滑的钝化层58，也许与采用所谓玻璃旋涂(SOG)工艺的上钝化层喷涂相结合。
虽然焊球被用在电连接封装的实施例中，但是也能在封装中使用根据本发明的应力缓冲元件而它们不包含焊球，例如在更一般的封装中包含与引线架的导线连接。它的优点是用于提供应力缓冲装置的工艺过程可以用于工厂中几种类型的封装。

Claims (13)

1.一种半导体部件的应力缓冲封装，包括：
至少一个电元件；
与所述元件电连接的I/O焊盘；
钝化层，其保护所述电元件并且至少部分地暴露所述I/O焊盘，所述钝化层具有背对所述电元件的上侧面；
与I/O焊盘电连接的焊球；
吸收应力的应力缓冲装置，其设置在I/O焊盘和焊球之间；
其特征在于：所述应力缓冲装置包括各自独立的应力缓冲元件，其中每一应力缓冲元件吸收包含至少一个焊球的组中产生的应力，使得应力缓冲元件的应力吸收不影响其他应力缓冲元件的应力缓冲效果。
2.如权利要求1中所述的封装，其特征在于：每个应力缓冲元件对应于一个焊球。
3.如权利要求1或2中所述的封装，其特征在于：应力缓冲元件包含导电材料。
4.如权利要求3中所述的封装，其特征在于：应力缓冲元件主要包括铝。
5.如权利要求1中所述的封装，其特征在于：每一应力缓冲元件从钝化层的上侧面延伸。
6.一种半导体部件的应力缓冲封装，包括：
至少一个具有I/O焊盘的电元件；
钝化层，其保护所述电元件并且至少部分地暴露所述I/O焊盘，所述钝化层具有背对所述电元件的上侧面；
与I/O焊盘电连接的焊球；
吸收应力的应力缓冲装置，其设置在I/O焊盘和焊球之间；
其特征在于：应力缓冲装置包括各自独立的应力缓冲元件，其中每一应力缓冲元件包括：第一部分，其设置在钝化层的开口中，和第二部分，其从钝化层的上侧面延伸，其中第一部分沿由钝化层的上侧面限定的表面平行方向上的尺寸小于第二部分沿相应方向上的尺寸。
7.一种适合放置焊球的半导体部件的应力缓冲封装，包括：
至少一个具有I/O焊盘的电元件；
钝化层，其保护所述电元件并且至少部分地暴露所述I/O焊盘，所述钝化层具有背对所述电元件的上侧面；
放置焊球的结合焊盘，其中所述结合焊盘与I/O焊盘电连接；
吸收应力的应力缓冲装置，其设置在I/O焊盘和结合焊盘之间；
其特征在于：所述应力缓冲装置包括各自独立的应力缓冲元件，其中，当焊球定位在结合焊盘上时，所述应力缓冲元件吸收包含至少一个结合焊盘的组中产生的应力，使得一个应力缓冲元件的应力吸收不影响其他应力缓冲元件的应力缓冲效果。
8.一种组件，包括衬底和如权利要求1-6中任何一项所述的应力缓冲封装，所述组件通过焊球与衬底电连接。
9.一种音频电路，包括如权利要求1-6中任何一项所述的应力缓冲封装，其中所述至少一个电元件包括用于接收和放大音频信号的电路。
10.一种应力缓冲元件，用于如权利要求1所述的封装，其中从包含焊球的组中吸收应力的应力缓冲元件被设置在与所述电元件中心间隔开的位置上，间隔开的距离大于极限距离。
11.一种制造半导体部件的应力缓冲封装的方法，包括以下步骤：
提供至少一个包括I/O焊盘和钝化层的电元件，所述钝化层保护电元件并且至少部分地暴露I/O焊盘，所述该钝化层具有背对电元件的上侧面；
提供导电的应力缓冲元件，其中每一元件一方面延伸进入I/O焊盘上方所形成的钝化层的开口中，另一方面从钝化层的上侧面延伸。
12.如权利要求11所述的方法，其特征在于：在应力缓冲元件上施加结合层。
13.如权利要求12所述的方法，其特征在于：所述结合层施加至所述应力缓冲元件的每一自由侧面。
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