DE602007013181D1 - Spannungspufferungsgehäuse für ein halbleiterbauelement - Google Patents

Spannungspufferungsgehäuse für ein halbleiterbauelement

Info

Publication number
DE602007013181D1
DE602007013181D1 DE602007013181T DE602007013181T DE602007013181D1 DE 602007013181 D1 DE602007013181 D1 DE 602007013181D1 DE 602007013181 T DE602007013181 T DE 602007013181T DE 602007013181 T DE602007013181 T DE 602007013181T DE 602007013181 D1 DE602007013181 D1 DE 602007013181D1
Authority
DE
Germany
Prior art keywords
semiconductor component
voltage buffer
stress buffering
buffer housing
relates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013181T
Other languages
English (en)
Inventor
Hendrik P Hochstenbach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37964096&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE602007013181(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by NXP BV filed Critical NXP BV
Publication of DE602007013181D1 publication Critical patent/DE602007013181D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Die Bonding (AREA)
DE602007013181T 2006-01-24 2007-01-18 Spannungspufferungsgehäuse für ein halbleiterbauelement Active DE602007013181D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06100793 2006-01-24
PCT/IB2007/050174 WO2007085988A1 (en) 2006-01-24 2007-01-18 Stress buffering package for a semiconductor component

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EP1979942A1 (de) 2008-10-15
TW200735302A (en) 2007-09-16
CN101371357B (zh) 2011-04-13
ATE502398T1 (de) 2011-04-15
US20100224987A1 (en) 2010-09-09
JP2009524922A (ja) 2009-07-02
CN101371357A (zh) 2009-02-18
US8338967B2 (en) 2012-12-25
EP1979942B1 (de) 2011-03-16
WO2007085988A1 (en) 2007-08-02

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