CN101315903B - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN101315903B CN101315903B CN200810108871XA CN200810108871A CN101315903B CN 101315903 B CN101315903 B CN 101315903B CN 200810108871X A CN200810108871X A CN 200810108871XA CN 200810108871 A CN200810108871 A CN 200810108871A CN 101315903 B CN101315903 B CN 101315903B
- Authority
- CN
- China
- Prior art keywords
- film
- mentioned
- mask
- pattern
- pattern openings
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 58
- 125000006850 spacer group Chemical group 0.000 claims description 49
- 238000005530 etching Methods 0.000 claims description 25
- 239000012528 membrane Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 33
- 238000001020 plasma etching Methods 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 7
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000035807 sensation Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007147108A JP4551913B2 (ja) | 2007-06-01 | 2007-06-01 | 半導体装置の製造方法 |
JP147108/2007 | 2007-06-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101315903A CN101315903A (zh) | 2008-12-03 |
CN101315903B true CN101315903B (zh) | 2010-12-08 |
Family
ID=40088793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200810108871XA Expired - Fee Related CN101315903B (zh) | 2007-06-01 | 2008-05-29 | 半导体装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (4) | US8343874B2 (zh) |
JP (1) | JP4551913B2 (zh) |
KR (1) | KR100993405B1 (zh) |
CN (1) | CN101315903B (zh) |
TW (1) | TWI370516B (zh) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4811520B2 (ja) * | 2009-02-20 | 2011-11-09 | 住友金属鉱山株式会社 | 半導体装置用基板の製造方法、半導体装置の製造方法、半導体装置用基板及び半導体装置 |
KR20120091453A (ko) * | 2010-02-19 | 2012-08-17 | 도쿄엘렉트론가부시키가이샤 | 반도체 장치의 제조 방법 |
KR101828492B1 (ko) * | 2010-10-13 | 2018-03-29 | 삼성전자 주식회사 | 패턴 형성 방법, 레티클, 및 패턴 형성 프로그램이 기록된 기록 매체 |
US8895445B2 (en) * | 2010-12-13 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming via holes |
JP5738786B2 (ja) * | 2012-02-22 | 2015-06-24 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
CN103972054B (zh) * | 2013-01-24 | 2017-03-01 | 华邦电子股份有限公司 | 图案化工艺 |
US9184058B2 (en) * | 2013-12-23 | 2015-11-10 | Micron Technology, Inc. | Methods of forming patterns by using a brush layer and masks |
US9368349B2 (en) | 2014-01-14 | 2016-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut last self-aligned litho-etch patterning |
US9425049B2 (en) | 2014-01-14 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut first self-aligned litho-etch patterning |
JP6289996B2 (ja) * | 2014-05-14 | 2018-03-07 | 東京エレクトロン株式会社 | 被エッチング層をエッチングする方法 |
US9406511B2 (en) | 2014-07-10 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned double patterning |
US10175575B2 (en) | 2016-06-01 | 2019-01-08 | Jsr Corporation | Pattern-forming method and composition |
US10274817B2 (en) * | 2017-03-31 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mask and photolithography system |
CN107164726B (zh) * | 2017-07-13 | 2019-07-09 | 京东方科技集团股份有限公司 | 一种oled蒸镀用掩膜板及制备方法 |
CN109390285B (zh) | 2017-08-08 | 2021-02-12 | 联华电子股份有限公司 | 接触结构及其制作方法 |
CN111902934A (zh) * | 2019-03-06 | 2020-11-06 | 深圳市汇顶科技股份有限公司 | 半导体结构及其制作方法 |
JP2021048372A (ja) | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | 半導体記憶装置及び半導体記憶装置の製造方法 |
US20210265166A1 (en) * | 2020-02-20 | 2021-08-26 | International Business Machines Corporation | Via-via spacing reduction without additional cut mask |
JP2023528134A (ja) * | 2020-04-23 | 2023-07-04 | エルジー イノテック カンパニー リミテッド | Oled画素蒸着のための金属材質の蒸着用マスク及び蒸着用マスクの製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1385889A (zh) * | 2001-05-14 | 2002-12-18 | 世界先进积体电路股份有限公司 | 下埋式微细金属连线的制造方法 |
CN1897246A (zh) * | 2005-03-02 | 2007-01-17 | 恩益禧电子股份有限公司 | 制造半导体器件的方法 |
CN1933109A (zh) * | 2005-09-14 | 2007-03-21 | 海力士半导体有限公司 | 在半导体器件中形成微图案的方法 |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0514850B1 (en) * | 1991-05-20 | 1996-08-21 | Matsushita Electronics Corporation | Method for producing a MIS type semiconductor device |
JP2787646B2 (ja) * | 1992-11-27 | 1998-08-20 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPH0831575B2 (ja) * | 1993-02-12 | 1996-03-27 | 日本電気株式会社 | 半導体記憶装置 |
JPH07245343A (ja) * | 1994-03-03 | 1995-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3859764B2 (ja) * | 1995-06-27 | 2006-12-20 | 株式会社ルネサステクノロジ | 重ね合わせ精度測定マーク、そのマークの欠陥修正方法、および、そのマークを有するフォトマスク |
JP4086926B2 (ja) * | 1997-01-29 | 2008-05-14 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6107119A (en) * | 1998-07-06 | 2000-08-22 | Micron Technology, Inc. | Method for fabricating semiconductor components |
JP3819711B2 (ja) * | 1998-10-23 | 2006-09-13 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP3367460B2 (ja) * | 1999-04-09 | 2003-01-14 | 日本電気株式会社 | 半導体装置の製造方法およびこれに用いるフォトマスク |
JP2002151665A (ja) * | 2000-11-14 | 2002-05-24 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6753954B2 (en) * | 2000-12-06 | 2004-06-22 | Asml Masktools B.V. | Method and apparatus for detecting aberrations in a projection lens utilized for projection optics |
JP4410951B2 (ja) * | 2001-02-27 | 2010-02-10 | Nec液晶テクノロジー株式会社 | パターン形成方法および液晶表示装置の製造方法 |
JP2002280463A (ja) * | 2001-03-16 | 2002-09-27 | Toshiba Corp | 半導体装置及びその製造方法 |
US6873720B2 (en) * | 2001-03-20 | 2005-03-29 | Synopsys, Inc. | System and method of providing mask defect printability analysis |
JP2003249572A (ja) * | 2001-12-19 | 2003-09-05 | Mitsubishi Electric Corp | 半導体装置の製造方法及び半導体装置 |
JP2003249437A (ja) * | 2002-02-26 | 2003-09-05 | Sony Corp | パターン形成方法および半導体装置の製造方法 |
DE10230532B4 (de) * | 2002-07-05 | 2007-03-08 | Infineon Technologies Ag | Verfahren zum Bestimmen des Aufbaus einer Maske zum Mikrostrukturieren von Halbleitersubstraten mittels Fotolithographie |
JP3895269B2 (ja) * | 2002-12-09 | 2007-03-22 | 富士通株式会社 | レジストパターンの形成方法並びに半導体装置及びその製造方法 |
KR100476690B1 (ko) | 2003-01-17 | 2005-03-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR100539272B1 (ko) * | 2003-02-24 | 2005-12-27 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US7056828B2 (en) * | 2003-03-31 | 2006-06-06 | Samsung Electronics Co., Ltd | Sidewall spacer structure for self-aligned contact and method for forming the same |
US20050088895A1 (en) * | 2003-07-25 | 2005-04-28 | Infineon Technologies Ag | DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM |
JP2005150222A (ja) * | 2003-11-12 | 2005-06-09 | Semiconductor Leading Edge Technologies Inc | パターン形成方法 |
JP4150660B2 (ja) * | 2003-12-16 | 2008-09-17 | 松下電器産業株式会社 | パターン形成方法 |
US7585731B2 (en) * | 2004-02-20 | 2009-09-08 | Renesas Technology Corp. | Semiconductor integrated circuit device and its manufacturing method |
US7755162B2 (en) * | 2004-05-06 | 2010-07-13 | Sidense Corp. | Anti-fuse memory cell |
US7266800B2 (en) * | 2004-06-04 | 2007-09-04 | Invarium, Inc. | Method and system for designing manufacturable patterns that account for the pattern- and position-dependent nature of patterning processes |
US7309653B2 (en) * | 2005-02-24 | 2007-12-18 | International Business Machines Corporation | Method of forming damascene filament wires and the structure so formed |
US20060202341A1 (en) * | 2005-03-10 | 2006-09-14 | Nec Electronics Corporation | Semiconductor device, and method of manufacturing the same |
JP2006276655A (ja) | 2005-03-30 | 2006-10-12 | Teijin Chem Ltd | プラスティックミラー用成形材料 |
JP4409524B2 (ja) | 2006-03-28 | 2010-02-03 | 富士通株式会社 | レジストパターン厚肉化材料、レジストパターンの製造方法、及び半導体装置の製造方法 |
US7605081B2 (en) | 2006-06-19 | 2009-10-20 | International Business Machines Corporation | Sub-lithographic feature patterning using self-aligned self-assembly polymers |
US7709367B2 (en) * | 2006-06-30 | 2010-05-04 | Hynix Semiconductor Inc. | Method for fabricating storage node contact in semiconductor device |
US7553760B2 (en) | 2006-10-19 | 2009-06-30 | International Business Machines Corporation | Sub-lithographic nano interconnect structures, and method for forming same |
GB0620955D0 (en) * | 2006-10-20 | 2006-11-29 | Speakman Stuart P | Methods and apparatus for the manufacture of microstructures |
US7700473B2 (en) * | 2007-04-09 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gated semiconductor device and method of fabricating same |
US7923801B2 (en) * | 2007-04-18 | 2011-04-12 | Invisage Technologies, Inc. | Materials, systems and methods for optoelectronic devices |
KR100946022B1 (ko) * | 2007-05-07 | 2010-03-09 | 주식회사 하이닉스반도체 | 반도체 소자의 패턴 형성 방법 |
JP5102653B2 (ja) * | 2008-02-29 | 2012-12-19 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置及びコンピュータ記憶媒体 |
US8512582B2 (en) * | 2008-09-15 | 2013-08-20 | Micron Technology, Inc. | Methods of patterning a substrate |
KR101095828B1 (ko) * | 2009-06-29 | 2011-12-16 | 주식회사 하이닉스반도체 | 반도체 소자의 형성 방법 |
US8492744B2 (en) * | 2009-10-29 | 2013-07-23 | The Board Of Trustees Of The University Of Illinois | Semiconducting microcavity and microchannel plasma devices |
US8547720B2 (en) * | 2010-06-08 | 2013-10-01 | Sandisk 3D Llc | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines |
US8829589B2 (en) * | 2010-09-17 | 2014-09-09 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory device |
-
2007
- 2007-06-01 JP JP2007147108A patent/JP4551913B2/ja not_active Expired - Fee Related
-
2008
- 2008-05-23 US US12/126,098 patent/US8343874B2/en active Active
- 2008-05-28 TW TW097119724A patent/TWI370516B/zh not_active IP Right Cessation
- 2008-05-29 CN CN200810108871XA patent/CN101315903B/zh not_active Expired - Fee Related
- 2008-05-30 KR KR1020080050971A patent/KR100993405B1/ko active IP Right Grant
-
2012
- 2012-08-23 US US13/593,063 patent/US8664120B2/en active Active
-
2014
- 2014-01-27 US US14/164,878 patent/US9142419B2/en active Active
-
2015
- 2015-08-21 US US14/831,981 patent/US9601343B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1385889A (zh) * | 2001-05-14 | 2002-12-18 | 世界先进积体电路股份有限公司 | 下埋式微细金属连线的制造方法 |
CN1897246A (zh) * | 2005-03-02 | 2007-01-17 | 恩益禧电子股份有限公司 | 制造半导体器件的方法 |
CN1933109A (zh) * | 2005-09-14 | 2007-03-21 | 海力士半导体有限公司 | 在半导体器件中形成微图案的方法 |
Non-Patent Citations (1)
Title |
---|
JP特开2003-249437A 2003.09.05 |
Also Published As
Publication number | Publication date |
---|---|
US20150357194A1 (en) | 2015-12-10 |
US9601343B2 (en) | 2017-03-21 |
JP4551913B2 (ja) | 2010-09-29 |
CN101315903A (zh) | 2008-12-03 |
KR100993405B1 (ko) | 2010-11-09 |
US9142419B2 (en) | 2015-09-22 |
US8664120B2 (en) | 2014-03-04 |
JP2008300740A (ja) | 2008-12-11 |
US20080299773A1 (en) | 2008-12-04 |
TW200913141A (en) | 2009-03-16 |
TWI370516B (en) | 2012-08-11 |
US8343874B2 (en) | 2013-01-01 |
US20140141617A1 (en) | 2014-05-22 |
US20120315766A1 (en) | 2012-12-13 |
KR20080106100A (ko) | 2008-12-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101315903B (zh) | 半导体装置的制造方法 | |
US11521857B2 (en) | Cut first self-aligned litho-etch patterning | |
US10840131B2 (en) | Patterning methods for semiconductor devices and structures resulting therefrom | |
US7830025B2 (en) | Contact layout structure | |
KR100759616B1 (ko) | 패턴 형성 방법 및 반도체 장치의 제조 방법 | |
US8808971B2 (en) | Method for forming fine patterns of semiconductor device | |
KR20060074876A (ko) | 반도체 장치 및 그 제조 방법 | |
KR101062514B1 (ko) | 패턴 형성 방법, 반도체 제조 장치 및 기억 매체 | |
KR100564578B1 (ko) | 비직교형 반도체 메모리 소자의 자기 정렬 콘택 패드형성방법 | |
US10795255B2 (en) | Method of forming layout definition of semiconductor device | |
US8236697B2 (en) | Method for manufacturing semiconductor device | |
JP2006228943A (ja) | 半導体装置および半導体装置の製造方法 | |
CN102522371B (zh) | 接触孔的制作方法 | |
US20030235790A1 (en) | Method for forming opening and application thereof | |
JP2008089817A (ja) | フォトマスク及びそれを用いた半導体素子の配線パターン形成方法 | |
KR20040099616A (ko) | 반도체소자의 레이아웃방법 | |
KR20120128517A (ko) | 반도체 소자의 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170810 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
|
TR01 | Transfer of patent right | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20211231 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 |