CN101233615A - 半导体元件和电气设备 - Google Patents

半导体元件和电气设备 Download PDF

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Publication number
CN101233615A
CN101233615A CNA2006800273996A CN200680027399A CN101233615A CN 101233615 A CN101233615 A CN 101233615A CN A2006800273996 A CNA2006800273996 A CN A2006800273996A CN 200680027399 A CN200680027399 A CN 200680027399A CN 101233615 A CN101233615 A CN 101233615A
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China
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semiconductor element
diode
schottky
electrode
mode
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CN101233615B (zh
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北畠真
楠本修
内田正雄
山下贤哉
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供一种半导体元件和一种电气设备。本发明的半导体元件(20)包括多个场效应晶体管(90)和肖特基电极(9a)，上述肖特基电极(9a)以沿着形成有上述多个场效应晶体管(90)的区域的外周的方式设置。

Description

半导体元件和电气设备
技术领域
本发明涉及半导体元件、尤其是对逆变电路等进行控制的半导体电力开关元件。
背景技术
作为通常的半导体电力开关元件，例如可列举IGBT(Insulated GateBipolar Transistor：绝缘栅双极晶体管)等。作为半导体电力开关元件的应用例，有用于电力电子控制的控制电路，例如可列举对三相电动机进行控制的逆变电路。
图8是表示该以往的逆变电路的概要的电路图。如图8所示，以往的逆变电路(在此为3相用)具有相数的量(在此为3个)的由开关功能部分(以下，称为上臂)23H和开关功能部分(以下，称为下臂)23L串联连接而成的电路(以下，称为相开关电路)23，上臂23H和下臂23L分别由相互并联连接的开关元件21与二极管22构成。开关元件21例如由使用硅的IGBT构成。并且，上臂23H与高电位配线25连接，下臂23L与接地电位配线24连接。各个臂23的中点26与作为负载的3相交流电动机的输入端子(以下，称为电动机输入端子)27连接。于是，通过对上臂23H与下臂23L的导通、断开的定时进行调整，能够控制中点26的电位。即，中点26进而输入端子27的电位，在下臂23L为导通、上臂23H为断开的情况下，与接地电位24相等。另一方面，中点26进而输入端子27的电位，在上臂23H为导通、下臂23L为断开的情况下，与高电位25相等。这样，通过将电动机输入端子27的电位切换为接地电位24和高电位25，能够对三相电动机28进行控制。
但是，开关元件21和二极管22的响应速度有限，因此，即使向开关元件21和二极管22提供从导通状态切换为断开状态的信号，也不能立刻变成断开状态。因此，当同时进行上臂23H和下臂23L的导通、断开的切换时，上臂23H和下臂23L有可能会同时变为导通状态。这样的状态是高电位25与接地电位24短路的状态，在逆变电路中会流过大电流。另外，因为该电流成为损失电流，所以开关损失增加，使电力利用效率下降。并且，因为在逆变电路中利用高速的开关进行高效率逆变控制，所以一次的开关损失会被累计开关次数次，整体的开关损失变大。因此，在以往，考虑开关元件21和二极管22的响应速度而决定开关的定时。换言之，逆变控制的频率根据开关元件21和二极管22的响应速度的制约而决定。但是，当要利用更高速的开关进行高效率逆变控制时，要求使开关元件21和二极管22的开关进一步高速化。
但是，在使用IGBT作为开关元件的情况下，因为该IGBT是双极器件，所以，少数载流子的寿命长，反向恢复需要时间，所以不能高速地进行由导通向断开的切换。因此，可考虑使用作为单极器件的MOSFET(金属-氧化物-半导体-场效应晶体管)作为开关元件。单极器件因为不受少数载流子的影响，所以能够高速地进行由导通向断开的切换。但是，由硅构成的MOSFET，每单位面积的导通电阻Ron(Ωcm2)大，由发热引起的导通损失增加。
另一方面，在使二极管的开关高速化的器件中，有实施了载流子的寿命控制的快恢复二极管。但是，快恢复二极管在几10kHz以上的高频下难以进行动作。另外，因为快恢复二极管是双极器件，所以，导通电阻由于少数载流子的扩散而变小，但是因为少数载流子的寿命长，所以从导通向断开的切换需要时间。另外，在使二极管的开关进一步高速化的器件中，有使肖特基电极与半导体进行肖特基接触的肖特基二极管。肖特基二极管是单极器件，不受少数载流子的影响，因此，能够高速地进行从导通向断开的切换。但是，在由硅构成的肖特基二极管的情况下，只耐压100V左右，在需要耐压600V以上的电力电子领域不能使用。
另外，因为由硅构成的IGBT和二极管被实施载流子的寿命控制，所以不能集成为一个芯片。
因此，已提出利用宽带隙半导体构成在逆变电路等中使用的开关元件和二极管。
例如，关于二极管，由宽带隙半导体构成的肖特基二极管，耐压有600V以上，与由硅构成的情况相比，导通电阻也足够小，并且，能够高速地进行从导通向断开的切换。
另一方面，关于开关元件，由宽带隙半导体构成的MOSFET与由硅构成的IGBT相比，每单位面积的导通电阻足够小，能够确保耐压，并且，能够高速地进行从导通向断开的切换。
但是，即使是SiC-MISFET，由于半导体装置内的由p型区域与n型区域的PN结构成的寄生二极管，有可能伴随有反偏压时的从寄生二极管的导通状态向SiC-MISFET的断开的切换的反向恢复时间的延迟。
例如，当在开关元件的断开时由电感负载产生的作为反电动势的正电压被施加到源电极上时，通过寄生二极管，作为少数载流子的空穴被注入到n型区域，导致二极管动作的反向恢复时间的延迟。
另一方面，利用宽带隙半导体构成纵型MOSFET，以与该纵型MOSFET的漂移区域进行肖特基接合的方式配设肖特基电极，由此，能够将肖特基二极管和作为开关元件的MOSFET集成为单芯片(参照专利义献1)。
专利文献1：日本特开2002-203967号公报
发明内容
但是，当使用上述以往的半导体元件作为构成具体的逆变电源电路(例如，空调压缩机等的3相电动机用的逆变电源电路)的开关元件时，这样的开关元件的实用化，明显存在以下的问题。
肖特基结的金属电极(肖特基电极)的配置面积不会对半导体元件的高速开关动作造成大的妨碍。但是，如果向MOSFET内存在的寄生二极管和肖特基二极管施加正向电压、并考虑在两者中流动电流的状况，从确保适当的通电能力的观点出发，肖特基电极的配置面积成为重要的应该考虑的内容。
实际上，当将专利文献1所记载的技术应用于3相电动机用的逆变电源电路时，发现：以基于开关元件断开时的电感负载的反电动势作为触发，集中在肖特基电极中的电流可能引起元件的破坏。
另外，专利文献1的图2所示的肖特基电极，在俯视时以包围场效应晶体管区域的方式配置成与细配线连接的正交格子状。因此，在半导体元件的制造过程中容易诱发细配线的断线，这可能成为半导体元件的制造成品率下降的主要原因。
本发明鉴于上述情况而做出，其目的是提供能够同时实现高速开关动作与能量损失降低、并且对基于由电气设备的电感负载等产生的反电动势的电流集中具有优异的耐性的半导体元件和电气设备。
本发明的发明人为了解决上述问题而专心研究，结果查明，原因之一是：因为配设有肖特基电极的区域的面积相对于半导体元件整体的面积所占的比例小，所以电流集中到肖特基电极，半导体元件被破坏。
另外，本发明的发明人发现：因电场集中在半导体元件端部，该端部被破坏也是原因之一。即，在纵型MOSFET中，当在断开状态下向漏电极与源电极之间施加电压时，该电压实质上被施加到漂移区域与包含与它连接的沟道区域的阱之间的p/n结的耗尽层上，该电场在p/n结处最大。另一方面，在专利文献1的结构中，半导体元件具有多个单元(cell)，在该多个单元中分别形成有场效应晶体管，这些场效应晶体管相互并联连接。在这样的结构中，在排列有上述单元的区域中，p/n结的电场大致均匀，但是在该区域的端部，p/n结的电场因电场集中而变大。因此，在半导体元件的端部，附加有例如台面结构、护环(场限环(field limiting ring)结构)等。当附加这样的结构时，能够抑制该部分的电场集中，结果，耐压提高。但是，在施加浪涌电压的情况下，半导体元件的端部的电场变大，有该端部被破坏的情况。
因此，本发明的半导体元件包括：多个场效应晶体管，该场效应晶体管具有由宽带隙半导体构成的半导体层、在该半导体层中以包含该半导体层的上面的方式形成的第一导电型的第一源极/漏极区域、在上述半导体层中以包含上述上面和上述第一源极/漏极区域的方式形成的第二导电型区域、在上述半导体层中以包含上述上面和上述第二导电型区域的方式形成的第一导电型的漂移区域、以至少与上述第一源极/漏极区域的上述上面接触的方式设置的第一源电极/漏电极、以隔着栅极绝缘膜至少与上述第二导电型区域的上述上面相对的方式设置的栅电极、和与上述漂移区域欧姆连接的第二源电极/漏电极；和在上述漂移区域的上述上面以与该上面形成肖特基结的方式设置的肖特基电极，上述肖特基电极以沿着形成有上述多个场效应晶体管的区域的外周的方式设置。
当形成这样的结构时，与场效应晶体管中存在的p/n势垒相比具有较小的能垒的肖特基结以沿着形成有多个场效应晶体管的区域的外周的方式存在，因此，当半导体元件被施加浪涌电压时，漏电流优先在肖特基结部分中流动，由此，浪涌电压被缓和，能够抑制半导体元件的端部(形成有多个场效应晶体管的区域的外周部)的破坏。另外，当将场效应晶体管的寄生二极管从导通切换为断开时，来自于场效应晶体管的寄生二极管的少数载流子被肖特基电极吸收，从而能够进行高速的开关。
上述源电极可以以与上述源极区域和第二导电型区域的上述上面接触的方式设置。
可以上述第一导电型为n型、上述第二导电型为p型。
可以上述半导体层在俯视时被假想的边界线分割成多个单元，上述漂移区域和漏电极以在上述多个单元中延伸的方式形成，上述多个单元由在其中形成有上述场效应晶体管的晶体管单元、和在其中形成有上述肖特基电极的二极管单元构成，多个上述晶体管单元在晶体管形成区域相互邻接而形成，以包围上述晶体管形成区域的方式形成有二极管形成区域，在该二极管形成区域形成有1个以上的上述二极管单元。
可以在上述半导体层的上面，以在俯视时位于上述二极管形成区域与上述半导体层的端部之间的方式形成有护环。
上述肖特基电极可以沿着形成有上述多个场效应晶体管的区域的外周排列在其整个周边。
上述半导体元件中，优选所有上述晶体管单元的俯视时的面积相对于上述半导体元件的俯视时的面积的比例为50％以上99％以下。
上述半导体元件中，优选上述肖特基电极的面积相对于上述半导体元件的俯视时的面积的比例为1％以上50％以下。
优选上述二极管单元的上述肖特基电极的面积比上述晶体管单元的上述第二导电型区域的俯视时的面积大。
另外，本发明能够作为构成交流驱动装置的逆变电源电路的半导体元件使用，例如，能够应用于上述半导体元件作为臂模块被插入的电气设备。
根据这样的电气设备，因为半导体元件的导通损失与电流乘以电压的值(电流×电压)对应，所以，与以往的PN结二极管的正向电压相比，能够将肖特基二极管的正向电压保持得较低。因此，在电气设备的逆变电源电路中作为臂模块被插入的半导体元件的导通损失，与采用PN结二极管的以往的半导体元件相比，得到改善。
另外，在电气设备的逆变电源电路中作为臂模块被插入的半导体元件的从导通状态向断开状态的切换速度变快，开关损失降低。
也可以构成为：基于由上述交流驱动装置内的电感负载产生的反电动势而向上述场效应晶体管的寄生二极管和上述肖特基二极管施加的电压，比上述肖特基二极管的正向的上升沿电压(导通电压)大、并且比上述寄生二极管的正向的上升沿电压小。
上述交流驱动装置的一个例子是由上述逆变电源电路驱动的交流电动机，利用该交流电动机，例如对空调机的压缩机进行驱动。
本发明的上述目的、其它目的、特征和优点，通过参照附图的以下的优选实施方式的详细说明将变得明显。
发明效果
根据本发明，能够得到能够同时实现高速开关动作与能量损失降低、并且对基于由电气设备的电感负载等产生的反电动势的电流集中具有优异的耐性、并且元件端部的破坏得到抑制的半导体元件和电气设备。
附图说明
图1是表示本发明的第一实施方式的半导体元件的结构的平面图。
图2是将图1的半导体元件的结构的一部分放大后的部分平面图。
图3是表示图1的半导体元件的截面视图的结构的部分截面图，是沿着图2所示的III-III线切断后的截面图。
图4是示意性地表示作为本发明的第二实施方式的半导体装置的臂模块的结构的平面图。
图5是表示本发明的第二实施方式的逆变电路的结构的电路图。
图6是表示本发明的第三实施方式的半导体元件的结构的平面图。
图7是将图6的半导体元件的结构的一部分放大的部分平面图。
图8是表示作为以往的半导体元件的应用例的三相电动机驱动用的逆变电路的概要的电路图。
图9是用于对假想的边界线进行说明的概略图，(a)是表示对假想的边界线进行确定的第一方法的图，(b)是表示对假想的边界线进行确定的第二方法的图，(c)是表示对假想的边界线进行确定的第三方法的图，(d)是表示对假想的边界线进行确定的第四方法的图。
符号说明
1漏电极
2半导体基板
3半导体层(SiC层)
3a漂移区域
4p型半导体区域(第二导电型区域)
4ap型半导体区域外周部
4bp型半导体区域中央部
5源极区域
6源电极
7栅极绝缘膜
8栅电极
9二极管形成区域
9a、9b肖特基电极
10晶体管形成区域
11护环(耐压部件)
12接合垫(bonding pad)
12S源极·肖特基用垫
12G栅极用垫
13S、13G导线
14半导体元件端部
15漏电极端子
16源电极端子
17栅电极端子
18封装树脂
20半导体元件
21开关元件
22二极管
23相开关电路
23H上臂
23L下臂
24接地电位配线(接地电位)
25高电位配线(高电位)
26臂的中点
27电动机输入端子
28三相电动机
50假想的边界线
50a、50c横边界线
50b、50d、50f纵边界线
50X X部分假想线
50Y Y部分假想线
51曲折线
70肖特基二极管
80二极管单元
90场效应晶体管(MOSFET)
100晶体管单元
200单元
201单元形成区域
具体实施方式
以下，参照附图，对本发明的实施方式进行说明。
(第一实施方式)
图1是表示本发明的第一实施方式的半导体元件的结构的平面图。图2是将图1的半导体元件的结构的一部分放大后的部分平面图。图3是表示图1的半导体元件的截面视图的结构的部分截面图，是沿着图2所示的III-III线切断后的截面图。
本实施方式的半导体元件，作为将场效应晶体管(以下，有时也称为MOSFET)与肖特基二极管并联连接的电路而发挥作用，由集成有构成这样的电路的多个场效应晶体管和多个肖特基二极管的1个IC芯片构成。本实施方式的半导体元件，例如，在三相电动机驱动用的逆变电路(参照图5)中被用作相开关电路23。集成的场效应晶体管的数目由期望的电流容量决定。
如图1和图2所示，本实施方式的半导体元件20具有单元形成区域201。在此，该单元形成区域201在俯视时为正方形。此外，单元形成区域201并不限于在俯视时为正方形的情况。该单元形成区域201被分割成在俯视时由格子状的假想的边界线50划分的多个单元200，换言之，被分割成由被划分成行列状的区域构成的多个单元200。各单元200在此是正方形。该多个单元200由形成有后述的场效应晶体管90的晶体管单元100、和配设有肖特基电极9a并形成有肖特基二极管70的二极管单元80构成。
在本实施方式的半导体元件20中，沿着单元形成区域201的外周以列状形成有二极管单元80。以下，将以列状形成有该二极管单元80的区域称为二极管形成区域9。二极管形成区域9在此被形成为矩形的环状，由1列的二极管单元80构成。当然，也可以由多列的二极管单元80构成。在单元形成区域201的除了二极管形成区域9以外的正方形区域中形成有晶体管单元100。以下，将形成有该晶体管单元100的区域称为晶体管形成区域10。换言之，以包围正方形的晶体管形成区域10的方式形成有正方形的环状的二极管形成区域9。在本实施方式中，二极管形成区域9由竖的一边各20个、横的一边各20个共计76个二极管单元80聚集而构成，但二极管单元80的数目并不限定于此。在单元形成区域201的外侧，在后述的半导体层3的表面以包围该单元形成区域201的方式形成有护环11。
接着，对假想的边界线50进行说明。图9是用于对假想的边界线进行说明的概略图，(a)是表示对假想的边界线进行确定的第一方法的图，(b)是表示对假想的边界线进行确定的第二方法的图，(c)是表示对假想的边界线进行确定的第三方法的图，(d)是表示对假想的边界线进行确定的第四方法的图。
在图1和图2中，用两点划线表示的假想的边界线50，用于使对权利要求和说明书的内容的说明容易，并不实际存在于将本发明具体化的制品中。假想的边界线50，在晶体管单元100彼此邻接的情况下，是从各晶体管单元100的中心等距离地向纵方向或横方向延伸的假想线，在二极管单元80彼此邻接的情况下，是从各二极管单元80的中心等距离地向纵方向或横方向延伸的假想线，在晶体管单元100与二极管单元80邻接的情况下，是从晶体管单元100的中心与二极管单元80的中心等距离地向纵方向或横方向延伸的假想线。假想的边界线50可根据场效应晶体管90和肖特基二极管70的形状而适当变更。
在此，作为场效应晶体管90和肖特基二极管70的实际的排列，如图9所示，可假定各种配置图案。因此，参照图9，说明对与各配置图案对应的假想的边界线50进行确定的方法。此外，在以下，将假想的边界线50分成横边界线50a和纵边界线50b进行说明。为了将说明简化，在图9中，将场效应晶体管90简记为元件“T”，将肖特基二极管70简记为元件“S”。另外，为了方便说明，将横边界线50a的延伸方向设为“X方向”，将纵边界线50b的延伸方向设为“Y方向”。另外，将在X方向上并列的元件S和元件T的排列设为行方向排列，将在Y方向上并列的元件S和元件T的排列设为列方向排列。
首先，参照图9(a)，对确定假想的边界线50的第一方法进行说明。
图9(a)举例说明呈3行2列的矩阵状配置的元件T和在形成有该元件T的区域的左侧的外周呈3行1列配置的元件S。这样的元件T和元件S的配置图案是与图1～图3所示的晶体管单元100和二极管单元80的配置同样的配置图案。另外，在图9(a)中，表示元件T和元件S被形成为正方形状的例子。这样，对于肖特基电极9a的形状，为了使说明容易，简化成正方形状进行记载。
但是，这样的元件T和元件S的形状和排列，只是用于对假想的边界线50的确定方法进行说明。因此，例如，元件T和元件S的具体形状不需要一定是正方形，只要其中心可适当确定，也可以是圆形、三角形、或者五角形以上的多角形。
但是，在元件T为正方形状、元件S为三角形状的情况那样元件T与元件S的形状非常不同的情况下，当要求出晶体管单元100或者二极管单元80的面积相对于半导体元件20整体的面积的比例时，有时需要根据适当的修正系数进行修正。
如图9(a)所示，在由3行和3列构成的各部位存在的元件T和元件S为正方形状，因此，这些元件的中心Pij(i＝1～3，j＝1～3)，作为正方形的对角线的交点而唯一确定。
在此，横边界线50a以与在列方向上相互邻接的一对元件S的各自的中心(P11和P21)等距离、并且与在列方向上相互邻接的一对元件T的各自的中心(例如P12和P22)等距离的方式形成。另外，横边界线50c以与在列方向上相互邻接的一对元件S的各自的中心(P21和P31)等距离、并且与在列方向上相互邻接的一对元件T的各自的中心(例如P22和P32)等距离的方式形成。
纵边界线50b以与在行方向上相互邻接的元件S和元件T的各自的中心(例如P11和P12)等距离的方式形成。另外，纵边界线50f以与在行方向上相互邻接的一对元件T的各自的中心(例如P12和P13)等距离的方式形成。
另外，图9(a)中的左端的列方向的假想线50d，分开与纵边界线50b和纵边界线50f的间隔相等的间隔而形成在纵边界线50b的左侧。
接着，参照图9(b)，对确定假想的边界线50的第二方法进行说明。
图9(b)举例说明将正方形的元件T和正方形的元件S配置成交错状(交错对准)的情况。元件S在配置有元件T的区域的左侧的区域形成。构成第二行的排列的元件T和元件S，相对于构成第一行和第三行的排列的元件T和元件S，向X方向偏移构成第一行和第三行的排列的元件T和元件S的间距的一半。因此，元件T和元件S的配置图案成为3行6列。由此，在由3行和6列构成的各部位中的一部分(例如，2行×3列的部位)中，没有配置元件T和元件S。
在由3行和6列构成的各部位的适当位置存在的元件T和元件S为正方形，因此，元件T和元件S的中心Pij(i＝1～3，j＝1～6，但是P12、P14、P16、P21、P23、P25、P32、P34、P36除外)，作为该正方形的对角线的交点而唯一确定。
横边界线50a(在图9(b)中，用细的两点划线进行图示)是以通过以下各点的方式在X方向延伸的假想线：连接在倾斜方向上相互邻接的第一行×第一列的元件S的中心P11和第二行×第二列的元件S的中心P22的曲折线51上的中点(图9(b)所示的黑圆点：以下相同)；连接在倾斜方向上相互邻接的第二行×第二列的元件S的中心P22和第一行×第三列的元件T的中心P13的曲折线51上的中点；连接在倾斜方向上相互邻接的第一行×第三列的元件T的中心P13和第二行×第四列的元件T的中心P24的曲折线51上的中点；连接在倾斜方向上相互邻接的第二行×第四列的元件T的中心P24和第一行×第五列的元件T的中心P15的曲折线51上的中点；和连接在倾斜方向上相互邻接的第一行×第五列的元件T的中心P15和第二行×第六列的元件T的中心P26的曲折线51上的中点。
纵边界线50b(在图9(b)中，用粗的两点划线进行图示)是由以下假想线构成的假想线：以与在行方向上相互邻接的元件S的中心P11和元件T的中心P13等距离的方式在Y方向延伸的Y部分假想线50Y；以与在行方向上相互邻接的元件S的中心P22和元件T的中心P24等距离的方式在Y方向延伸的Y部分假想线50Y；以与在行方向上相互邻接的元件S的中心P31和元件T的中心P33等距离的方式在Y方向延伸的Y部分假想线50Y；和将这3个Y部分假想线50Y的端部彼此连接并在X方向延伸的2个X部分假想线50X。
接着，参照图9(c)，对确定假想的边界线50的第三方法进行说明。
图9(c)举例说明在X方向配置有3个的长方形的元件T、和在配置有该元件T的区域的左侧的外周沿Y方向延伸的1个长方形的元件S。元件T和元件S形成为在Y方向不间断地连接的条纹状。
因为元件T和元件S是长方形，所以这些元件的中心Pij(i＝1，j＝1～4)作为该长方形的对角线的交点而唯一确定。
纵边界线50b是以与在行方向上相互邻接的元件S的中心P11和元件T的中心P12等距离的方式在Y方向延伸的假想线。另外，纵边界线50f是以与在行方向上相互邻接的元件T的各自的中心P12、P13等距离的方式在Y方向延伸的假想线。另外，图9(c)中的左端的列方向的假想线50d，分开与纵边界线50b和纵边界线50f的间隔相等的间隔而形成在纵边界线50b的左侧。
在图9(c)中，不存在在列方向上相互邻接的元件T和元件S。因此，作为横边界线50a，选择在Y方向上与在行方向上邻接排列的4个元件的各自的中心等距离的一对假想线。在此，作为该假想线的例子，表示出了通过元件T和元件S的两端面的一对横边界线50a。
接着，参照图9(d)，对确定假想的边界线50的第四方法进行说明。
图9(d)举例说明配置成矩阵状的正方形的元件T、和在配置有该元件T的区域的左侧的外周沿Y方向延伸的元件S。图9(d)所示的元件T和元件S的配置图案，除了元件S以在多个单元200中延伸的方式与横边界线50a交叉而形成这一点之外，与图9(a)所示的元件T和元件S的配置同样。因此，在此，省略对与元件S交叉的横边界线以外的假想的边界线50的说明。
如图9(d)所示，与元件S交叉的横边界线50a是以与在列方向上相互邻接的元件T的各自的中心(例如P11、P21)等距离的方式在行方向上延伸的假想线的延长线。另外，与元件S交叉的横边界线50c是以与在列方向上相互邻接的元件T的各自的中心(例如P21、P31)等距离的方式在行方向上延伸的假想线的延长线。
接着，对采用平面型的半导体元件20的结构详细地进行说明。
如图3所示，半导体元件20具有半导体基板2。该半导体基板2由SiC构成，被掺杂成n+型(高杂质浓度的n型)。在半导体基板2的下面，在整个面上形成有漏电极(第二源电极/漏电极)1。漏电极1由导电性材料、例如Ni、Al、Ti、Mo等金属构成。另外，在半导体基板2的上面，在整个面上形成有半导体层3。半导体基板2和半导体层3这样由碳化硅(SiC)构成，但是也可以由其它的宽带隙半导体构成。具体而言，能够使用GaN、AlN等IIIA族氮化物、金刚石等。在此，所谓宽带隙半导体，是指作为导带的下端与价带的上端的能量差的带隙能为2.0eV以上的半导体。该半导体层3和半导体基板2构成半导体元件20的半导体，该半导体被分割成上述的多个单元200。
在半导体层3的晶体管单元100中，以包含其上面的方式形成有n+型的源极区域(第一源极/漏极区域)5。源极区域5在俯视时被形成为矩形的环状，并且，以其中心与晶体管单元100的中心大致一致的方式形成。在半导体层3中，以包含其上面并且包含源极区域5的方式形成有p型半导体区域(第二导电型区域)4。具体而言，p型半导体区域4，在半导体层3中，以包含其上面的源极区域5的内侧部分和包围源极区域5的矩形的环状部分、并且到达比源极区域5的下端更深的位置的方式形成。半导体层3的源极区域5和p型半导体区域4以外的区域由n-型(低杂质浓度的n型)的漂移区域3a构成。因此，漏电极1通过n+型的半导体基板2与漂移区域3a欧姆连接。在晶体管单元100中，以覆盖半导体层3的上面的从源极区域5的中间到晶体管单元100的外周的部分的方式形成有栅极绝缘膜7。换言之，栅极绝缘膜7在源极区域5的外周部、p型半导体区域4的源极区域5与漂移区域3a之间的部分(以下，称为p型半导体区域外周部)4a、和漂移区域3a的位于p型半导体区域外周部4a附近的部分上形成。栅极绝缘膜7由氧化膜(SiO2)构成。以正好与栅极绝缘膜7重叠的方式在该栅极绝缘膜7上形成有栅电极8。因此，p型半导体区域外周部4a形成有沟道区域。栅电极8由导电性材料、例如Ni、Ti、Al、Mo等金属、多晶硅等构成。在晶体管单元100中，在半导体层3的上面的从源极区域5的中间到位于内侧的部分上形成有源电极(第一源电极/漏电极)6。换言之，源电极6在源极区域5的内周部和p型半导体区域4的位于源极区域5的内侧的部分(以下，称为p型半导体区域中央部)4b上形成。源电极6通过n+型的源极区域5和p型半导体区域4与半导体层3欧姆连接。源电极6由导电性材料、例如Ni、Ti、Al、Mo等金属构成。
另一方面，在半导体层3的二极管单元80中，以与二极管单元80的外周之间具有若干间隙的方式，在其上面的大致整个面上形成有肖特基电极9a。在二极管单元80中，半导体层3的全部区域由n-型的漂移区域3a构成，因此，肖特基电极9a与半导体层3肖特基接合。肖特基电极9a，为了防止因电场集中而引起的破坏，如图1和图2所示，优选将角部形成为带有圆角的形状。肖特基电极9a由导电性材料、例如Ni、Ti、Al、Mo等金属构成。
在此，肖特基电极9a的面积优选比p型半导体区域4的俯视时的面积大。这是因为：肖特基电极9a与漂移区域3a之间的肖特基势垒比p型半导体区域4与漂移区域3a之间的p/n结的势垒小，因此，当向半导体元件20施加浪涌电压时，该浪涌电压被肖特基电极9a缓和，因此，当形成这样的结构时，该效果变得更大。
根据以上的结构，在晶体管单元100中形成有1个n沟道型的纵型场效应晶体管90，在二极管单元80中形成有1个肖特基二极管70。另外，漂移区域3a、半导体基板2、和漏电极1以遍及所有的单元200的方式设置。另外，栅极绝缘层7和栅电极8以在邻接的晶体管单元100之间连续的方式形成，因此，在半导体层3的晶体管形成区域10的整个表面上，格子状的栅极绝缘层7和栅电极8分别存在1个，源电极6存在于该格子状的栅极绝缘层7的开口内。
如图1和图2所示，在半导体层3的上面，还形成有护环11。护环11，在单元形成区域201与半导体层3的端部(芯片的端部)14之间，在俯视时形成为矩形的环状并形成为2层。在此，护环11并不限定于在俯视时形成为矩形的环状，只要包围单元形成区域201的外周即可。另外，护环11并不限定于形成为2层，也可以形成为1层、3层等任何层。护环11由与漂移区域3a相反的导电型的p型半导体区域构成。
另外，以将形成有源电极6、栅电极8、和肖特基电极9a的半导体层3的表面覆盖的方式设置有层间绝缘膜(未图示)。在该层间绝缘膜的上面，作为接合垫，配设有源极·肖特基用垫12S(参照图4)和栅极用垫12G(参照图4)。各接合垫12S、12G由Al等金属构成。在此，源极·肖特基用垫12S具有边长为0.6mm以上的正方形的形状。此外，源极·肖特基用垫12S的形状并不限定于正方形。源极·肖特基用垫12S在俯视时的晶体管形成区域10中，配设有纵3×横3合计9个。源极·肖特基用垫12S与源电极6和肖特基电极9a电连接。另外，在俯视时的晶体管形成区域10的外周的端部，配设有1个栅极用垫12G。在层间绝缘膜上，以贯通该层间绝缘膜并分别与栅电极8、源电极6、和肖特基电极9a连接的方式设置有多个由导电体构成的插头(未图示)。另外，在层间绝缘膜的上面，配设有将各插头与对应的接合垫连接的配线(未图示)。因此，源极·肖特基用垫12S与源电极6通过对应的插头和配线(源极配线)连接，源极·肖特基用垫12S与肖特基电极9a通过对应的插头和配线(肖特基电极配线)连接，栅极用垫12G与栅电极8通过对应的插头和配线(栅极配线)连接。在本实施方式的半导体元件20中，源极·肖特基用垫12S配设有9个，但是源极·肖特基用垫12S的个数并不限定于此。源极·肖特基用垫12S的全体，并联连接有晶体管单元100的数目的场效应晶体管90，并且并联连接有二极管单元80的数目的肖特基电极9a。另外，在本实施方式的半导体元件20中，栅极用垫12G配设有1个，但是栅极用垫12G的个数并不限定于此。即，也能够配设多个栅极用垫12G。在该情况下，可以与上述源极·肖特基用垫12S的情况同样，以将多个栅极用垫12G架桥的方式用导线13G连接。
而且，在一个方向上并列的3个源极·肖特基用垫12S以通过导线13S(参照图4)架桥的方式连接。导线13S由Al、Au等金属构成。源极·肖特基用垫12S与导线13S，通过一边施加超声波一边将导线13S按压在源极·肖特基用垫12S上而连接。在本实施方式的半导体元件20中，使用直径0.3mm的导线作为导线13S，但是为了能够耐大电流，优选使用该直径以上的直径的导线。在本实施方式的半导体元件20中，使用了三根导线13S，但是导线13S的根数并不限定于此。
另外，为了进行接合，源极·肖特基用垫12S的一边的长度优选为导线13S的直径以上。在本实施方式中，使用0.3mm直径的导线作为导线13S，因此，只要使源极·肖特基用垫12S的一边的长度为0.3mm以上即可。在此，为了使接合容易，优选如本实施方式那样，使源极·肖特基用垫12S的一边的长度为0.6mm以上。此外，为了进一步使接合容易，更优选使源极·肖特基用垫12S的一边的长度为0.9mm以上。
另一方面，栅极用垫12G通过导线13G连接。在此，导线13G由Al、Au等金属构成。栅极用垫12G与导线13G，通过一边施加超声波一边将导线13G按压在栅极用垫12G上而连接。在本实施方式的半导体元件20中，使用直径0.3mm的导线作为连接源极·肖特基用垫12S的导线13S，但是因为在栅电极8中流过的电流并不那么大，所以，作为连接栅极用垫12G的导线13G，优选使用直径更细的导线。
接着，参照图1～图3，对以上那样构成的半导体元件20的制造方法进行说明。此外，因为制造方法本身由众所周知的工序构成，所以简单地进行说明。
但是，在此省略各制造工序中途的图示。因此，在对本制造方法进行说明时，为了方便，对于制造工序中途的各构成部分的参照符号，使用图1～图3所示的完成品的符号作为代替进行说明。
首先，准备以3×1018cm-3的氮浓度掺杂有氮的n+型的具有4H-SiC(0001)Si面的[11-20]方向8度斜切面半导体基板2。
接着，在将该半导体基板2洗净后，在上述斜切面上，利用CVD法形成浓度被调整为1.3×1016cm-3的掺杂氮的n-型的作为外延生长层的SiC层(半导体层)3，并将厚度调整为10μm。
然后，配置在SiC层3的表面的适当位置开口的掩模(未图示)，适当选择30～700keV范围内的多级的离子能量，以2×1014cm-2浓度的剂量，通过开口向SiC层3的表面注入铝离子。通过该离子注入，在SiC层3的表层，呈岛状形成深度0.8μm左右的p型半导体区域4。另外，护环11也同时形成。
此后，使用在p型半导体区域4的表面的适当位置开口的另一个掩模(未图示)，以30～180keV的能量、以1.4×1015cm-2浓度的剂量向p型半导体区域4注入氮离子，形成n+型的源极区域5。
接着，将该半导体基板2暴露于Ar气氛，保持在1700℃的温度，实施约1个小时的热处理，使上述离子注入区域活化。
接着，将该半导体基板2在氧化处理炉内保持在1100℃的温度，实施3个小时的湿氧化。通过该氧化处理，在SiC层3的整个表面上形成厚度40nm的硅氧化膜。
使用光刻技术和蚀刻技术，在该硅氧化膜上图案化形成源电极用的第一开口和肖特基电极用的第二开口。由此，该硅氧化膜成为栅极绝缘膜7。
然后，在第一开口内露出的SiC层3的表面，选择性地形成由Ni构成的电极，在该第一开口内形成的电极成为源电极6。
接着，在半导体基板2的背面，设置由Ni构成的漏电极1。
然后，将这些Ni层堆积后，实施适当的热处理，上述电极6、1与半导体之间欧姆连接。
另外，在上述第二开口内露出的SiC层3的表面，选择性地形成由Ni构成的电极，在该第二开口内形成的电极成为肖特基电极9a。
此后，在栅极绝缘膜7的表面形成由Al构成的栅电极8。
此后，在源电极6、栅电极8、和肖特基电极9a的表面形成层间绝缘膜，对该层间绝缘膜适当形成插头、配线、和接合垫12S、12G。
接着，利用导线13S、13G将接合垫12S、12G适当连接。
这样，得到本实施方式的半导体元件20。
接着，对将半导体元件20的场效应晶体管90形成为沟槽型的情况、与将其形成为平面型的情况的比较进行说明。
就场效应晶体管的结构而言，有在半导体层上呈平面状形成p层和n层的平面型、和做出又窄又深的槽并埋入栅电极和栅极绝缘膜的沟槽型。本实施方式的半导体元件20的场效应晶体管90，考虑以下所述的与肖特基二极管70的关联性等各种理由，采用平面型。
例如，在日本特表2005-501408号公报(以下，称为现有例)中，公开了将肖特基二极管与沟槽型的MOSFET一体化的结构。在该现有例中，在沟槽(挖的槽或孔)的底面，形成半导体与金属的肖特基结部分，构成肖特基二极管。上述现有例的沟槽部分本来是构成晶体管单位元件部分的间隙的部分，与晶体管单位元件(如本实施方式那样，根据假想的边界线50划分的四角形的多个单元200)不同。
与此相对，本实施方式的形成有肖特基二极管70的部分，占据根据假想的边界线50划分的四角形的多个单元200中的一部分单元200的大致整个范围。因此，本实施方式的形成有肖特基二极管70的部分，与上述现有例的在间隙(的沟槽部分)中埋入肖特基电极的结构完全不同。
如本实施方式的半导体元件20那样，平面型的MOSFET90与肖特基二极管70的组合，具有能够任意选择在根据假想的边界线50划分的四角形的多个单元200中设置MOSFET90还是设置肖特基二极管70的结构上的自由度，与现有例那样采用沟槽型的MOSFET的情况相比具有优越性。由于该结构上的自由度，能够对配置有MOSFET90和肖特基二极管70的部分相对于半导体元件20整体的面积比任意进行设定这个本发明的特征之一，初次被具体化。
另外，在现有例中，需要隔着栅极绝缘膜在沟槽的壁面上形成栅电极、进而利用层间绝缘膜确保绝缘并在其上形成肖特基电极。这样，当在沟槽壁面上形成多层绝缘膜和电极时，在被多层绝缘膜的部分覆盖的沟槽的底面部分，不能形成大面积的肖特基电极。因此，只有沟槽的底面的一部分作为肖特基二极管发挥作用。因此，肖特基二极管的形成面积被限制得较小。在像本实施方式的半导体元件20那样使MOSFET90为平面型的情况下，没有上述的面积上的限制。
另外，当如现有例那样在沟槽底面形成肖特基电极时，成为在与背面的漏电极接近的位置存在肖特基电极的结构，在肖特基电极中会产生电场集中，耐压性存在担心。另一方面，当采用平面型的MOSFET时，肖特基电极9a被形成在半导体层3的表面，并且与肖特基电极9a邻接的MOSFET90的P型半导体区域4被形成得较深，因此，在肖特基电极9a中不会产生电场集中，能确保耐压性。
如以上所述，当像本实施方式的半导体元件20那样采用平面型的MOSFET90时，能够对MOSFET90和肖特基二极管70相对于半导体元件20整体的面积比任意地进行设定。另外，平面型的MOSFET90既能够确保耐压性，形成工艺也简单，因此，与采用现有例所示的沟槽型的MOSFET的情况相比，效果较大。
此外，在上述说明中，对在肖特基电极9a的材料中使用镍(Ni)的例子进行了说明，但是肖特基电极9a的材料并不限定于此，如上所述，使用钛(Ti)、铝(Al)、钼(Mo)等时也同样。
接着，对以上那样构成的半导体元件20的作用效果进行说明。
本实施方式的半导体元件20作为具有600V的耐压的功率器件(3mm见方(3mm×3mm的四角形)、额定电流值20A)起作用。
在此，在本实施方式的半导体元件20中，源电极6与p型半导体区域中央部4b接触，p型半导体区域4的下方的n-型的漂移区域3a通过半导体基板2与漏电极1连接，因此，在源电极6与漏电极1之间存在由漂移区域3a和p型半导体区域4构成的寄生二极管。另外，在本实施方式的半导体元件20中，源电极6以与漂移区域3a形成肖特基结的方式设置，因此，在源电极6与漏电极1之间存在由肖特基电极9a和漂移区域3a构成的肖特基二极管70。
本实施方式的半导体元件20，在使用时在源电极6与漏电极1之间施加漏电极1相对于源电极6为高电位的电压。当在该状态下向栅电极8施加阈值以上的电压(对源电极6的电压)时，在位于栅电极8下方的p型半导体区域4的上层部中形成n沟道。于是，电子从源电极6经过源极区域、n沟道、漂移区域3a、和半导体基板2向漏电极1移动，由此，电流从漏电极1向源电极6流动。
另一方面，在负载为感应性的情况下，当利用负载的电感将场效应晶体管90从导通切换到断开时，在源电极6与漏电极1之间暂时被施加源电极6相对于漏电极1为高电位的电压。由此，二极管单元80的肖特基二极管70导通，电流从源电极6向漏电极1流动。另外，当源电电极6的正电压进一步上升时，场效应晶体管90的寄生二极管导通，漂移区域3a中被注入少数载流子(空穴)。但是，通过将肖特基电极9a的面积设计得足够大，能够使肖特基二极管70的导通电阻比寄生二极管的导通电阻小，由此，在该情况下，电流优先在肖特基二极管70中流动。结果，被注入到漂移区域3a中的少数载流子的数目减少。另外，此后，当在源电极6与漏电极1之间施加的电压成为源电极6相对于漏电极1为低电位的电压时，该被注入的少数载流子瞬时被肖特基电极9a吸收。因此，半导体元件20与现有例相比，能够高速地进行从导通向断开的切换。另外，因为能够使配设肖特基电极9a的区域的面积足够大，所以能够防止电流向肖特基电极9a集中，从而能够抑制半导体元件20的破坏。
另外，在本实施方式的半导体元件20中，二极管形成区域9以沿着晶体管形成区域10的外周的方式配设，因此，与场效应晶体管90的p型半导体区域4和漂移区域3a之间的p/n势垒相比具有较小的能垒的肖特基结以沿着晶体管形成区域10的外周的方式存在，当半导体元件20被施加浪涌电压时，漏电流优先在肖特基结部分中流动，由此，浪涌电压被缓和，能够抑制半导体元件20的端部(晶体管形成区域10的外周部)的破坏。
另外，关于浪涌电压，因为肖特基二极管70与寄生二极管(PN结二极管)成为并联连接的结构，所以，直到某程度的电流值(与正向电压Vf低的区域对应的电流值)为止，肖特基二极管70高速地流动电流，当成为更大的电流值(与正向电压Vf高的区域对应的电流值)时，寄生二极管会流动电流。因此，也能够防止因电流向肖特基二极管70集中而引起的破坏。
因此，本发明的半导体元件20对于浪涌电压和浪涌电流具有高的耐性。
另外，当寄生二极管导通时，即使少数载流子分别被注入到p型半导体区域4、源极区域5中，当施加反偏压时，少数载流子会被吸入到肖特基电极9a 中，能够迅速地使寄生二极管成为断开状态。由此，在本发明的半导体元件20中，在以往的仅具有PN结二极管的半导体元件中所担心的、不能快速地使其成为断开状态的、即成为所谓的闩锁(latch up)状态的情况被抑制。
另外，构成本实施方式的半导体元件20的肖特基二极管70使用由Ni构成的肖特基电极9a作为阳极，使用宽带隙半导体(在本实施方式中为SiC)作为阴极(半导体层3)。该肖特基二极管70，难以因通常使用的通电动作而在半导体层3与肖特基电极9a的界面上形成硅化物层，因此，从高电流耐性和高电压耐性的观点看是合适的。
在假设使用Ni作为阳极(肖特基电极9a)、使用Si(硅)作为阴极(半导体层3)构成肖特基二极管的情况下，难以在该肖特基二极管中流动大电流。即，在使用Si作为阴极的肖特基二极管中，在Si与Ni的界面容易形成硅化物层，结果，Si与Ni欧姆连接，有不能发挥作为二极管的功能的情况。这样，与通过使因浪涌电压引起的漏电流优先在肖特基二极管70中流动、从而防止半导体元件20的绝缘破坏的本发明的问题解决原理相反。
因此，在本实施方式中，阴极的构成的差异(半导体层3是由SiC构成还是由Si构成的差异)，不是取决于本领域技术人员的简单的设计事项，而是与上述问题解决原理直接关联的事项。
另外，使用宽带隙半导体SiC作为阴极(半导体层3)的肖特基二极管70，与使用Si作为阴极(半导体层3)的肖特基二极管比较，被施加浪涌电压时的耐压特性优异。
此外，PN结二极管通常具有优异的高电流耐性和高电压耐性，但当使用作为宽带隙半导体的SiC构成PN结二极管时，会产生因正向电压Vf的上升量而引起的导通损失。
综合以上内容，在本实施方式的半导体元件20中，优选在半导体层3中使用宽带隙半导体(SiC)构成肖特基二极管70。
(第二实施方式)
本发明的第二实施方式，对插入有使用第一实施方式的半导体元件20的臂模块(半导体装置)的逆变电路进行举例说明。
[臂模块]
图4是示意性地表示作为本发明的第二实施方式的半导体装置的臂模块的结构的平面图。在图4中，与图1～图3相同或相当的部分，标注相同的符号，省略其说明。
如图4所示，本实施方式的臂模块包括：第一实施方式的半导体元件20；和具有漏电极端子15、源电极端子16、和栅电极端子17的封装体。
半导体元件20，以其下面的漏电极1与漏电极端子15的上面连接的方式，配设在漏电极端子1上。并且，半导体元件20的源极·肖特基用垫12S通过导线13S分别与源电极端子16连接，半导体元件20的栅极用垫12G通过导线13G与栅电极端子17连接。半导体元件20的漏电极1与漏极端子15通过芯片接合(die bonding)而连接。另外，导线13S、13G的端部与源电极端子16或栅电极端子17通过接合(bonding)而连接。
这样相互连接的半导体元件20和各电极端子15、16、17由封装树脂18封装(塑模)。在此，作为上述封装树脂18，能够使用通用的封装树脂。
[逆变电路]
图5是表示本发明的第二实施方式的逆变电路的结构的电路图。在图5中，与图8相同或相当的部分，标注相同的符号，省略其说明。
本实施方式的逆变电路用于三相交流电动机驱动，具有相数的量(在此为3个)的由上臂23H与下臂23L串联连接而成的相开关电路23，上臂23H和下臂23L的各个由相互并联连接的开关元件21与二极管22构成。并且，上臂23H和下臂23L分别由本实施方式的臂模块构成。另外，各臂23H、23L的开关元件21由第一实施方式的半导体元件20中的场效应晶体管90构成。另一方面，二极管22是与开关元件21并联连接的反馈二极管，由第一实施方式的半导体元件20中的肖特基二极管70构成。关于除此以外的方面，在背景技术部分中已经说明过，因此省略其说明。
在本实施方式中，使用该逆变电路对第一实施方式的半导体元件20的结构进行研究。
参照图1～图3，在半导体元件20中，肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例优选为1％以上50％以下。进一步，肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例更优选为10％以上50％以下。
首先，对使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为1％的情况进行说明。对使用这样的半导体元件20作为本实施方式的臂模块时的开关损失进行了测定，能够实现开关损失降低2％。在此，对于半导体元件20，二极管形成区域9的单位面积换算的导通电阻为1mΩcm2左右。在使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为1％的情况下，如果使电流沿着肖特基二极管70的正向流动时的正向电压Vf加上肖特基势垒的正向的上升沿电压(1V)为3V左右(由电阻的电流产生的正向电压Vf上升是2V)，则按照元件整体的电流密度换算，能够流动20A/cm2(半导体元件为2A)左右的电流。在此，所谓正向电压为3V，是使正向的电流在本发明的半导体元件20中存在的寄生二极管中流动时的最低的正向电压。这是因为使用SiC作为半导体材料。因此，当使正向的电流在肖特基电极9a中流动时，如果能够将正向电压Vf保持在3V以下，则与不配设肖特基电极9a的以往的半导体元件相比，能够降低开关损失。
此时，晶体管形成区域10的平均化的单位面积换算的导通电阻，成为比二极管形成区域9的单位面积换算的导通电阻大约一个数量级的值。具体而言，晶体管形成区域10的平均化的单位面积换算的导通电阻成为10mΩcm2。因此，场效应晶体管90导通时的电流密度(以下称为导通电流密度)，当设正向电压Vf上升为2V时，估计为200A/cm2。此外，场效应晶体管90导通时的电流(以下，称为导通电流)，与在肖特基二极管70中流动的电流的流向为相反方向。
因此，当使场效应晶体管90的导通电流密度的约十分之一的电流密度的电流值在与导通电流相反的方向上在肖特基二极管70中流动的情况下，优选使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为1％。
另一方面，在上臂23H和下臂23L的连续动作试验中，上臂23H和下臂23L有因发热而动作不稳定的情况。据推测这是因为在肖特基二极管70中流动的电流值超过了上述允许电流值(20A/cm2)。因此，优选对肖特基电极9a的面积的比例进行设计，使得允许电流值比在肖特基二极管70中流动的电流值高。
接着，制作出肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为10％的半导体元件20，当使用该半导体元件20作为臂模块时，能够实现开关损失降低5％。另外，在该情况下，在肖特基二极管70中流动的电流的允许值，按照元件整体的电流密度换算，为200A/cm2(半导体元件为20A)。在此，因为允许电流值200A/cm2是足够高的电流值，所以在肖特基二极管70中流动的电流值不会超过允许电流值，上臂23H和下臂23L将稳定地进行动作。
如上所述，晶体管形成区域10的平均化的单位面积换算的导通电阻为10mΩcm2，因此，当使与场效应晶体管90的导通电流密度相同电流密度的电流值在与导通电流相反的方向上在肖特基二极管70中流动的情况下，优选使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为10％。
另外，制作出肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为50％的半导体元件20，当使用该半导体元件20作为臂模块时，能够实现开关损失降低1％。
如上所述，晶体管形成区域10的平均化的单位面积换算的导通电阻为10mΩcm2，但是可认为：将来，通过沟道电阻的降低等，能够使晶体管形成区域10的单位面积换算的导通电阻降低。结果，晶体管形成区域10的单位面积换算的导通电阻与二极管形成区域9的单位面积换算的导通电阻(1mΩcm2)接近。在此，晶体管形成区域10的导通电阻不能比二极管形成区域9的导通电阻小，但是有两者的导通电阻成为相同程度的值的情况。在该情况下，当使在场效应晶体管90中流动的导通电流的电流密度与在肖特基二极管70中流动的导通电流的电流密度相同时，优选使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为50％。
在此，当使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为10％以上时，半导体元件20的发热也能够得到抑制，逆变电路稳定地进行动作。
但是，当使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例超过50％时，晶体管单元100在半导体元件20整体中所占的比例降低，因此，场效应晶体管90的导通电阻增大，开关损失也增加。
另外，如果在肖特基二极管70中流动的电流按照元件整体的电流密度换算为200～600A/cm2，则能够期待半导体元件20的稳定动作，因此，更优选肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为10％以上30％以下。
如以上所述，当在肖特基二极管70中流动的电流值与在场效应晶体管90中流动的电流值相同(但是，流动的方向相反)时，在二极管形成区域9的导通电阻为晶体管形成区域10的导通电阻的十分之一的情况下，只要使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为10％即可。另外，在二极管形成区域9的导通电阻为晶体管形成区域10的导通电阻的三分之一的情况下，只要使肖特基电极9a的面积相对于半导体元件20的俯视时的面积的比例为大约30％即可。
综合以上的研究结果，在第一实施方式的半导体元件20中，为了充分实现本来的作为开关元件的功能，优选所有的晶体管单元100的俯视时的面积相对于半导体元件20的俯视时的面积的比例为50％以上99％以下。进一步，为了半导体元件20的稳定动作，更优选所有的晶体管单元100的俯视时的面积相对于半导体元件20的俯视时的面积的比例为70％以上90％以下。
(第三实施方式)
图6是表示本发明的第三实施方式的半导体元件的结构的平面图。图7是将图6的半导体元件的结构的一部分放大的部分平面图。在图6和图7中，与图1和图2相同或相当的部分，标注相同的符号，省略其说明。
如图6和图7所示，在本实施方式的半导体元件20中，二极管形成区域9通过以包围晶体管形成区域10的外周的方式配设肖特基电极9b面构成，该肖特基电极9b将在俯视时由格子状的假想的边界线50划分的单元200中的多个二极管单元80的上面覆盖。其它方面与第一实施方式同样。
肖特基电极9b沿着晶体管形成区域10的外周共配设有4个。此外，肖特基电极9b的配设数目并不限定于此。即，可以遍及多个单元200而配设肖特基电极9b、或者将肖特基电极9b的全体或者一部分一体化形成，其个数可以改变。即使形成这样的结构，也能实现与上述的第一实施方式同样的效果。另外，当形成这样的结构时，构成部件的件数变少，半导体元件20的制造变得容易，成品率提高。
在本实施方式的半导体元件20中，为了防止因电场的集中而导致的破坏，如图6所示，也优选将肖特基电极9b的角部形成为带有圆角的形状。
此外，二极管形成区域9可以不局限于单元200的大小而任意地变大。
另外，本实施方式的半导体元件20也与第一实施方式的半导体元件20同样，能够用于第二实施方式的臂模块和逆变电路，并能够取得与使用第一实施方式的半导体元件20时同样的效果。另外，优选所有的晶体管单元100的俯视时的面积相对于半导体元件20的俯视时的面积的比例也为50％以上99％以下。
此外，在第一～第三实施方式中，对场效应晶体管90为n沟道型的情况进行了说明，但本发明在场效应晶体管90为p沟道型的情况下也同样能够应用。但是，在该情况下，各半导体区域的导电型相反，源极区域和源电极与漏极区域和漏电极相反。
另外，在第一～第三实施方式中，对单元200为正方形并且呈行列状配置的情况进行了说明，但单元200的形状、配置等是任意的。
此外，在第一～第三实施方式中，对二极管单元80沿着晶体管形成区域10的外周在整个周边形成的情况进行了说明，但二极管单元80也可以沿着晶体管形成区域10的外周以散布的方式形成。例如，二极管单元80可以在沿着晶体管形成区域10的外周的一部分单元200上形成。另外，例如，也可以是二极管单元80沿着晶体管形成区域10的外周每隔一个单元200而形成的情况等。
根据上述说明，对于本领域技术人员来说，本发明的很多改良和其它实施方式是显而易见的。因此，上述说明应该被理解为仪是例示，是出于向本领域技术人员指导实施本发明的最佳方式的目的而提供的。只要不脱离本发明的精神，能够对其结构和/或功能的详细内容进行实质性的变更。
产业上的可利用性
本发明的半导体元件能够同时实现高速开关动作与能量损失降低，并且对基于由电气设备的电感负载等产生的反电动势的电流集中具有优异的耐性，同时元件端部的破坏得到抑制，例如，能够应用于电气设备的高速逆变电源电路的用途。

Claims (12)

1.一种半导体元件，其特征在于，包括：
多个场效应晶体管，该场效应晶体管具有：由宽带隙半导体构成的半导体层、在该半导体层中以包含该半导体层的上面的方式形成的第一导电型的第一源极/漏极区域、在所述半导体层中以包含所述上面和所述第一源极/漏极区域的方式形成的第二导电型区域、在所述半导体层中以包含所述上面和所述第二导电型区域的方式形成的第一导电型的漂移区域、以至少与所述第一源极/漏极区域的所述上面接触的方式设置的第一源电极/漏电极、以隔着栅极绝缘膜至少与所述第二导电型区域的所述上面相对的方式设置的栅电极、和与所述漂移区域欧姆连接的第二源电极/漏电极；和
在所述漂移区域的所述上面以与该上面形成肖特基结的方式设置的肖特基电极，
所述肖特基电极以沿着形成有所述多个场效应晶体管的区域的外周的方式设置。
2.如权利要求1所述的半导体元件，其特征在于：
所述源电极以与所述源极区域和第二导电型区域的所述上面接触的方式设置。
3.如权利要求1所述的半导体元件，其特征在于：
所述第一导电型为n型，所述第二导电型为p型。
4.如权利要求1所述的半导体元件，其特征在于：
所述半导体层在俯视时被假想的边界线分割成多个单元，
所述漂移区域和漏电极以在所述多个单元中延伸的方式形成，
所述多个单元由在其中形成有所述场效应晶体管的晶体管单元、和在其中形成有所述肖特基电极的二极管单元构成，
多个所述晶体管单元在晶体管形成区域相互邻接而形成，
以包围所述晶体管形成区域的方式形成有二极管形成区域，在该二极管形成区域形成有1个以上的所述二极管单元。
5.如权利要求4所述的半导体元件，其特征在于：
在所述半导体层的上面，以在俯视时位于所述二极管形成区域与所述半导体层的端部之间的方式形成有护环。
6.如权利要求1所述的半导体元件，其特征在于：
所述肖特基电极沿着形成有所述多个场效应晶体管的区域的外周排列在其整个周边。
7.如权利要求4所述的半导体元件，其特征在于：
所有所述晶体管单元的俯视时的面积相对于所述半导体元件的俯视时的面积的比例为50％以上99％以下。
8.如权利要求1所述的半导体元件，其特征在于：
所述肖特基电极的面积相对于所述半导体元件的俯视时的面积的比例为1％以上50％以下。
9.如权利要求4所述的半导体元件，其特征在于：
所述二极管单元的所述肖特基电极的面积比所述晶体管单元的所述第二导电型区域的俯视时的面积大。
10.一种电气设备，其特征在于，包括：
交流驱动装置；和构成该交流驱动装置的逆变电源电路的权利要求1～9中任一项所述的半导体元件，
所述半导体元件作为臂模块被插入。
11.如权利要求10所述的电气设备，其特征在于：
基于由所述交流驱动装置内的电感负载产生的反电动势而向所述场效应晶体管的寄生二极管和所述肖特基二极管施加的电压，比所述肖特基二极管的正向的上升沿电压大、并且比所述寄生二极管的正向的上升沿电压小。
12.如权利要求10所述的电气设备，其特征在于：
所述交流驱动装置为由所述逆变电源电路驱动的交流电动机。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101689821B (zh) * 2007-12-07 2012-08-29 松下电器产业株式会社 电动机驱动电路

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5770412B2 (ja) * 2008-01-31 2015-08-26 ダイキン工業株式会社 電力変換装置
JP4803241B2 (ja) * 2008-11-27 2011-10-26 三菱電機株式会社 半導体モジュール
KR101503226B1 (ko) * 2009-12-24 2015-03-16 미쓰비시덴키 가부시키가이샤 전력 변환 장치 및 전력 변환 장치의 구동 방법
JP2011210916A (ja) * 2010-03-30 2011-10-20 Mitsumi Electric Co Ltd 半導体装置の製造方法
EP2482315B1 (en) * 2010-10-29 2015-08-12 Panasonic Intellectual Property Management Co., Ltd. Semiconductor element
CN102668094B (zh) * 2010-10-29 2015-02-25 松下电器产业株式会社 半导体元件以及半导体装置
US8735968B2 (en) * 2010-12-28 2014-05-27 Monolithic Power Systems, Inc. Integrated MOSFET devices with Schottky diodes and associated methods of manufacturing
US8937319B2 (en) * 2011-03-07 2015-01-20 Shindengen Electric Manufacturing Co., Ltd. Schottky barrier diode
US8482029B2 (en) * 2011-05-27 2013-07-09 Infineon Technologies Austria Ag Semiconductor device and integrated circuit including the semiconductor device
JP5720478B2 (ja) 2011-08-05 2015-05-20 住友電気工業株式会社 炭化珪素半導体装置
US8772950B2 (en) * 2012-11-07 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for flip chip substrate with guard rings outside of a die attach region
JP5837229B2 (ja) * 2012-11-22 2015-12-24 三菱電機株式会社 車両用交流電動発電機
JP6295797B2 (ja) * 2014-04-10 2018-03-20 住友電気工業株式会社 炭化珪素半導体装置およびその製造方法
JP6274968B2 (ja) * 2014-05-16 2018-02-07 ローム株式会社 半導体装置
JP6021032B2 (ja) 2014-05-28 2016-11-02 パナソニックＩｐマネジメント株式会社 半導体素子およびその製造方法
US20160056817A1 (en) * 2014-08-20 2016-02-25 Navitas Semiconductor Inc. Power transistor with distributed diodes
US9691759B2 (en) 2015-10-01 2017-06-27 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device including semiconductor substrate, silicon carbide semiconductor layer, unit cells, source, and gate
US9837999B2 (en) * 2016-04-06 2017-12-05 Monolithic Power Systems, Inc. Electronic device with substrate current management
DE112017004143T5 (de) * 2016-08-19 2019-05-02 Rohm Co., Ltd. Halbleitervorrichtung und verfahren zur herstellung einer halbleitervorrichtung
JP2019046977A (ja) * 2017-09-01 2019-03-22 トヨタ自動車株式会社 半導体装置
US20200020679A1 (en) * 2018-07-10 2020-01-16 Sanken Electric Co., Ltd. Semiconductor Device and Method for Forming the Semiconductor Device
JP2020047679A (ja) * 2018-09-14 2020-03-26 株式会社東芝 半導体装置

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0752770B2 (ja) 1985-09-30 1995-06-05 株式会社東芝 導電変調型ｍｏｓｆｅｔ
JPH0828506B2 (ja) 1988-11-07 1996-03-21 三菱電機株式会社 半導体装置およびその製造方法
US5111253A (en) * 1989-05-09 1992-05-05 General Electric Company Multicellular FET having a Schottky diode merged therewith
JPH0834709B2 (ja) * 1990-01-31 1996-03-29 株式会社日立製作所 半導体集積回路及びそれを使つた電動機制御装置
JP2817536B2 (ja) 1991-09-27 1998-10-30 日本電気株式会社 半導体装置
US5430314A (en) 1992-04-23 1995-07-04 Siliconix Incorporated Power device with buffered gate shield region
JPH06120347A (ja) 1992-10-06 1994-04-28 Nissan Motor Co Ltd 半導体装置
JP2988871B2 (ja) 1995-06-02 1999-12-13 シリコニックス・インコーポレイテッド トレンチゲートパワーｍｏｓｆｅｔ
US6049108A (en) 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
JP3272242B2 (ja) 1995-06-09 2002-04-08 三洋電機株式会社 半導体装置
JP3291439B2 (ja) 1996-10-31 2002-06-10 三洋電機株式会社 Ｄｃ−ｄｃコンバータ装置
JP3291441B2 (ja) 1996-10-31 2002-06-10 三洋電機株式会社 Ｄｃ−ｄｃコンバータ装置
JPH11274482A (ja) 1998-03-20 1999-10-08 Toshiba Corp 半導体装置
US6476456B1 (en) 1999-06-10 2002-11-05 International Rectifier Corporation Integrated radiation hardened power mosgated device and schottky diode
GB0006092D0 (en) 2000-03-15 2000-05-03 Koninkl Philips Electronics Nv Trench-gate semiconductor devices
JP3502371B2 (ja) 2000-10-23 2004-03-02 松下電器産業株式会社 半導体素子
US7126169B2 (en) 2000-10-23 2006-10-24 Matsushita Electric Industrial Co., Ltd. Semiconductor element
JP2002373989A (ja) 2001-06-13 2002-12-26 Toshiba Corp 半導体装置
GB0118000D0 (en) 2001-07-24 2001-09-19 Koninkl Philips Electronics Nv Manufacture of semiconductor devices with schottky barriers
US6621107B2 (en) 2001-08-23 2003-09-16 General Semiconductor, Inc. Trench DMOS transistor with embedded trench schottky rectifier
JP4097417B2 (ja) 2001-10-26 2008-06-11 株式会社ルネサステクノロジ 半導体装置
JP4557507B2 (ja) 2002-06-13 2010-10-06 パナソニック株式会社 半導体デバイス及びその製造方法
JP5011634B2 (ja) 2003-08-29 2012-08-29 富士電機株式会社 半導体装置およびその半導体装置を用いた双方向スイッチ素子
CN100550383C (zh) * 2005-07-08 2009-10-14 松下电器产业株式会社 半导体装置和电气设备
JP5326405B2 (ja) * 2008-07-30 2013-10-30 株式会社デンソー ワイドバンドギャップ半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101689821B (zh) * 2007-12-07 2012-08-29 松下电器产业株式会社 电动机驱动电路

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