CN101233611A - 通过全半导体金属合金转变的金属栅极mosfet - Google Patents
通过全半导体金属合金转变的金属栅极mosfet Download PDFInfo
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Abstract
描述了一种MOSFET结构以及形成方法。所述方法包括:形成含金属层(56),所述含金属层(56)厚得足以将在第一MOSFET型区域(40)中的半导体层(22)全转变为半导体金属合金,但仅厚得足以将第二MOSFET型区域(30)中的半导体层(20)部分转变为半导体金属合金。在一个实施方式中,在形成含金属层(56)之前,使第一MOSFET区域(40)中的栅叠层凹进,使得第一MOSFET半导体叠层的高度小于第二MOSFET半导体叠层的高度。在另一实施方式中,在转变工艺之前,相对于第二类型MOSFET区域(30),使第一类型MOSFET区域(40)上方的含金属层(56)变薄。
Description
技术领域
本发明一般涉及集成电路的制造,并且更具体地涉及制造具有金属栅极的MOSFET(金属氧化物半导体场效应晶体管)器件的结构和方法。
背景技术
由于消除了栅极中的耗尽层,与使用半导体栅电极的传统半导体MOSFET器件相比,金属栅极技术允许改善的MOSFET器件性能;这样,将电转变氧化物厚度tinv降低大约3-5,而没有导致随后栅极氧化物泄漏电流显著增加。通常,半导体栅电极由多晶硅(poly或者poly-Si、非晶硅、SiGe等)形成。具有全硅化栅电极(FUSI栅极)的MOSFET器件允许较薄的电转变氧化物厚度tinv,这样由于在沟道中增加的载流子密度而导致改善的器件性能,并且还改进了对短沟道效应的控制。最近,已经显示,在硅化反应之前进行多晶硅栅电极的掺杂和将掺杂剂原子驱动到电介质界面的高温退火可以调整产生的金属电极的功函数。作为结果,不需要经由补偿沟道注入降低阈值电压,并且可以实现表面沟道MOSFET操作。具体地,类似于标准多晶硅栅极预掺杂步骤以接近4×1015cm-3的高剂量预掺杂锑(Sb)(锑是一种公知的n型掺杂剂),然后在高温下适当地退火,并且最后使用Ni作为开始材料进行全硅化,这样形成的多晶硅栅极相对于未掺杂的NiSi栅极来说具有从带隙中间(mid-gap)到距导带边缘大约120meV处的功函数偏移。另一方面,还发现p型掺杂剂可以将功函数朝向价带边缘显著偏移;这样,预掺杂全硅化栅极的技术对于pFET器件来说很少有效。使用当前的方法,为了获得距价带边缘200meV内的功函数,需要不同的金属硅化物材料,例如,使用具有30%Pt浓度的NiPt合金。针对nFET和pFET栅导体的硅化使用不同工艺使得很难集成nFET和pFET器件两者,特别是在密集封装的存储器单元中。在下文中,为了方便起见,术语“硅化(silicidation)”的使用意味着包括形成半导体金属合金的任何工艺,术语“硅化物(silicide)”意味着包括任何这种产生的半导体金属合金,以及术语“硅化的(silicided)”意味着包括已经转变为半导体金属合金的任何适当的半导体,而并不意味着局限于只包括硅半导体的工艺或者材料。
因而,期望提供一种结构和方法,用于以密集布局方式成本有效地集成全硅化(FUSI)MOSEFET器件,以实现FUSI栅极的改进性能,同时对MOSFET的电属性没有显著的不利影响。
发明内容
本发明的一个目的在于,提供一种结构以及用于制造该结构的方法,所述结构可以调整经由半导体栅极的全硅化(FUSI)所实现的金属栅极的改进性能,同时不干扰晶体管的电属性。
本发明的另一目的在于,提供一种针对全硅化的nFET或者pFET之一的集成的成本有效的方法,同时并没有不利地影响nFET和pFET的另一个的电属性。
本发明的又一目的在于,提供一种结构以及制造和集成所述结构的成本有效的方法,所述结构包括第一类型的全硅化FET(例如,nFET或者pFET)和第二类型的部分硅化的FET。例如,如果nFET具有全硅化的栅极,则pFET形成有部分硅化的栅极,或者如果期望,反之亦然。
本发明的又一目的在于,提供全硅化(FUSI)的nFET器件以及用于制造和集成FUSI nFET器件与具有部分硅化的栅电极的pFET器件的方法,使得nFET和pFET器件两者具有类似于标准栅电极的阈值电压。
本发明的再一目的在于,提供FUSI nFET和pFET器件,其可以在nFET和pFET器件之间间隔小于大约200nm的情况下集成在密集封装的电路中。
根据本发明的一个方面,提供了一种形成半导体结构的方法,包括:提供一种结构,所述结构包括在nFET区域中的栅叠层和在pFET区域中的栅叠层,其中所述栅叠层各自包括半导体层,以及所述结构进一步包括在nFET和pFET区域中的所述栅叠层上方形成的平坦化的电介质层;去除部分所述平坦化的电介质层,以暴露所述栅叠层的所述半导体层;形成与所述栅叠层的暴露的半导体层相接触的含金属层,其中所述含金属层厚得足以将所述nFET区域和pFET区域的第一个中的所述栅叠层的所述半导体层全硅化,但是没有厚得足以将所述nFET区域和pFET区域的第二个中的所述半导体层全硅化;以及由与在所述nFET区域和pFET区域的第一个中的所述栅叠层的所述半导体层相接触的所述含金属层,来形成全硅化的栅导体,而由与在所述nFET区域和pFET区域的第二个中的所述栅叠层的所述半导体层相接触的所述含金属层,来形成部分硅化的栅导体。
在本发明的一个实施方式中,在形成所述含金属层之前,使所述nFET区域和pFET区域的第一个中的所述栅叠层的所述半导体层凹进至一个高度,所述高度小于在所述nFET区域和pFET区域的第二个中的所述栅叠层的所述半导体层的高度。优选地,使在所述nFET区域和pFET区域的第一个中的所述栅叠层的所述半导体层凹进包括:相对于平坦化的电介质层有选择地对半导体层进行各向异性蚀刻(诸如,RIE)。
根据本发明的另一实施方式,相对于所述nFET区域和pFET区域的第一个上方的所述含金属层的厚度,使所述nFET区域和pFET区域的第二个上方的所述含金属层变薄。优选地,使用湿蚀刻执行使所述含金属层变薄。
根据本发明的又一方面,描述了一种半导体结构,包括:nFET器件和pFET器件的第一个,包含部分硅化的栅导体,所述部分硅化的栅导体包括包含半导体层的下部栅导体部分以及在所述下部栅导体部分之上的上部硅化栅导体部分;以及nFET器件和pFET器件的第二个,包含全硅化的栅导体,所述全硅化的栅导体高度小于所述nFET器件和pFET器件的所述第一个的所述部分硅化的栅导体的高度。在优选实施方式中,本发明的半导体结构包括以小于200nm距离间隔开的pFET器件和nFET器件。
根据本发明的又一方面,通过以下方法来形成包括nFET器件和pFET器件的半导体结构,所述nFET器件包括全硅化的栅导体,并且所述pFET器件包括部分硅化的栅导体,所述方法包括:提供一种结构,所述结构包括在nFET区域中的栅叠层和在pFET区域中的栅叠层,其中所述栅叠层各自包括半导体层,以及所述结构进一步包括在所述nFET和pFET区域中的所述栅叠层上方形成的平坦化的电介质层;去除部分所述平坦化电介质层,以暴露所述栅叠层的所述半导体层;形成与所述栅叠层的所述暴露的半导体层相接触的含金属层,其中所述含金属层厚得足以将所述nFET区域中的所述栅叠层的所述半导体层全硅化,但是没有厚得足以将所述pFET区域中的所述半导体层全硅化;以及由与在所述nFET区域中的所述栅叠层的所述半导体层相接触的所述含金属层,来形成全硅化的栅导体,而由与在所述pFET区域中的所述栅叠层的所述半导体层相接触的所述含金属层,来形成部分硅化的栅导体。
附图说明
参考以下附图,从本发明的以下详细描述中,这些和其他特征、方面和优点将变得更为清楚并且容易理解,其中相同的标记表示相同的元件,不必依照比例来绘制所述附图。
图1至图10示出了用以形成本发明的一个实施方式的工艺步骤。
图11至图15示出了用以形成本发明的第二实施方式的工艺步骤。
具体实施方式
现在将通过参考伴随本申请的附图来详细描述本发明,其中本发明提供了用于将具有全硅化的栅电极的第一类型(例如,nFET)的MOSFET器件与具有部分硅化的栅电极的第二类型(例如,pFET)的MOSFET器件进行集成的结构和方法。
根据本发明,提供了一个工艺流程,其中第一类型的MOSFET器件包括全硅化的栅电极,以及第二类型的MOSFET器件具有部分硅化的电极,使得两种器件具有类似于标准多晶硅栅电极方式的阈值电压。在此公开中描述的技术可以应用于具有小于大约200nm栅极间隙的密集封装的电路。在下文中所描述的示例性实施方式中,利用全硅化的栅电极来实现nFET,而利用部分硅化的栅电极来实现pFET,但是本发明并非旨在局限于这些实施方式,而是可以类似地应用于将全硅化的pFET栅电极与部分硅化的nFET栅电极集成。所描述的结构适用于密集的电路,具有200nm量级的栅极间隙,符合65nm工艺节点,并且可扩展到未来的工艺代。
参考图1,图1示出了初始半导体晶片衬底10,所述初始半导体晶片衬底10可以包括但不限于块状含硅衬底、绝缘体上硅(SOI)晶片。硅或者含硅衬底可以包括半导体材料,诸如但不限于可以在本发明中使用的Si、SiGe、SiC以及SiGeC。具体地,图1的初始晶片10包括n掺杂的阱区域11和p掺杂的阱区域12。在衬底10之上形成栅极电介质层18,并且在衬底10中可以形成隔离区域13。可以使用当前已知或者未来开发的任何方法(包括传统光刻以及蚀刻工艺)来形成沟槽,随后使用诸如化学气相沉积(CVD)或者等离子体CVD的工艺来使该沟槽填充有诸如TEOS(正硅酸乙酯)或者氧化物的电介质,以及之后通过诸如化学机械抛光(CMP)进行平坦化,来形成隔离区域13。利用传统热生长工艺或者通过沉积来在衬底之上形成栅极电介质层18。栅极电介质18通常是一个薄层,具有从大约1至大约10nm的厚度。栅极电介质可以包括氧化物,所述氧化物包括但不限于SiO2、氮氧化物、Al2O3、ZrO2、HfO2、Ta2O3、TiO2、钙钛矿型氧化物、硅酸盐、以及具有或者没有附加的氮的上述物质的组合物。可以使用热生长工艺或者通过沉积来形成栅极电介质。
在结构的暴露表面上形成栅极电介质之后,如图2中所示,分别在n掺杂的阱区域11和p掺杂的阱区域12上方形成栅叠层25和35。p-FET器件区域30包括在n掺杂的区域上形成的栅叠层25,以及n-FET器件区域40包括在p掺杂的区域12上形成的栅叠层35。
栅叠层25、35可以包括一个或者多个半导体层20、22,所述半导体层包括但不限于诸如多晶硅、Ge、SiGe、SiC、SiGeC等的半导体材料,其可以包括例如在pFET区域30中掺杂有p+型掺杂剂以及在nFET区域40中掺杂有n+型掺杂剂的半导体。栅叠层25、35可以包括硬掩模层24、26,通常包括诸如氮化硅的氮化物。栅叠层25、35可以通过如下工艺来形成:沉积半导体层和硬掩模层,并且利用诸如传统光刻以及蚀刻的构图方法来在晶片10之上提供多个构图的叠层区域。
参考图3,通过利用传统的离子注入,在掺杂的区域11、12之中形成在区域28、29中示出的源区/漏区,所述离子注入为诸如在pFET区域30的n型阱11中的源区/漏区28中的n+型掺杂剂以及在nFET区域40的p型阱12中的源区/漏区29中的p+类型掺杂剂。之后,例如在大约1000至1100℃范围的温度下进行退火,以激活源区/漏区28、29。然后,通过首先沉积绝缘材料(诸如,氮化物或者氮氧化物)并且然后选择性地蚀刻所述绝缘材料,来在构图的叠层区域25、35的每个暴露的垂直侧壁表面上形成绝缘间隔物27。间隔物27可以包括多个间隔物和材料,例如,间隔物27可以包括包含氮化物的内间隔物以及包含氧化物的外间隔物。图3示出了在已经执行上述处理步骤之后的结构。
现在参考图4,形成在源区/漏区28、29上的硅化物区域32。在优选实施方式中,使用自对准硅化物(salicide)工艺来形成硅化物区域32。在优选实施方式中,例如通过适当的方法(诸如溅射、PECVD、电子束蒸发等)来沉积诸如镍的金属。可以使用当与硅接触并且经受退火时能够形成金属硅化物的任意金属。适合的金属包括但不限于:Co、Ni、Ti、W、Mo、Ta等。优选的金属包括Ni、Co以及Ti,而镍是最为优选的。之后,在取决于金属的温度下,进行快速热退火(RTA),例如,如果所述金属是Ni,则温度优选地处于300-600℃的范围,以形成硅化镍区域32。随后,去除任何未反应的金属,产生图4所示的结构。
接着,参考图5,在覆盖包括硅化物区域32的nFET区域40和pFET区域30的结构的上方形成薄电介质层52。在随后的反应离子蚀刻(RIE)工艺期间,薄电介质层52将用作保护硅化物区域32。优选地,薄电介质层52是具有大约10-30nm厚度的氮化物。随后,在薄电介质层52之上形成第二电介质层54。在优选实施方式中,厚电介质层54是氧化物。厚电介质层54比栅叠层25、35的高度厚,优选地,比栅叠层的高度厚大约1.5至3倍,并且更优选地,大约为栅叠层25、35的高度的2至3倍。在图5中示出了产生的结构。
然后,正如图6所示,例如通过化学机械抛光(CMP)使得将厚电介质层54平坦化并且仍然覆盖栅叠层25、35,来使晶片平坦化。然后,例如使用RIE 71,对厚电介质层54(通常是氧化物)、薄电介质层52(通常是氮化物)、硬掩模24(通常是氮化物)以及间隔物27(通常是氧化物和氮化物的组合物)进行各向异性蚀刻,以便暴露半导体栅电极20、22(通常是多晶硅)。可以存在一些拓扑,这是因为通常针对氧化物和氮化物的蚀刻速率是不同的,只要蚀刻工艺在多晶硅上停止。在图7中示出了产生的结构。
参考图8,接着使用工艺中现有的光刻掩模版(reticle),利用光阻层60来阻挡pFET区域30。注意,本发明不需要在工艺的此步骤之中引入新的掩模版。然后,使用相对于电介质层54、52和间隔物27(通常相对于氮化物和氧化物)有选择性的干法各向异性蚀刻(例如,RIE),来使nFET半导体栅极22(通常是多晶硅)变薄。优选地,使nFET半导体栅电极22变薄至初始厚度的大约二分之一至三分之一。优选地,使产生的nFET栅电极足够薄,以实现nFET栅电极22的全硅化,但没有使pFET栅电极20全硅化。优选地,执行RIE,使得没有横向地影响产生的结构,这对于密集封装的栅极线(<200nm间隔)来说是一个重要的考虑。
参考图9,然后例如通过湿法蚀刻来去除光阻层,并且接着沉积含金属层56来接触半导体栅电极20、22的暴露表面,其中所述含金属层56随后与栅电极20、22反应。优选地,含金属层56在nFET30和pFET40区域上成分是基本均匀的。含金属层56可以包括当与半导体接触时能够形成半导体金属合金的任意金属,其中当半导体材料是硅时,这种反应通常称作硅化。在下文中,使用术语“硅化”来表示由半导体材料与金属的反应形成半导体金属合金的工艺,所述半导体材料包括但不限于Si、Ge、SiGe、SiC、SiGeC、GaAs等,所述金属包括但不限于Co、Ni、Ti、W、Mo、Ta等。优选地,对金属进行选择,使得产生的半导体金属合金(在下文中为了方便起见,称作“硅化物”)的功函数类似于重掺杂半导体(诸如,重掺杂的多晶硅)的功函数。对于多晶硅栅电极,优选金属包括Ni、Co和Ti,而镍是最优选的。使金属层56沉积一定厚度,所述厚度足够厚以便将剩余的nFET栅电极22全硅化,但是没有将pFET栅电极20全硅化。
接着,对所述结构进行快速热退火(RTA),以使金属层56与栅电极20、22反应。在依赖于半导体材料和金属的温度下,执行RTA。对于多晶硅栅电极与镍来说,优选的温度范围是300-600℃,而对于Co,优选的温度范围是550-750℃。在此实施方式中,由于pFET多晶硅20比nFET多晶硅22更厚,所以产生的自对准硅化物工艺部分地消耗了pFET电极20,而完全消耗了nFET电极22,这形成了如图10中所示的全硅化的nFET栅电极62。将pFET栅叠层部分地硅化,包括硅化物部分64以及未反应部分20。通常在所述结构上方形成层间电介质(ILD)层70,所述ILD层70具有从大约400至500nm范围的厚度,并且nFET和pFET器件依照常规来完成。
在另一实施方式中,使用湿法蚀刻而不是干法蚀刻来实现全硅化的nFET和部分硅化的pFET栅极。具体参考图11,紧接着在图7处开始的上述实施方式的序列,此时沉积一定厚度的优选包含Ni的含金属层56,该厚度足够将半导体(例如,多晶硅)栅极20、22全硅化。接着,如图12中所示,使用工艺中的现有光刻掩模版来利用光阻层63阻挡nFET区域40。注意,本发明不需要在工艺的此步骤中引入新的掩模版。接着,如图13中所示,使含金属层56暴露至稀释的湿蚀刻剂,该湿蚀刻剂从p-FET区域去除金属,将其变薄至使得最终产生的栅极在热反应之后不被全硅化的厚度。注意,由于湿法蚀刻工艺是各向同性的,所以将发生横向蚀刻。然后,使用湿法蚀刻来去除光阻层,留下nFET区域40上方的含金属层56,但是在pFET区域30上方的含金属层56已经变薄。
参考图14,对所述结构进行快速热退火(RTA),以使金属层56与栅电极20、22反应。温度依赖于反应,例如,对于多晶硅栅电极与Ni来说,优选地在300-600℃的温度范围中执行RTA。如果金属是Co,则优选的RTA温度范围是550-750℃。由于在nFET区域40上方的含金属层56比在pFET区域30上方的含金属层56更厚,所以产生的nFET栅极35被全硅化,具有金属转变区域66,但是pFET栅极25被部分硅化,具有在多晶硅20导体上方形成的金属转变区域65。
最后,如图15中所示出,通常在所述结构上方形成层间电介质(ILD)层70,通常具有范围从大约400至500nm的厚度。随后,nFET 35和pFET 25器件可以依照常规来完成。
根据本发明,所述方法不限于nFET的全硅化和pFET的部分硅化,而是还可适用于形成全硅化的pFET和部分硅化的nFET,可以进行所有合适的变化。
本发明实现了一种高性能的CMOS结构,所述CMOS结构针对nFET和pFET之一来利用金属栅极工艺,同时还针对nFET和pFET的另一个应用传统多晶硅栅电极工艺。在全硅化的nFET和部分硅化的pFET的情况下,可以使用多种公知的技术来进一步提高pFET性能,诸如使用应力来改善性能等。本发明的结构和方法尤其适用于密集电路,其中nFET和pFET器件之间具有小于200nm的间隔,符合65nm工艺或者更高工艺。
尽管已经根据本发明的特定优选实施方式描述了本发明,但是本领域技术人员应该理解,在不脱离本发明的真实范围和精神的情况下,还可以对本发明进行许多修改和增强,本发明的真实范围和精神仅由下文所附权利要求来限定。
工业应用性
根据本发明的结构和方法在集成电路制造中是有用的,并且实现了高性能的CMOS结构,所述CMOS结构针对nFET和pFET之一来利用金属栅极工艺,同时还针对nFET和pFET的另一个应用传统多晶硅栅电极工艺,并且根据本发明的结构和方法尤其适用于密集电路,其中nFET和pFET器件之间具有小于200nm的间隔,符合65nm工艺或者更高工艺。
Claims (20)
1.一种形成半导体结构的方法,包括:
提供一种结构,所述结构包括在第一类型的MOSFET区域(40)中的栅叠层和在第二类型的MOSFET区域(30)中的栅叠层,其中所述栅叠层各自包括半导体层(22、20),以及所述结构进一步包括在所述第一类型的MOSFET区域和所述第二类型的MOSFET区域中的所述栅叠层上方形成的平坦化的电介质层(54);
去除部分所述平坦化的电介质层(54),以暴露所述栅叠层的所述半导体层(22、20);
形成与所述栅叠层的所述暴露的半导体层(22、20)相接触的含金属层(56),其中所述含金属层(56)厚得足以将所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)全转变为半导体金属合金,但厚得不足以将所述第二类型的MOSFET区域(30)中的所述半导体层(20)全转变为半导体金属合金;以及
由与在所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)相接触的所述含金属层(56),来形成全转变的半导体金属合金栅导体(62、66),而由与在所述第二类型的MOSFET区域(30)中的所述栅叠层的所述半导体层(20)相接触的所述含金属层(56),来形成部分转变的半导体金属合金栅导体。
2.根据权利要求1所述的方法,其中所述栅叠层的所述半导体层(22、20)包括硅,以及所述含金属层(56)包括当与硅接触时能够形成半导体金属硅化物的金属,并且所述半导体金属硅化物的功函数基本类似于重掺杂多晶硅的功函数。
3.根据权利要求1所述的方法,进一步包括:在形成所述含金属层(56)之前,使所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)凹进至一个高度,所述高度小于在所述第二类型的MOSFET区域(30)中的所述栅叠层的所述半导体层(20)的高度。
4.根据权利要求3所述的方法,其中所述使所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)凹进包括:相对于所述平坦化电介质层(54)有选择地对所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)进行各向异性蚀刻。
5.根据权利要求3所述的方法,其中所述含金属层(56)包括镍,并且所述形成所述栅叠层的所述全部以及部分转变的半导体金属合金栅导体包括在大约300-600℃之间的温度下进行快速热退火。
6.根据权利要求1所述的方法,其中所述形成所述含金属层(56)进一步包括:相对于所述第一类型的MOSFET区域(40)上方的所述含金属层(56)的厚度,将所述第二类型的MOSFET区域(30)上方的所述含金属层(56)变薄。
7.根据权利要求6所述的方法,其中所述将所述第二类型的MOSFET区域(30)上方的所述含金属层(56)变薄进一步包括:在所述第一类型的MOSFET区域(40)上方形成掩模层(63),并且使用湿法蚀刻来使所述第二类型的MOSFET区域(30)上方的所述含金属层(56)变薄。
8.根据权利要求7所述的方法,其中所述湿法蚀刻包括稀释的湿法蚀刻。
9.根据权利要求6所述的方法,其中所述含金属层(56)包括镍,并且所述形成所述全部和部分转变的半导体金属合金栅导体包括在大约300-600℃之间的温度下进行快速热退火。
10.根据权利要求1所述的方法,其中所述含金属层(56)包括镍,并且所述形成所述全部和部分转变的半导体金属合金栅导体包括在大约300-600℃之间的温度下进行快速热退火。
11.根据权利要求1所述的方法,其中所述栅叠层的所述半导体层(22、20)包括从以下组中选择的半导体,所述组包括:Si、Ge、SiGe、SiC、SiGeC以及GaAs。
12.根据权利要求3所述的方法,其中所述栅叠层的所述半导体层(22、20)包括从以下组中选择的半导体,所述组包括:Si、Ge、SiGe、SiC、SiGeC以及GaAs。
13.根据权利要求6所述的方法,其中所述栅叠层的所述半导体层(22、20)包括从以下组中选择的半导体,所述组包括:Si、Ge、SiGe、SiC、SiGeC以及GaAs。
14.一种半导体结构,包括:
第一类型的MOSFET器件(35),包括全转变的半导体金属合金栅导体;以及
第二类型的MOSFET器件(25),包括部分转变的半导体金属合金栅导体,所述部分转变的半导体金属合金栅导体包括包含半导体层(20)的下部栅导体部分以及在所述下部栅导体部分(20)之上的上部半导体金属合金栅导体部分(64、65),
其中所述第一类型的MOSFET器件(35)的所述全转变的半导体金属合金栅导体(62、66)的高度小于所述第二类型的MOSFET器件(25)的所述部分转变的半导体金属合金栅导体的高度。
15.根据权利要求14所述的半导体结构,其中所述第一类型的MOSFET器件(35)和所述第二类型的MOSFET器件(25)以小于200nm的距离间隔开。
16.根据权利要求14所述的半导体结构,其中所述第一类型的MOSFET器件(35)的所述全转变的半导体金属合金栅导体以及所述第二类型的MOSFET器件(25)的所述上部半导体金属合金栅导体部分(64、65)包括硅化镍。
17.根据权利要求14所述的半导体结构,由以下方法形成,包括步骤:
提供一种结构,所述结构包括在第一类型的MOSFET区域(40)中的栅叠层和在第二类型的MOSFET区域(30)中的栅叠层,其中所述栅叠层各自包括半导体层(22、20),以及所述结构进一步包括在所述第一类型的MOSFET区域和所述第二类型的MOSFET区域中的所述栅叠层上方形成的平坦化的电介质层(54);
去除部分所述平坦化的电介质层(54),以暴露所述栅叠层的所述半导体层(22、20);
形成与所述栅叠层的所述半导体层(22、20)的所述暴露的部分相接触的含金属层(56),其中所述含金属层(56)厚得足以将所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)全转变为半导体金属合金,但没有厚得足以将所述第二类型的MOSFET区域(30)中的所述栅叠层的所述半导体层(20)全转变为半导体金属合金;以及
由与在所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)相接触的所述含金属层(56),来形成全转变的栅导体(62、66),而由与在所述第二类型的MOSFET区域(30)中的所述栅叠层的所述半导体层(20)相接触的所述含金属层,来形成部分转变的栅导体。
18.根据权利要求17所述的半导体结构,所述方法进一步包括:在形成所述含金属层(56)之前,使所述第一类型的MOSFET区域(40)中的所述栅叠层的所述半导体层(22)凹进至一个高度,所述高度小于在所述第二类型的MOSFET区域(30)中的所述栅叠层的所述半导体层(20)的高度。
19.根据权利要求1所述的方法,其中所述第一类型的MOSFET区域(40)是nFET区域,并且所述第二类型的MOSFET区域(30)是pFET区域。
20.根据权利要求14所述的结构,其中所述第一类型的MOSFET器件(35)是nFET器件,并且所述第二类型的MOSFET器件(25)是pFET器件。
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US11/161,372 US7151023B1 (en) | 2005-08-01 | 2005-08-01 | Metal gate MOSFET by full semiconductor metal alloy conversion |
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EP (1) | EP1911088A4 (zh) |
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