CN101154630A - 制造快闪存储器件的方法 - Google Patents

制造快闪存储器件的方法 Download PDF

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CN101154630A
CN101154630A CNA2007101294731A CN200710129473A CN101154630A CN 101154630 A CN101154630 A CN 101154630A CN A2007101294731 A CNA2007101294731 A CN A2007101294731A CN 200710129473 A CN200710129473 A CN 200710129473A CN 101154630 A CN101154630 A CN 101154630A
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朴丙洙
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    • HELECTRICITY
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H10B41/41Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND

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Abstract

本发明涉及一种制造快闪存储器件的方法。在包括单元区域和周边区域的半导体衬底上形成多个单元、多个选择晶体管和晶体管。在整个表面上形成绝缘层。蚀刻金属接触孔并利用金属接触层填充。还蚀刻漏极接触孔并利用漏极接触层填充。可以颠倒金属接触层形成和漏极接触层形成的顺序。实施单一化学机械抛光步骤以去除金属和漏极接触层的顶部,从而暴露间层绝缘层的顶表面并同时形成金属和漏极接触。

Description

制造快闪存储器件的方法
技术领域
本发明一般涉及快闪存储器件,更具体涉及一种制造快闪存储器件的方法,该方法可减少工艺步骤的数量。
背景技术
图1A~1D是图示说明根据常规的制造快闪存储器件的方法的横截面图。
参考图1A,通过常规的工艺,在半导体衬底10的单元区域中形成多个存储单元Cell和选择晶体管Sel Tr。在半导体衬底10的周边区域中形成晶体管Tr。在包括周边和单元区域的半导体衬底10的整个表面上形成绝缘层11。通过蚀刻过程在选择晶体管Sel Tr之间的漏极区域中形成漏极接触孔12。利用多晶硅层13a填充漏极接触孔12。
参考图1B,对多晶硅层13a实施化学机械抛光(CMP)过程以暴露绝缘层11的顶表面。因此,形成漏极接触13。
参考图1C,实施蚀刻过程,使得邻近周边区域中晶体管Tr的结区暴露,从而形成金属接触孔14。形成钨层15a以填充金属接触孔14。
参考图1D,对钨层15a实施CMP过程,使得绝缘层11的顶表面被暴露。因此,形成金属接触15。
在上述的方法中,在漏极接触13的顶表面上形成缝。在对多晶硅层13a实施CMP过程之后的清洗过程中缝被弱化。此外,在钨层15a的沉积过程中,钨渗透缝区,引起接触电阻值的变化。
对于单元区域中漏极接触13和周边区域中金属接触15的每一个,上述的方法也需要单独的蚀刻、沉积和CMP步骤。此外,即使用于形成漏极接触13的CMP过程和用于形成金属接触15的CMP过程所得到的最终抛光高度相同,但是必须实施两个CMP过程。因此,增长加工时间并增加生产成本。
发明内容
因此,本发明解决上述问题,并公开一种制造快闪存储器件的方法,其中当形成单元区域的漏极接触和周边区域的金属接触时,在两个区域的接触塞形成后同时实施抛光步骤,因此,有效地去除由漏极接触弯曲所引起的缝。此外,能够减少工艺步骤的数量和总存取时间(TAT),从而降低制造成本。
根据本发明的一个方面,提供一种制造快速存储器件的方法,包括步骤:在具有单元区域和周边区域的半导体衬底上形成多个单元、多个选择晶体管、和晶体管,其中在单元区域中形成所述多个单元和所述多个选择晶体管,在周边区域中形成所述晶体管;在所得表面上形成绝缘层;部分地蚀刻绝缘层,使得邻近晶体管的结区暴露,从而形成第一接触孔;沉积第一接触材料以填充第一接触孔;部分地蚀刻第一接触材料和绝缘层,使得邻近选择晶体管的漏极区域暴露,从而形成第二接触孔;沉积第二接触材料以填充第二接触孔;以及实施CMP过程以暴露绝缘层的顶表面,从而同时形成第一接触和第二接触。
根据本发明的另一个方面,提供一种制造快速存储器件的方法,包括步骤:在具有单元区域和周边区域的半导体衬底上形成多个单元、多个选择晶体管、和晶体管,其中在单元区域中形成所述多个单元和所述多个选择晶体管,在周边区域中形成所述晶体管;在所述表面上形成绝缘层;部分地蚀刻绝缘层,使得邻近选择晶体管的漏极区域暴露,从而形成第一接触孔;沉积第一接触材料以填充第一接触孔;部分地蚀刻第一接触材料和绝缘层,使得邻近晶体管的结区暴露,从而形成第二接触孔;沉积第二接触材料以填充第二接触孔;以及实施CMP过程以暴露绝缘层的顶表面,从而同时形成第一接触和第二接触。
附图说明
图1A~1D是图示说明根据常规的制造快闪存储器件的方法的横截面图。
图2A~2D是图示说明根据本发明的第一实施方案制造快闪存储器件的方法的横截面图。
图3A~3C是图示说明根据本发明的第二实施方案制造快闪存储器件的方法的横截面图。
具体实施方式
下面参考附图描述本发明的实施方案。
第一实施方案
参考图2A,在半导体衬底100的单元区域中形成多个存储单元Cell以及选择晶体管Sel Tr。在这种情况下,多个存储单元Cell的每一个都具有隧道绝缘层、浮栅、介电层和控制栅极的结构,选择晶体管Sel Tr具有隧道绝缘层、浮栅和控制栅极的结构。此外,在半导体衬底100的周边区域中形成晶体管Tr。
在包括多个存储单元Cell、选择晶体管Sel Tr和晶体管Tr的整个表面上形成绝缘层101。
蚀刻绝缘层101以暴露邻近周边区域的晶体管Tr的结区,从而形成第一接触孔102。沉积金属层103a以填充第一接触孔102。优选地,由钨形成金属层103a。
参考图2B,蚀刻金属层103a和绝缘层101以暴露单元区域的各选择晶体管Sel Tr之间的漏极区域,从而形成第二接触孔104。
参考图2C,沉积接触材料105a以填充第二接触孔104。优选地,用多晶硅形成接触材料105a。在这种情况下,由于在绝缘层101的顶表面上的金属层103a的附加厚度,相对于现有技术,第二接触孔104的高度增加。因此,接触材料105a的形成引起接触孔104的上侧面的弯曲(即,顶部,相比于现有技术)。
参考图2D,通过去除金属材料103a和接触材料105a的顶部,实施CMP过程以暴露绝缘层101的顶表面。因此,分别形成金属接触103和漏极接触105。优选利用相对于全部材料具有相同的抛光速率的低选择性浆料(LSS)实施CMP过程。在这种情况下,由于CMP过程而在接触材料105a顶表面上由弯曲所产生的缝被去除。
此外,因为仅实施一次用于形成金属接触103和漏极接触105的CMP过程,所以相对于现有技术,减少了工艺步骤的数量。
第二实施方案
参考图3A,在半导体衬底200的单元区域中形成多个存储单元Cell和选择晶体管Sel Tr。多个存储单元Cell的每一个都具有隧道绝缘层、浮栅、介电层和控制栅极的结构,选择晶体管Sel Tr具有隧道绝缘层、浮栅和控制栅极的结构。此外,在半导体衬底200的周边区域中形成晶体管Tr。
在包括多个存储单元Cell、选择晶体管Sel Tr和晶体管Tr的整个表面上形成绝缘层201。
蚀刻绝缘层201以暴露单元区域的选择晶体管Sel Tr之间的漏极区域,从而形成第一接触孔202。沉积接触材料203a以填充第一接触孔202。优选地,由多晶硅形成接触材料203a。
此后,蚀刻接触材料层203a和绝缘层201以暴露邻近周边区域的晶体管Tr的结区,因此形成第二接触孔204。
参考图3B,沉积金属材料205a以完全填充第二接触孔204。优选地,用钨形成金属材料205a。
参考图3C,实施CMP过程,以通过去除金属材料205a和接触材料203a的顶部来暴露绝缘层201的顶表面。因此,分别形成漏极接触203和金属接触205。可利用相对于全部材料具有相同的抛光速率的LSS实施CMP过程。因为仅实施一次用于形成金属接触205和漏极接触203的CMP过程,所以相对于现有技术,减少了工艺步骤的数量。
如上所述,根据本公开的第一实施方案,在形成漏极接触和金属接触的方法中,在形成金属接触孔后,沉积金属材料。然后形成漏极接触孔而没有CMP过程介入。在沉积接触材料后,对金属和接触材料实施单一的CMP过程。因此,由于升高的漏极接触的弯曲位置,可省略额外的CMP过程。此外,由于减少了工艺步骤的数量,因此可减少TAT并降低生产成本。
根据本发明的第二实施方案,在形成漏极接触和金属接触的方法中,形成漏极接触孔,然后沉积接触材料。然后形成金属接触孔而没有CMP过程介入。在沉积金属材料后,对金属和接触材料实施单一的CMP过程。因此,由于减少了工艺步骤的数量,因此可减少TAT并降低生产成本。
尽管已参考不同的实施方案在前面描述了本发明,但是本领域技术人员应该理解,在不背离本发明公开和所附权利要求的范围和精神的情况下,可对本发明公开进行各种变化和修改。

Claims (10)

1.一种制造快闪存储器件的方法,包括步骤:
在具有单元区域和周边区域的半导体衬底上形成多个单元、多个选择晶体管、和晶体管,其中,在所述单元区域中形成所述多个单元和所述多个选择晶体管,在所述周边区域中形成所述晶体管;
在所述多个单元、所述多个选择晶体管、所述晶体管和所述半导体衬底上形成绝缘层;
蚀刻所述绝缘层以暴露邻近所述晶体管的结区,从而形成第一接触孔;
沉积第一接触材料以填充所述第一接触孔;
蚀刻所述第一接触材料和所述绝缘层以暴露邻近所述选择晶体管的漏极区域,从而形成第二接触孔;
沉积第二接触材料以填充所述第二接触孔;和
实施化学机械抛光(CMP)过程以暴露所述绝缘层的顶表面,从而形成第一接触和第二接触。
2.根据权利要求1所述的方法,其中
所述第一接触是金属接触,和
所述第二接触是漏极接触。
3.根据权利要求1所述的方法,其中所述第一接触材料包含钨。
4.根据权利要求1所述的方法,其中所述第二接触材料包含多晶硅。
5.根据权利要求1所述的方法,其中利用相对于全部材料具有相同的抛光速率的低选择性浆料(LSS)实施所述CMP过程。
6.一种制造快闪存储器件的方法,包括步骤:
在具有单元区域和周边区域的半导体衬底上形成多个单元、多个选择晶体管、和晶体管,其中,在所述单元区域中形成所述多个单元和所述多个选择晶体管,在所述周边区域中形成所述晶体管;
在所述多个单元、所述多个选择晶体管、所述晶体管和所述半导体衬底上形成绝缘层;
蚀刻所述绝缘层以暴露邻近所述选择晶体管的漏极区域,从而形成第一接触孔;
沉积第一接触材料以填充所述第一接触孔;
蚀刻所述第一接触材料和所述绝缘层以暴露邻近所述晶体管的结区,从而形成第二接触孔;
沉积第二接触材料以填充所述第二接触孔;和
实施CMP过程以暴露所述绝缘层的顶表面,从而形成第一接触和第二接触。
7.根据权利要求6所述的方法,其中
所述第一接触是漏极接触,和
所述第二接触是金属接触。
8.根据权利要求6所述的方法,其中所述第一接触材料包含多晶硅。
9.根据权利要求6所述的方法,其中所述第二接触材料包含钨。
10.根据权利要求6所述的方法,其中利用相对于全部材料具有相同的抛光速率的低选择性浆料(LSS)实施CMP过程。
CNB2007101294731A 2006-09-29 2007-07-17 制造快闪存储器件的方法 Expired - Fee Related CN100505220C (zh)

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* Cited by examiner, † Cited by third party
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KR970072090A (ko) * 1996-04-24 1997-11-07 김광호 반도체 소자의 배선층 형성 방법
US6376879B2 (en) * 1998-06-08 2002-04-23 Kabushiki Kaisha Toshiba Semiconductor device having MISFETs
KR100734083B1 (ko) 2001-06-28 2007-07-02 주식회사 하이닉스반도체 반도체 소자의 콘택홀 형성방법
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KR20040080599A (ko) 2003-03-12 2004-09-20 주식회사 하이닉스반도체 반도체 소자의 콘택 플러그 형성방법
JP2004335522A (ja) * 2003-04-30 2004-11-25 Elpida Memory Inc 半導体記憶装置製造方法及び半導体記憶装置
KR20050108141A (ko) 2004-05-11 2005-11-16 주식회사 하이닉스반도체 낸드 플래쉬 메모리 소자의 제조 방법
KR100626378B1 (ko) * 2004-06-25 2006-09-20 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
KR20060108035A (ko) 2005-04-11 2006-10-17 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
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