CN101150120A - 堆叠的半导体封装及其制造方法和引线键合监控方法 - Google Patents

堆叠的半导体封装及其制造方法和引线键合监控方法 Download PDF

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CN101150120A
CN101150120A CNA2007101534646A CN200710153464A CN101150120A CN 101150120 A CN101150120 A CN 101150120A CN A2007101534646 A CNA2007101534646 A CN A2007101534646A CN 200710153464 A CN200710153464 A CN 200710153464A CN 101150120 A CN101150120 A CN 101150120A
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chip
semiconductor
pad
interposer chip
semiconductor chip
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金泰勋
权兴奎
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明公开了一种堆叠的半导体封装及其制造方法和堆叠的半导体封装的引线键合的监测方法。该半导体封装可包括布线基板。第一半导体芯片可安置在布线基板上且引线键合布线基板。内插芯片可安置在布线基板上且引线键合布线基板。内插芯片可包括导电连接的电路元件和焊盘。第二半导体芯片可安置在内插芯片上且引线键合内插芯片。第二半导体芯片通过内插芯片可导电连接布线基板。

Description

堆叠的半导体封装及其制造方法和引线键合监控方法
技术领域
本发明涉及一种半导体封装、一种该半导体封装的制造方法和该半导体封装的使用方法。
背景技术
电子器件市场在移动电子产品领域普遍增长。可安装在移动电子产品中的电子元件，如，半导体器件，应该更轻和更小。因此，已开发了以下的半导体器件：可缩小尺寸的半导体器件；可在一个半导体芯片中包括几个独立半导体器件的半导体器件，即芯片上系统(SOC)；和/或可包括封装在一个半导体封装中的多个半导体芯片的半导体器件，即系统级封装(SIP)。
依照SIP技术，多个半导体芯片安装在引脚框架或基板上。针对半导体封装水平或垂直地安装这些半导体芯片。SIP技术与传统多芯片组件(MCM)技术具有相似的概念。它们的区别是传统MCM技术包括以水平方向安装半导体芯片，而SIP技术包括垂直堆叠半导体芯片形成一种半导体堆叠封装。
同时，如果采用传统半导体芯片形成半导体堆叠封装，半导体芯片中焊垫的位置将是一样的，与半导体堆叠封装的类型无关。因此，在布线基板中，如，在PCB中，布线层的数量增多。为了减少PCB中布线层的数量，可在半导体芯片之间堆叠内插芯片。
但是，传统内插芯片只包括输入/输出(I/O)焊盘以连接上下半导体芯片。因此，如果该内插芯片的焊盘例如用金线进行引线键合，那么该引线键合是否成功可能无法探测到。
例如，不粘缺陷可出现在引线没有跟内插芯片上的焊盘适当键合的情况下。如果不粘缺陷出现，将判断所有半导体芯片有缺陷，而不能发现缺陷的引线键合。因此，该半导体堆叠封装的成品率将会降低。同样，如果在内插芯片的焊盘中引线键合缺陷没有探测到，该半导体堆叠封装可进入下一工序，而增加实行进一步测试的负担，这可接着增加成本。
发明内容
示范实施例可提供一种包括能监测引线键合的内插芯片的堆叠的半导体封装。
示范实施例可提供一种堆叠的半导体封装的制备方法，该半导体封装能实现内插芯片的引线键合监测。
本发明的一示范实施例中，堆叠的半导体封装可包括布线基板。第一半导体芯片可安置在布线基板上且引线键合布线基板。内插芯片可安置在第一半导体芯片上且引线键合布线基板。内插芯片可包括导电连接的电路元件和焊盘。第二半导体芯片可安置在内插芯片上且引线键合内插芯片，第二半导体芯片通过内插芯片导电连接布线基板。
依照一示范实施例，电路元件可连接接地垫或接地线。
依照一示范实施例，电路元件可为二极管。
依照一示范实施例，电路元件可为电容器。
本发明的一实施例中，堆叠的半导体封装的制备方法可包括：在布线基板上安置第一半导体芯片；引线键合第一半导体芯片和布线基板；在第一半导体芯片上安置内插芯片，内插芯片包括导电连接的电路元件和焊盘；引线键合内插芯片的焊盘和布线基板；在内插芯片上安置第二半导体芯片；且引线键合第二半导体芯片和内插芯片的焊盘以导电连接第二半导体芯片和布线基板。
依照一示范实施例，该方法可包括连接电路元件和接地垫或接地线。
依照一示范实施例，电路元件可为二极管。
依照一示范实施例，电路元件可为电容器。
本发明的一实施例中，一种堆叠的半导体封装的引线键合的监测方法，该方法可包括：在内插芯片的焊盘上施加电流；测量电路元件的电流或电压之一；且将电路元件的测量电流或电压分别与参考电流或电压比较。
依照一示范实施例，电路元件可为二极管，且施加电流可包括在内插芯片的焊盘上施加直流电。
依照一示范实施例，电路元件可为电容器，且施加电流可包括在内插芯片的焊盘上施加交流电。
附图说明
示范实施例将参考附图进行说明。
图1为依照一示范实施例所绘示的堆叠的半导体封装的截面图。
图2为图1的堆叠的半导体封装的透视图。
图3和图4为依照一示范实施例所绘示的内插芯片的示意图。
图5为依照一示范实施例所绘示的内插芯片的截面图。
图6为传统内插芯片的截面图。
图7和图8为监测堆叠的半导体封装的内插芯片上引线键合的说明示意图。
具体实施方式
现将参考附图更加全面地描述示范实施例。然而，示范实施例可以以许多不同的形式实现且不应解释为限于这里阐述的示范实施例。而是，提供这些示范实施例使得本公开充分和完整，且向那些本领域的技术人员全面地传达本发明的范围。在附图中，为了清晰夸大了层和区域的厚度。
可以理解当元件被称为“连接到”或“耦合到”另一元件时，它可以直接连接到或耦合到另一元件，或者可以存在中间的元件。相反，当元件被称为“直接连接到”或“直接耦合到”另一元件时，则没有中间元件存在。其他用来描述元件间关系的词语应解释为相同的模式(如，“中间”与“直接中间”，“邻近”与“直接邻近”等)。
这里所使用的术语是只为了描述特别的实施例的目的且不旨在限制示范实施例。如这里所用，单数形式“一”和“该”也旨在包括复数形式，除非内容清楚地指示另外的意思。可以进一步理解当在此说明书中使用时术语“包括”说明所述特征、整体、步骤、操作、元件和/或组分的存在，但是不排除存在或添加一个或更多其他特征、整体、步骤、操作、元件、组分和/或其组。如这里所用，术语“和/或”包括一个或多个有关列出项的任一和全部组合。
可以理解虽然术语第一、第二和第三等可以用于此来描述各种元件、部件、区域、层和/或部分，这些元件、部件、区域、层和/或部分应不受这些术语限制。这些术语只用于区分一个元件、部件、区域、层或部分与其他元件、部件、区域、层或部分。因此，以下讨论的第一元件、部件、区域、层或部分可以被称为第二元件、部件、区域、层或部分，而不背离示范实施例的范围。
在这里为了描述的方便，可以使用空间相对术语，诸如“下面”、“下方”、“下”、“上方”、“上”等，来描述一个元件或特征和其他元件或特征如图中所示的关系。可以理解空间相对术语旨在包括除了在图中所绘的方向之外的器件在使用或操作中的不同方向。例如，如果在图中的器件被翻转，被描述为在其他元件或特征的“下方”或“下面”的元件则应取向在所述其他元件或特征的“上方”。因此，例如术语“下方”可以包括下方和上方两个方向。器件也可以有其它取向(旋转90度或其它取向被观察或参照)且相应地解释这里所使用的空间相对描述语。
参考横截面图示在这里描述示范实施例，该图示是理想实施例(和中间结构)的示意图。因此，可以预期由于例如制造技术和/或公差引起的图示的形状的变化。因此，示范实施例不应解释为限于这里所示的特别的区域形状，而是可包括由于例如制造引起的形状的偏离。例如，被示为矩形的注入区将通常具有修圆或弯曲的特征和/或在其边缘具有(例如注入浓度)的梯度而不是从注入区到非注入区的突然变化。相似地，由注入形成的埋入区可以引起埋入区和通过其可进行注入的表面之间的区域中的某些注入。因此，图中示出的区域本质上是示意性的且它们的形状不必示出器件的区域的实际形状且不旨在限制本发明的范围。
除非另有界定，这里使用的所有术语(包括技术和科学术语)具有示范实施例属于的领域的普通技术人员共同理解的相同的意思。还可以理解这里所用术语应解释为具有与它们在此说明书上下文和相关技术中的意思一致的意思，而不应解释为理想化或过度正式的意义，除非在这里明确地如此界定。
依照一示范实施例，一种堆叠的半导体封装可包括能监测引线键合的内插芯片。该堆叠的半导体封装可包括多个在布线基板上的半导体芯片，如，三个或更多半导体芯片。该堆叠的半导体封装可包括内插芯片。应用该堆叠的半导体封装可不考虑堆叠位置、内插芯片尺寸、内插芯片的堆叠方法、封装形式和/或半导体芯片的尺寸或形式。内插芯片可应用于堆叠的半导体封装的半导体芯片之间不考虑这些半导体芯片是垂直地、水平地堆叠，还是垂直堆叠的半导体芯片堆平行的排放。
图1为依照一示范实施例绘示的堆叠的半导体封装的截面图。图2为图1的堆叠的半导体封装的透视图。
堆叠的半导体封装可包括布线基板10。引脚14在布线基板10的上表面上可形成。导电凸点，如，焊料球，在布线基板10的下表面上可形成。
第一半导体芯片18可安置在布线基板10上。第一粘合层16可插入布线基板10和第一半导体芯片18之间。第一焊线20可引线键合第一半导体芯片18的布线垫(没显示)和布线基板10的引脚14。
内插芯片24可安置在第一半导体芯片18上。第二粘合层22可插入第一半导体芯片18和内插芯片24之间。内插芯片24的焊盘(没显示)和布线基板10的引脚14由第二焊线26引线键合。
如果用于堆叠封装的信号、电源和/或接地的焊垫(或可选地，管脚，球或引脚)集成在内插芯片24中，内插芯片24可减少布线基板10中的布线层。如果每一个半导体芯片为引线键合，内插可缩小布线的长度。如果内插芯片24引线键合焊盘(没显示)，电路元件(没显示)，如，二极管或电容器，可与内插芯片24的焊盘(没显示)连接以产生极性和电流。因此，电路元件能够监测引线键合，这将在下面进行更为详细的描述。
第二半导体芯片30可安置在内插芯片24上。第三粘合层28可插入内插芯片24和第二半导体芯片30之间。第二半导体芯片30的焊盘(没显示)和内插芯片24的焊盘(没显示)可由第三焊线32引线键合。第二半导体芯片30通过内插芯片24可导电连接布线基板10。垫片36可安置在第二半导体芯片30上。第四粘合层34可插入第二半导体芯片30和垫片36之间。垫片36可利于引线键合随后贴装的第三半导体芯片40。
第三半导体芯片40可安置在垫片36上。第五粘合层38可插入垫片36和第三半导体芯片40之间。第四焊线42可引线键合第三半导体芯片40的焊盘(没显示)和内插芯片24的焊盘(没显示)。第三半导体芯片40通过内插芯片24可导电连接布线基板10。如上所述，内插芯片24可作为导电连接第二和第三半导体芯片30和40及布线基板10的中间媒介。可形成密封剂44以保护和覆盖第一、第二和第三半导体芯片18、30、40、内插芯片24和垫片36。如，密封剂44可为环氧树脂。
依照一示范实施例，如图1所示，垂直堆叠在内插芯片24上的第二半导体芯片30和第三半导体芯片40可导电连接布线基板10。在另一示范实施例中，水平堆叠的第二半导体芯片30和第三半导体芯片40可导电连接布线基板10。
参照图1，依照一示范实施例，一种堆叠的半导体封装的制备方法可包括在布线基板10上安置第一半导体芯片18。第一半导体芯片18采用第一焊线20可引线键合布线基板10。内插芯片24可安置在第一半导体芯片18上。内插芯片24可包括可具有极性和电流的电路元件。内插芯片24的焊盘采用第二焊线26可引线键合到布线基板10。
第二半导体芯片30可安置在内插芯片24上。第二半导体芯片30采用第三焊线32可引线键合内插芯片24的焊盘从而导电连接布线基板10。垫片36可安置在第二半导体芯片30上。第三半导体芯片40可安置在垫片36上。第三半导体芯片40采用第四焊线42可引线键合内插芯片24的焊盘从而导电连接第三半导体芯片40到布线基板10。可形成密封剂44以覆盖第一、第二和第三半导体芯片18、30和40、内插芯片24和垫片36。如，密封剂44可为环氧树脂。
在引线键合到内插芯片24的焊盘的第二、第三和第四焊线26、32和42上可进行布线监测。
上文描述的示范实施例中，参考图1，此方法可包括安置第一、第二和第三半导体芯片18、30和40及内插芯片24中的任意一个，和继而引线键合每一个元件。然而，在另一示范实施例中，一种方法可包括直接将第一、第二和第三半导体芯片18、30和40、内插芯片24和垫片36贴装到布线基板10，依赖每一个半导体芯片和/或内插芯片24的尺寸，和同时引线键合。
图3和4为依照一示范实施例的内插芯片的示意图。图5为依照一示范实施例的内插芯片的截面图。图6为传统内插芯片的截面图。
参考图3至5，内插芯片24可包括电路元件，如，二极管54或电容器56。焊盘50可与电路元件相连。电路元件可具有极性且可产生电流流过硅基板80。电路元件可与接地垫52或接地线相连。
参考图3和5，焊盘50可与硅基板80中形成的二极管54相连。二极管54可为包括P阱82(N型杂质)和N+阱(N型杂质)的N-P型二极管。N-P型二极管54可与接地垫52或接地线相连。N-P型二极管54可与焊盘50下方的硅基板80相连。
参考图5，在硅基板80中可形成P阱82。在P阱82中可形成N+阱84，以至于只有P阱82可接地到硅基板80。在焊盘50形成之处下方的基板80的一部分区域可形成N+阱和P阱。P阱82可延伸到接地垫52形成之处的下方。
在硅基板80的表面上可形成层间绝缘层88。在层间绝缘层88上可形成焊盘50和接地垫52。在层间绝缘层88中可形成接触孔栓86以连接N+阱84到焊盘50及P阱82到接地垫52。
焊线可引线键合到焊盘50，且在焊盘50上可施加电压以实行监测引线键合。
如果二极管54为N-P型二极管，如图5所示，可施加在接地垫52上的电压比焊盘50上的更大，产生由接地垫52到焊盘50的电流，从而实现监测引线键合。
如果二极管54为P-N型二极管(没显示)，可施加在焊盘50上的电压比接地垫52上的更大，产生由焊盘50到接地垫52的电流，从而实现监测引线键合。
参考图4，焊盘50可连接硅基板80中形成的电容器56。电容器56可连接接地垫52或接地线。因此，如果焊线引线键合到焊盘50，由于电容器56，接地垫52和焊盘50之间可产生极性，且电流可流经电容器56，从而实现监测引线键合。
相反地，在图6说明的传统内插芯片24a中，硅基板90上可顺序形成绝缘层60和金属层58。焊盘50a可设置在上层上。例如，形成焊盘50a的材料可与金属层58相同。绝缘层60可形成约9000的厚度，且金属层58和/或焊盘50a可形成5700的厚度。
因此，由于传统内插芯片24a包括无极性且不接地的焊盘50a，如果焊线引线键合到焊盘50a，则不会有电流可流过。因而，不能监测引线键合。
依照一示范实施例，图7和8为说明用于堆叠的半导体封装的内插芯片的引线键合监测方法的示意图。
参考图7和8，引线键合装置可包括引线键合监测系统(WBMS)。为方便起见，焊盘50的引线键合监测将参考安置在加热块70上的内插芯片24进行描述。依照一示范实施例如图3和5所示，在图7中，二极管54可与内插芯片24的焊盘50相连接。依照一示范实施例如图6所示，在图8中，电容器56可与内插芯片24的焊盘50相连接。
在图7和8中说明的从引线键合装置的线轴76延长出来的线77通过线夹74可插入毛细管72。插入毛细管72的线77可引线键合内插芯片24的焊盘50，如，通过球焊。在引线键合监测系统中，电流比如直流或交流通过线夹74可施加到线77上。可检测流经电路元件比如二极管54或电容器56的电流或电压以判断焊线是否很好的引线键合焊盘50。因此，可探测出不粘缺陷，例如，焊盘50和焊线的缺陷键合。
参考图7，如上面所描述的在引线键合监测系统78中通过线夹74在线77上可施加直流电。如果在线77上施加直流电，且直流电施加在接地垫52上的电压比焊盘50上的更大，电流可由接地垫52流到焊盘50。电流可反馈到线77和线夹74以检测引线键合监测系统78中的电流或电压以监测引线键合。
在检测电流(或电压)时，可将储存在引线键合监测系统78中的参考电流(或参考电压)与检测电流(或电压)进行比较。可选择地，在引线键合监测系统78中采用多个内插芯片24的焊盘可比较检测电流(或电压)。因此，可判断引线键合是否很好的键合焊盘50。
如果二极管54为P-N型二极管，且通过直流电流施加在焊盘50上的电压比接地垫52上的更大，电流可从焊盘50流到接地垫52。在引线键合监测系统78中采用连接线73，图7中的点线代表，可检测该电流以判断引线键合是否很好的键合焊盘50。
例如，如果通过在内插芯片24的焊盘50上施加直流电实行引线键合监测，二极管54的电阻和电流可分别小于约8兆欧和2μA。
参考图8，在引线键合监测系统78中，通过线夹74可施加交流电到线77上。如果交流电施加到线77上，其间可流过电流的焊盘50和接地垫52之间可具有极性。可检测引线键合监测系统78中反馈给线夹74的电流或电压以监测引线键合。参考图7可实行如前面所描述的检测方法。
通过连接接地垫52的连接线73检测引线键合监测系统78中的电流或电压从而可实行引线键合监测。例如，如果通过在内插芯片24的焊盘50上施加交流电来实行引线键合监测，电容器56的容量可约为15至20pF。
依照示范实施例，通过连接电路元件如二极管或电容器，在堆叠的半导体封装中可实行引线键合监测。该电路元件可具有极性且可产生流向内插芯片的焊盘的电流。
依照示范实施例，堆叠的半导体封装可包括使线可具有极性且可产生流向内插芯片的焊盘的电流的电路元件。因而，可检测不粘缺陷，比如，焊线在引线键合时没有很好的键合。
因此，判断堆叠的半导体封装中所有半导体芯片有缺陷的情况可减少或防止出现，从而提高成品率且减小在下一工序中测试的负担。
虽然已经具体显示和描述了本发明的示范性实施例，然而本领域的一般技术人员可以理解在不脱离本发明的精神和范围的情况下，可以作出形式和细节上的不同变化。
本美国非临时申请要求2006年9月20日于韩国知识产权局(KIPO)申请的韩国专利申请第10-2006-0091143号的优先权，它的公开部分在此处被全文引用作为参考。

Claims (25)

1.一种堆叠的半导体封装，包括：
布线基板；
第一半导体芯片，安置在所述布线基板上且引线键合所述布线基板；
内插芯片，安置在所述第一半导体芯片上且引线键合所述布线基板，所述内插芯片包括导电连接的电路元件和焊盘；以及
第二半导体芯片，安置在所述内插芯片上且引线键合所述内插芯片，所述第二半导体芯片通过所述内插芯片导电连接到所述布线基板上。
2.如权利要求1所述的堆叠的半导体封装，其中所述电路元件与所述内插芯片的接地垫或接地线相连接。
3.如权利要求2所述的堆叠的半导体封装，其中所述电路元件为二极管。
4.如权利要求3所述的堆叠的半导体封装，其中所述二极管包括N型杂质层和P型杂质层。
5.如权利要求3所述的堆叠的半导体封装，其中所述二极管包括：
在所述内插芯片中在所述焊盘和所述接地垫下方形成的P阱，该P阱导电连接所述接地垫，且
在所述P阱中在所述焊盘下方形成的N+阱，该N+阱导电连接所述焊盘。
6.如权利要求3所述的堆叠的半导体封装，其中所述二极管的电阻约小于8兆欧。
7.如权利要求2所述的堆叠的半导体封装，其中所述电路元件为电容器。
8.如权利要求7所述的堆叠的半导体封装，其中所述电容器的容量约为15至20pF。
9.如权利要求1所述的堆叠的半导体封装，其中所述第一半导体芯片、所述内插芯片和所述第二半导体芯片水平堆叠在所述布线基板上。
10.如权利要求1所述的堆叠的半导体封装，其中所述第一半导体芯片、所述内插芯片和所述第二半导体芯片垂直堆叠在所述布线基板上。
11.一种堆叠的半导体封装的制备方法，该方法包括：
在布线基板上安置第一半导体芯片；
引线键合所述第一半导体芯片和所述布线基板；
在所述第一半导体芯片上安置内插芯片，所述内插芯片包括导电连接的电路元件和焊盘；
引线键合所述内插芯片的所述焊盘和所述布线基板；
在所述内插芯片上安置第二半导体芯片；且
引线键合所述第二半导体芯片和所述内插芯片的所述焊盘以导电连接所述第二半导体芯片和所述布线基板。
12.如权利要求11所述的方法，还包括：
连接所述电路元件和所述内插芯片的接地垫或接地线。
13.如权利要求12所述的方法，其中所述电路元件为二极管。
14.如权利要求13所述的方法，其中所述二极管包括N型杂质层和P型杂质层。
15.如权利要求13所述的方法，其中内插芯片的制造方法包括：
在所述内插芯片中在所述焊盘和所述接地垫下方形成P阱，该P阱导电连接所述接地垫，且
在所述P阱中在所述焊盘下方形成N+阱，该N+阱导电连接所述焊盘。
16.如权利要求12所述的堆叠的半导体封装，其中所述电路元件为电容器。
17.如权利要求11所述的方法，其中安置所述第一半导体芯片、所述内插芯片和所述第二半导体芯片包括安置所述第一半导体芯片、所述内插芯片和所述第二半导体芯片水平地堆叠在所述布线基板上。
18.如权利要求11所述的方法，其中安置所述第一半导体芯片、所述内插芯片和所述第二半导体芯片包括安置所述第一半导体芯片、所述内插芯片和所述第二半导体芯片垂直地堆叠在所述布线基板上。
19.一种堆叠的半导体封装的引线键合的监测方法，该方法包括：
在内插芯片的焊盘上施加电流，内插芯片通过引线键合连接到线；
测量与所述内插芯片的所述焊盘相连的所述内插芯片的电路元件的电流或电压之一；且
将内插芯片的电路元件的测量电流或电压分别与参考电流或电压进行比较。
20.如权利要求19所述的方法，其中所述电路元件为二极管，且施加电流包括在所述内插芯片的所述焊盘上施加直流电。
21.如权利要求20所述的方法，其中所述二极管的电阻约小于8兆欧且所述二极管的测量电流约小于2μA。
22.如权利要求19所述的方法，其中所述电路元件为电容器，且施加电流包括在所述内插芯片的所述焊盘上施加交流电。
23.如权利要求22所述的方法，其中所述电容器的容量约为15至20pF。
24.如权利要求19所述的方法，其中所述参考电流或电压为存储值。
25.如权利要求19所述的方法，其中所述参考电流或电压为从导电连接所述内插芯片的第二焊盘的第二电路元件探测到的电流或电压。
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