CN110914982A - 背面偏置式半导体管芯的接地技术以及相关的设备、系统和方法 - Google Patents
背面偏置式半导体管芯的接地技术以及相关的设备、系统和方法 Download PDFInfo
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Abstract
本发明提供了半导体设备,该半导体设备可以包括衬底和支撑在衬底上方的背面偏置式半导体管芯。背面偏置式半导体管芯的背面表面可以与衬底隔开。背面表面可以通过延伸到衬底的线接合件电连接到接地。制造半导体设备的方法可以涉及将背面偏置式半导体管芯支撑在衬底上方,背面偏置式半导体管芯的背面表面与衬底隔开。背面表面可以通过延伸到衬底的线接合件电连接到接地。系统可以包括传感器设备、非暂态存储器设备以及可操作地连接到其的至少一个半导体设备。至少一个半导体设备可以包括衬底和支撑在衬底上方的背面偏置式半导体管芯。背面偏置式半导体管芯的背面表面可以通过延伸到衬底的线接合件电连接到接地。
Description
优先权要求
本申请根据35 U.S.C.§119(e)要求于2017年2月10日提交的美国临时专利申请序列号62/457,490的权益,其公开内容全文以引用方式并入本文。
技术领域
本公开整体涉及半导体设备和制造半导体设备的方法。更具体地,所公开的实施方案涉及用于将背面偏置式半导体管芯接地的技术、可以实现背面偏置式半导体管芯的倒装芯片取向和堆叠的方法、所得的半导体设备和包含此类半导体设备的系统。
背景技术
半导体设备可以是“背面偏置式的”,意味着设备可以包括位于半导体设备的有源表面和半导体设备的背面表面之间的介电材料区域。随着电流由嵌入在有源表面内或位于有源表面上的集成电路处理,介电材料可以使半导体设备作为电容器进行操作,其中电荷在背面表面处积聚在半导体设备的半导体材料中。所积聚的电荷可能不期望地与集成电路交互作用,导致半导体设备以非预期的方式运行或甚至损坏半导体设备。
附图说明
虽然本公开以特别指出并清楚地要求保护具体实施方案的权利要求书作为结尾,但当结合附图阅读时,通过以下描述可更容易地确定本公开范围内的实施方案的各种特征和优点,在附图中:
图1是包括呈倒装芯片配置的背面偏置式半导体管芯的半导体设备的横截面侧视图;
图2是包括呈倒装芯片配置的背面偏置式半导体管芯的半导体设备的另一实施方案的横截面侧视图;
图3是包括堆叠的背面偏置式半导体管芯的半导体设备的横截面侧视图;
图4是包括堆叠的背面偏置式半导体管芯的半导体设备的另一实施方案的横截面侧视图;并且
图5是包括根据本公开的半导体设备的系统的示意图。
具体实施方式
本公开中呈现的图示并不意味着是任何特定半导体设备、包括半导体设备的系统或其部件的实际视图,而仅仅是用来描述示例性实施方案的理想化表示。因此,附图不一定按比例绘制。
所公开的实施方案整体涉及用于将背面偏置式半导体管芯接地的技术以及可以实现背面偏置式半导体管芯的倒装芯片取向和堆叠的相关方法。更具体地,公开了可以包括呈倒装芯片配置的背面偏置式半导体管芯的半导体设备的实施方案,包括从半导体管芯的背面表面附近延伸到电接地的线接合件。作为另一具体示例,公开了可以包括电连接到背面偏置式半导体管芯的背面表面的接地中介层的半导体设备的实施方案,其中接地中介层可以包括从接地中介层延伸到电接地的线接合件。
如本文所用,关于给定参数、属性或条件的术语“基本上”和“约”是指并且包括本领域普通技术人员将理解给定参数、属性或条件满足方差程度(诸如,在可接受的制造公差范围内)的程度。例如,基本上或约为指定值的参数可以是指定值的至少约90%、指定值的至少约95%、指定值的至少约99%或甚至指定值的至少约99.9%。
参考图1,示出了包括呈倒装芯片配置的背面偏置式半导体管芯102的半导体设备100的横截面侧视图。背面偏置式半导体管芯102可以包括有源表面104和位于半导体管芯102的与有源表面104相对的一侧上的背面表面106。有源表面104可以包括在有源表面104处嵌入半导体管芯102的半导体材料内和/或位于该半导体材料上的集成电路。背面表面106可以不含这种集成电路。半导体管芯102可以包括位于半导体管芯102内的在有源表面104和背面表面106之间的绝缘材料108。绝缘材料108可以在半导体管芯102的相对横向侧上的侧表面107和109之间横向延伸,使得绝缘材料108可以在有源表面104和背面表面106之间纵向地形成电屏障。绝缘材料108可以呈例如层的形式,并且可以包括例如半导体管芯102的半导体材料的氧化区域(例如,当半导体管芯102包含硅材料时的氧化硅)。作为具体的非限制性示例,半导体管芯102可以是绝缘体上硅(SOI)设备,其包括由电绝缘衬底(例如,玻璃衬底)承载的硅层。半导体管芯102可以是背面偏置式的,以降低嵌入在有源表面104内的集成电路的操作与绝缘材料108之间的交互作用可导致在绝缘材料108和背面表面106之间在半导体管芯102的区域116中形成不需要的电荷的可能性,这可以在没有这种背面偏置的情况下导致非预期的交互作用或损坏。
半导体管芯102可以可操作地连接到衬底110并且支撑在该衬底上。半导体管芯102的有源表面104可以面向衬底110,使得半导体管芯102以倒装芯片的方式附接到衬底110。半导体管芯102的背面表面106可以与衬底110隔开大于或等于半导体管芯102的厚度(如从有源表面104到背面表面106所测量)的距离。呈例如凸块、球、柱或螺柱形式的导电元件112可以将半导体管芯102的有源表面104电气地和机械地连接到衬底。
背面表面106可以有利地电连接到接地或者其他基准或偏置电压114(例如,电连接到从中可以测量半导体设备100中的其他电压的基准电压、电连接到电流的返回路径或电连接到电能的接收器)。如本文所用,术语“接地”意指并包括常规接地以及其他施加的基准或偏置电压。将背面表面106连接到接地114可以使得在绝缘材料108和背面表面106之间在半导体管芯102的区域116中以其他方式形成的不需要的电荷能够耗散,从而降低这种不需要的电荷可能导致非预期的交互作用或损坏的可能性。
为了将背面表面106电连接到接地114,可以将导电材料118置于与背面表面106电接触。如图1所示,导电材料118可以采取直接位于半导体管芯102的与有源表面104相对的一侧上的背面表面106上的导电材料118的质量块120的形式。更具体地,导电材料118可以覆盖例如背面表面106的至少一部分,直到(并且包括)覆盖整个背面表面106。作为具体的非限制性示例,导电材料118可以覆盖背面表面106的约10%至约100%之间、约50%至约100%之间或约75%至约100%之间。导电材料118可以是单个连续质量块120(如图1所示),或者可以在背面表面106上分成导电材料118的几个离散质量块。在其他实施方案中,导电材料118可以采取例如接地中介层的各种实施方式的形式,如结合图2至图4更详细地示出和描述。导电材料118的质量块120可以通过例如镀覆(例如,电镀、无电镀、化学镀等)、化学气相沉积(CVD)工艺、通过作为预成形膜的应用,或者通过溅射(即,物理气相沉积)工艺定位在背面表面106上。导电材料118的质量块120可以包括例如导电金属或金属合金。作为具体的非限制性示例,质量块120可以包含铜、金、铝或包含此类金属的合金。
一个或多个线接合件122可以从导电材料118延伸到衬底110,以将背面表面106电连接到接地114。更具体地,每个线接合件122都可以例如从导电材料118的质量块120(或对应的离散质量块)延伸到位于衬底110的面向半导体管芯102的表面117上的导电元件115。作为具体的非限制性示例,线接合件122可以从导电材料118延伸到衬底110的表面117上的接合焊盘、迹线、通孔或其他导电结构形式的导电元件115。半导体管芯102、导电材料118的质量块102、线接合件122、导电元件112、接地114处的导电元件115和衬底110的上表面117可以嵌入在介电密封剂材料124内。
图2是包括呈倒装芯片配置的背面偏置式半导体管芯102的半导体设备130的另一实施方案的横截面侧视图。在一些实施方案中,诸如图2中所示的实施方案,接地中介层132可以电连接到半导体管芯102的背面表面106,而不是将导电材料118的质量块120(参见图1)直接定位在背面表面106上。接地中介层132可以包括例如导电材料118的板134(如图2所示)、印刷电路板、半导体芯片、重新分布层、引线框架或者可以电连接到半导体管芯102的背面表面106以将背面表面106电连接到接地114的任何其他合适的设备或结构。接地中介层132可以横向延伸超出半导体管芯102的横向侧表面107和109(如图2所示),并且超出与其垂直的其他横向侧表面(未示出)。在其他实施方案中,接地中介层132可以延伸成与半导体管芯102的横向侧表面107和109横向齐平,或者半导体管芯102的横向侧表面107和109可以横向延伸超出接地中介层132。
接地中介层132可以通过例如导电粘合剂材料136机械地和电气地连接到半导体管芯102的背面表面106。导电粘合剂材料136可以定位成与半导体管芯102的背面表面106和接地中介层132直接接触并插置在它们之间。导电粘合剂材料136可以包含例如导电环氧树脂、导体填充环氧树脂、导电膏、导电底部填充物、导电密封剂或其他粘合剂材料。作为具体的非限制性示例,导电粘合剂材料136可以包含双马来酰亚胺-三嗪环氧树脂。
线接合件122可以从位于接地中介层132的与半导体管芯102相对的一侧上的上表面133延伸。在其中线接合件122被配置为柔性电连接件(例如,导电材料的带)的实施方案中,线接合件122可以从位于接地中介层132的面向半导体管芯102的一侧上的下表面135,或者从接地中介层132的上表面133和下表面135两者延伸到衬底110处的接地114。具体地,在其中线接合件122从接地中介层132的上表面133延伸的实施方案中,这些线接合件可以从接地中介层132上的横向超出横向侧表面107和109定位的位置(如图2所示),或者从位于横向侧表面107和109的横向界限之间的位置延伸。
图3是包括第一偏置式半导体管芯102和堆叠的背面偏置式半导体管芯142两者的半导体设备140的横截面侧视图。半导体设备140可以包括第一半导体管芯102,该第一半导体管芯以与结合图2所示和所述至少基本上相同的方式配置。第二半导体管芯142可以位于接地中介层132的与第一半导体管芯102相对的一侧上。第二半导体管芯142同样可以是背面偏置式的,并且可以包括有源表面144、位于第二半导体管芯142的与有源表面144相对的一侧上的背面表面146、以及在有源表面144和背面表面146之间位于半导体管芯142的材料内的电绝缘材料148。有源表面144可以包括在有源表面144处嵌入第二半导体管芯142的半导体材料内或位于该半导体材料上的集成电路。背面表面146可以不含这种集成电路。电绝缘材料148可以在第二半导体管芯142的相对横向侧上的侧表面143和145之间横向延伸,使得绝缘材料148可以在有源表面144和背面表面146之间纵向地形成电屏障。电绝缘材料148可以呈例如层的形式,并且可以包含例如第二半导体管芯142的半导体材料的氧化区域(例如,当第二半导体管芯142包含硅材料时的氧化硅)。作为具体的非限制性示例,第二半导体管芯142可以是绝缘体上硅(SOI)设备。
第二半导体管芯142的背面表面146可以通过第二导电粘合剂材料150机械地和电气地连接到接地中介层132。例如,第一半导体管芯102的背面表面106可以机械地和电气地连接到接地中介层132的与第二半导体管芯142相对的一侧上的下表面135,并且第二半导体管芯142的背面表面146可以通过第二导电粘合剂材料150机械地和电气地连接到接地中介层132的与第一半导体管芯102相对的一侧上的上表面133,使得接地中介层132插置在第一半导体管芯102和第二半导体管芯142之间。在这种布置中,第一半导体管芯102的背面表面106可以面向第二半导体管芯142的背面表面146,并且第一半导体管芯102的有源表面104可以背向第二半导体管芯142的有源表面146。更具体地,第一半导体管芯102的有源表面104可以面向衬底110,第一半导体管芯102的背面表面106可以面向接地中介层132,第二半导体管芯142的背面表面146可以面向接地中介层132、第一半导体管芯102和衬底110,并且第二半导体管芯142的有源表面144可以位于半导体管芯142的与接地中介层132、第一半导体管芯102和衬底110相对的一侧上。
第二导电粘合剂材料150可以是与第一导电粘合剂材料136相同的材料或不同的材料。第二导电粘合剂材料150可以包含先前结合第一导电粘合剂材料136所描述的材料中的任一种。
在一些实施方案中,诸如图3中所示的实施方案,第一半导体管芯102的侧表面107和109可以与第二半导体管芯142的侧表面143和145至少基本上横向齐平。在其他实施方案中,侧表面107和109以及与其垂直的第一半导体管芯102的其他侧表面中的一个、一些或全部可以横向延伸超出第二半导体管芯142的对应的侧表面143和145,并且第二半导体管芯142的侧表面143和145中的一个、一些或全部可以横向延伸超出第一半导体管芯102的对应的侧表面107和109。
在一些实施方案中,诸如图3中所示的实施方案,接地中介层132可以横向延伸超出第一半导体管芯102的侧表面107和109并且横向延伸超出第二半导体管芯142的侧表面143和145。在其他实施方案中,接地中介层132可以延伸成与第一半导体管芯102的侧表面107和109、第二半导体管芯142的侧表面143和145或两者横向齐平;或者可以仅在第一半导体管芯109的侧表面107和109、半导体管芯142的侧表面143和145或两者的界限内横向延伸。图3中所示的接地中介层132可以包括例如半导体芯片152,该半导体芯片具有在其相对的纵向侧之间延伸的导电通孔154,以便为第一半导体管芯102的背面表面106和第二半导体管芯142的背面表面146提供电连接和接地。电连接到通孔154的接地线接合件122可以从接地中介层132延伸到衬底110,以将第一半导体管芯102的背面表面106和第二半导体管芯142的背面表面146接地。操作性线接合件156可以从第二半导体管芯142的有源表面144延伸到衬底110,以使得能够操作地连接到嵌入在第二半导体管芯142的有源表面144内的电路。更具体地,操作性线接合件156可以从可操作地连接到嵌入在第二半导体管芯142的有源表面144内的接合焊盘147,横向超出第二半导体管芯142的侧表面143和145,延伸到衬底110的表面117上的接合焊盘、迹线、通孔或其他导电结构形式的导电元件119。在一些实施方案中,诸如图3中所示的实施方案,操作性线接合件156可以从第二半导体管芯142的横向周边处的接地线接合件122的上方,横向超出接地线接合件122,延伸到衬底110,使得当从图3所示的透视图观察时,操作性线接合件156和接地线接合件122可以不垂直于其中操作性线接合件156和接地线接合件122延伸的横向方向彼此交叉。在其他实施方案中,随着接地线接合件122横向地和纵向地延伸到衬底110,操作性线接合件156可以从第二半导体管芯142的横向周边处的接地线接合件122的上方,纵向延伸穿过接地线接合件122,使得当从图3所示的透视图观察时,操作性线接合件156和接地线接合件122可以垂直于其中操作性线接合件156和接地线接合件122延伸的横向方向彼此交叉。在此类实施方案中,接地线接合件122和操作性线接合件156可以在垂直于其横向延伸方向的方向上彼此偏移,以减小接地线接合件122和操作性线接合件156可以彼此不期望地接触和电短路的可能性。
图4是包括堆叠的背面偏置式半导体管芯142的半导体设备160的另一实施方案的横截面侧视图。在图4中,第二堆叠的半导体管芯142可以与先前结合图3所描述的半导体管芯142至少基本上类似地配置。图4中所示的第一半导体管芯162可以不处于倒装芯片取向。例如,第一半导体管芯162可以包括有源表面164和位于第一半导体管芯162的与有源表面164相对的一侧上的背面表面166。有源表面164可以包括在有源表面164处嵌入在第一半导体管芯162的半导体材料内的集成电路。背面表面166可以不含这种集成电路。在图4中所示的实施方案中,第一半导体管芯162可以不是背面偏置式的,并且可以不含在有源表面164和背面表面166之间嵌入在第一半导体管芯162的材料内的任何绝缘材料。在其他实施方案中,第一半导体管芯162可以是背面偏置式的。
第一半导体管芯162的背面表面166可以直接支撑在衬底110的上表面117上,并且第一半导体管芯162的有源表面164可以背向衬底110并且面向接地中介层132。背面表面166可以通过粘合剂材料168机械地固定到衬底110。在其中第一半导体管芯162不是背面偏置式的诸如图4中所示的实施方案中,粘合剂材料168可以不是导电的,并且可以包括与将第二半导体管芯142的背面表面146机械地和电气地连接到接地中介层132的导电粘合剂材料150不同的材料。在其中第一半导体管芯162是背面偏置式的其他实施方案中,粘合剂材料168可以是导电的,以将第一半导体管芯162的背面表面166电连接到衬底110处的接地114,并且可以包含与导电粘合剂材料150相同或不同的材料。
操作性线接合件170可以从第一半导体管芯162的有源表面164延伸到衬底110,以使得能够操作地连接到嵌入在第一半导体管芯162的有源表面164内的电路。更具体地,操作性线接合件170可以从可操作地连接到嵌入在第一半导体管芯162的有源表面164内的接合焊盘171,横向超出第一半导体管芯162的侧表面161和163,延伸到衬底110的表面117上的接合焊盘、迹线、通孔或其他导电结构形式的导电元件119。在一些实施方案中,诸如图4中所示的实施方案,操作性线接合件170中的一些可以从第一半导体管芯162的横向周边处的接地线接合件122的下方,横向地在接地线接合件122的界限内,延伸到衬底110,使得当从图4所示的透视图观察时,操作性线接合件170和接地线接合件122中的一些可以不垂直于其中操作性线接合件170和接地线接合件122延伸的横向方向彼此交叉。随着接地线接合件122横向地和纵向地延伸到衬底110,操作性线接合件170中的其他可以从第一半导体管芯162的横向周边处的接地线接合件122的下方横向延伸穿过接地线接合件122。
间隔件172可以插置在第一半导体管芯162和接地中介层132之间,以便为操作性线接合件170提供空间。间隔件172可以在接地中介层132的与第二半导体管芯142相对的一侧上固定到接地中介层132中的每一个;并且通过粘合剂材料174固定到第一半导体管芯162的有源表面164,该粘合剂材料可以不是导电的。间隔件172可以包含介电材料,例如非导电聚合物材料。
图5是包括根据本公开的一个或多个半导体设备100、130、140、160的系统180的示意图。例如,系统180可以包括控制单元182和探头单元184。
探头单元184可以包括传感器设备186,该传感器设备被配置为生成表示检测到的物理现象并且响应于检测到的物理现象的电信号。探头单元184可以是便携式设备,例如手持设备。在一些实施方案中,探头单元184可以包括位于探头单元184内的根据本公开的半导体设备100、130、140、160,半导体设备100、130、140、160被配置为至少部分地处理局部在探头单元184内的电信号。探头单元184可以可操作地连接到控制单元182(例如,通过有线或无线连接),并且可以将原始的、部分处理的或完全处理的电信号发送到控制单元182。在一些实施方案中,控制单元182可以包括根据本公开的另一半导体设备100、130、140、160或者可处理或进一步处理电信号的微处理器188。控制单元182可以包括非暂态存储器设备190,该非暂态存储器设备被配置为存储完全处理的电信号的结果。控制单元182可以任选地包括输出设备192(例如,电子显示器、音频扬声器、打印机等),该输出设备被配置为输出完全处理的电信号的结果。
当在医疗设备(例如,超声设备)中实现时,根据本公开的半导体设备100、130、140、160可能特别有用。根据本公开的半导体设备100、130、140、160所实现的外形薄、重量轻、功率低和电子稳定的构造可以使此类系统180更小、更易于运输,并且可以产生对感测到的现象的更高保真度的表示,因为根据本公开的半导体设备100、130、140、160可以减少与感测装备的交互作用。
因此,半导体设备可以包括衬底和背面偏置式半导体管芯。背面偏置式半导体管芯的背面表面可以与衬底隔开并且通过延伸到衬底的一个或多个线接合件电连接到接地。
制造半导体设备的方法可以涉及支撑背面偏置式半导体管芯,其中该背面偏置式半导体管芯的背面表面与衬底隔开。背面表面可以通过延伸到衬底的一个或多个线接合件电连接到接地。
系统可以包括传感器设备、非暂态存储器设备以及可操作地连接到其的至少一个半导体设备。至少一个半导体设备可以包括衬底和背面偏置式半导体管芯。背面偏置式半导体管芯的背面表面可以通过延伸到衬底的一个或多个线接合件电连接到接地。
虽然已经结合附图描述了某些示例性实施方案,但本领域普通技术人员将认识并理解,本公开的范围不限于在本公开中明确示出和描述的那些实施方案。相反,可以对本公开中描述的实施方案进行许多添加、删除和修改以产生本公开范围内的实施方案,诸如具体权利要求书保护的实施方案,包括合法等同物。此外,来自一个所公开的实施方案的特征可与另一个所公开的实施方案的特征组合,同时仍被包括在发明人所设想的本公开的范围内。
权利要求书(按照条约第19条的修改)
1.一种半导体设备,包括:
衬底;和
背面偏置式半导体管芯,所述背面偏置式半导体管芯包括:有源表面,所述有源表面具有嵌入在所述有源表面内的集成电路;背面表面,所述背面表面不含位于所述背面偏置式半导体管芯的与所述有源表面相对的一侧上的集成电路;和绝缘材料,所述绝缘材料插置在所述有源表面和所述背面表面之间,所述背面偏置式半导体管芯的所述背面表面与所述衬底隔开并通过延伸到所述衬底的一个或多个线接合件电连接到接地。
2.根据权利要求1所述的半导体设备,其中所述线接合件从直接位于所述背面偏置式半导体管芯的所述背面表面上的导电材料的质量块延伸到所述衬底。
3.根据权利要求1所述的半导体设备,其中所述线接合件从接地中介层延伸到所述衬底,所述接地中介层通过导电粘合剂材料机械地和电气地连接到所述背面偏置式半导体管芯的所述背面表面。
4.根据权利要求3所述的半导体设备,其中所述接地中介层横向延伸超出所述背面偏置式半导体管芯的至少一些侧表面。
5.根据权利要求3所述的半导体设备,其中所述背面偏置式半导体管芯处于倒装芯片取向,所述背面偏置式半导体管芯的有源表面面向所述衬底,所述接地中介层位于所述背面偏置式半导体管芯的与所述衬底相对的一侧上。
6.根据权利要求5所述的半导体设备,还包括位于所述接地中介层的与所述衬底相对的一侧上的另一背面偏置式半导体管芯,所述另一背面偏置式半导体管芯的背面表面通过另一导电粘合剂材料机械地和电气地连接到所述接地中介层。
7.根据权利要求6所述的半导体设备,其中所述另一背面偏置式半导体管芯的有源表面通过从所述有源表面延伸到至少一个导电元件的至少一个操作性线接合件电连接到所述衬底的所述至少一个导电元件。
8.根据权利要求3所述的半导体设备,其中所述背面偏置式半导体管芯堆叠在另一半导体管芯上方,所述接地中介层插置在所述背面偏置式半导体管芯和所述另一半导体管芯之间。
9.根据权利要求8所述的半导体设备,还包括间隔件,所述间隔件插置在所述另一半导体管芯和所述接地中介层之间。
10.根据权利要求8所述的半导体设备,其中所述另一半导体管芯的有源表面面向所述接地中介层。
11.根据权利要求10所述的半导体设备,其中所述另一半导体管芯的所述有源表面通过从所述有源表面延伸到至少一个导电元件的至少一个操作性线接合件电连接到所述衬底的所述至少一个导电元件。
12.一种制造半导体设备的方法,包括:
将背面偏置式半导体管芯支撑在衬底上方,所述背面偏置式半导体管芯包括:有源表面,所述有源表面具有嵌入在所述有源表面内的集成电路;背面表面,所述背面表面不含位于所述背面偏置式半导体管芯的与所述有源表面相对的一侧上的集成电路;和绝缘材料,所述绝缘材料插置在所述有源表面和所述背面表面之间,所述背面偏置式半导体管芯的所述背面表面与所述衬底隔开;以及
通过延伸到所述衬底的线接合件将所述背面表面电连接到接地。
13.根据权利要求12所述的方法,还包括将所述线接合件从直接位于所述背面偏置式半导体管芯的所述背面表面上的导电材料的质量块连接到所述衬底。
14.根据权利要求12所述的方法,还包括将所述线接合件连接到接地中介层,所述接地中介层通过导电粘合剂材料机械地和电气地连接到所述背面偏置式半导体管芯的所述背面表面。
15.根据权利要求14所述的方法,其中将所述背面偏置式半导体管芯支撑在所述衬底上方包括将所述背面偏置式半导体管芯以倒装芯片取向支撑在所述衬底上方,所述背面偏置式半导体管芯的有源表面面向所述衬底,并且还包括将所述接地中介层放置在所述背面偏置式半导体管芯的与所述衬底相对的一侧上。
16.根据权利要求15所述的方法,还包括将另一背面偏置式半导体管芯支撑在所述接地中介层的与所述衬底相对的一侧上,所述另一背面偏置式半导体管芯的背面表面通过另一导电粘合剂材料机械地和电气地连接到所述接地中介层。
17.根据权利要求14所述的方法,其中将所述背面偏置式半导体管芯支撑在所述衬底上方包括将所述背面偏置式半导体管芯堆叠在另一半导体管芯上方,所述接地中介层插置在所述背面偏置式半导体管芯和所述另一半导体管芯之间。
18.根据权利要求17所述的方法,还包括将所述间隔件放置在所述另一半导体管芯和所述接地中介层之间。
19.根据权利要求17所述的方法,还包括将所述另一半导体管芯的有源表面取向为面向所述接地中介层。
20.一种系统,包括:
传感器设备;
非暂态存储器设备;和
根据权利要求1所述的至少一个半导体设备,所述至少一个半导体设备能够操作地连接到所述传感器设备和所述非暂态存储器设备。
Claims (20)
1.一种半导体设备,包括:
衬底;和
背面偏置式半导体管芯,所述背面偏置式半导体管芯的背面表面与所述衬底隔开并通过延伸到所述衬底的一个或多个线接合件电连接到接地。
2.根据权利要求1所述的半导体设备,其中所述线接合件从直接位于所述背面偏置式半导体管芯的所述背面表面上的导电材料的质量块延伸到所述衬底。
3.根据权利要求1所述的半导体设备,其中所述线接合件从接地中介层延伸到所述衬底,所述接地中介层通过导电粘合剂材料机械地和电气地连接到所述背面偏置式半导体管芯的所述背面表面。
4.根据权利要求3所述的半导体设备,其中所述接地中介层横向延伸超出所述背面偏置式半导体管芯的至少一些侧表面。
5.根据权利要求3所述的半导体设备,其中所述背面偏置式半导体管芯处于倒装芯片取向,所述背面偏置式半导体管芯的有源表面面向所述衬底,所述接地中介层位于所述背面偏置式半导体管芯的与所述衬底相对的一侧上。
6.根据权利要求5所述的半导体设备,还包括位于所述接地中介层的与所述衬底相对的一侧上的另一背面偏置式半导体管芯,所述另一背面偏置式半导体管芯的背面表面通过另一导电粘合剂材料机械地和电气地连接到所述接地中介层。
7.根据权利要求6所述的半导体设备,其中所述另一背面偏置式半导体管芯的有源表面通过从所述有源表面延伸到至少一个导电元件的至少一个操作性线接合件电连接到所述衬底的所述至少一个导电元件。
8.根据权利要求3所述的半导体设备,其中所述背面偏置式半导体管芯堆叠在另一半导体管芯上方,所述接地中介层插置在所述背面偏置式半导体管芯和所述另一半导体管芯之间。
9.根据权利要求8所述的半导体设备,还包括间隔件,所述间隔件插置在所述另一半导体管芯和所述接地中介层之间。
10.根据权利要求8所述的半导体设备,其中所述另一半导体管芯的有源表面面向所述接地中介层。
11.根据权利要求10所述的半导体设备,其中所述另一半导体管芯的所述有源表面通过从所述有源表面延伸到至少一个导电元件的至少一个操作性线接合件电连接到所述衬底的所述至少一个导电元件。
12.一种制造半导体设备的方法,包括:
将背面偏置式半导体管芯支撑在衬底上方,所述背面偏置式半导体管芯的背面表面与所述衬底隔开;以及
通过延伸到所述衬底的线接合件将所述背面表面电连接到接地。
13.根据权利要求12所述的方法,还包括将所述线接合件从直接位于所述背面偏置式半导体管芯的所述背面表面上的导电材料的质量块连接到所述衬底。
14.根据权利要求12所述的方法,还包括将所述线接合件连接到接地中介层,所述接地中介层通过导电粘合剂材料机械地和电气地连接到所述背面偏置式半导体管芯的所述背面表面。
15.根据权利要求14所述的方法,其中将所述背面偏置式半导体管芯支撑在所述衬底上方包括将所述背面偏置式半导体管芯以倒装芯片取向支撑在所述衬底上方,所述背面偏置式半导体管芯的有源表面面向所述衬底,并且还包括将所述接地中介层放置在所述背面偏置式半导体管芯的与所述衬底相对的一侧上。
16.根据权利要求15所述的方法,还包括将另一背面偏置式半导体管芯支撑在所述接地中介层的与所述衬底相对的一侧上,所述另一背面偏置式半导体管芯的背面表面通过另一导电粘合剂材料机械地和电气地连接到所述接地中介层。
17.根据权利要求14所述的方法,其中将所述背面偏置式半导体管芯支撑在所述衬底上方包括将所述背面偏置式半导体管芯堆叠在另一半导体管芯上方,所述接地中介层插置在所述背面偏置式半导体管芯和所述另一半导体管芯之间。
18.根据权利要求17所述的方法,还包括将间隔件放置在所述另一半导体管芯和所述接地中介层之间。
19.根据权利要求17所述的方法,还包括将所述另一半导体管芯的有源表面取向为面向所述接地中介层。
20.一种系统,包括:
传感器设备;
非暂态存储器设备;和
至少一个半导体设备,所述至少一个半导体设备能够操作地连接到所述传感器设备和所述非暂态存储器设备,所述至少一个半导体设备包括:
衬底;和
背面偏置式半导体管芯,所述背面偏置式半导体管芯的背面表面与所述衬底隔开,所述背面表面通过延伸到所述衬底的一个或多个线接合件电连接到接地。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121070A (en) * | 1996-12-03 | 2000-09-19 | Micron Technology, Inc. | Flip chip down-bond: method and apparatus |
US20040113253A1 (en) * | 2002-10-08 | 2004-06-17 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
US20100013066A1 (en) * | 2007-10-11 | 2010-01-21 | Yong-Hoon Kim | Semiconductor package |
CN101809733A (zh) * | 2007-09-26 | 2010-08-18 | 费查尔德半导体有限公司 | 层叠双管芯封装及其制造方法以及纳入该封装的系统 |
US20150130053A1 (en) * | 2013-11-08 | 2015-05-14 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6297550B1 (en) * | 1998-04-01 | 2001-10-02 | Lsi Logic Corporation | Bondable anodized aluminum heatspreader for semiconductor packages |
JP3565319B2 (ja) * | 1999-04-14 | 2004-09-15 | シャープ株式会社 | 半導体装置及びその製造方法 |
US7176506B2 (en) * | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
WO2004080134A2 (en) | 2003-02-25 | 2004-09-16 | Tessera, Inc. | High frequency chip packages with connecting elements |
US7763963B2 (en) * | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
KR100703090B1 (ko) | 2005-08-30 | 2007-04-06 | 삼성전기주식회사 | 후면 접지형 플립칩 반도체 패키지 |
US7485969B2 (en) * | 2005-09-01 | 2009-02-03 | Micron Technology, Inc. | Stacked microelectronic devices and methods for manufacturing microelectronic devices |
DE102005055761B4 (de) * | 2005-11-21 | 2008-02-07 | Infineon Technologies Ag | Leistungshalbleiterbauelement mit Halbleiterchipstapel in Brückenschaltung und Verfahren zur Herstellung desselben |
US7592672B2 (en) * | 2006-03-30 | 2009-09-22 | Casio Computer Co., Ltd. | Grounding structure of semiconductor device including a conductive paste |
KR100809693B1 (ko) | 2006-08-01 | 2008-03-06 | 삼성전자주식회사 | 하부 반도체 칩에 대한 신뢰도가 개선된 수직 적층형멀티칩 패키지 및 그 제조방법 |
KR100761860B1 (ko) | 2006-09-20 | 2007-09-28 | 삼성전자주식회사 | 와이어 본딩 모니터링이 가능한 인터포저 칩을 갖는 적층반도체 패키지 및 이의 제조방법 |
US9368429B2 (en) * | 2011-10-25 | 2016-06-14 | Intel Corporation | Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips |
US20130277855A1 (en) * | 2012-04-24 | 2013-10-24 | Terry (Teckgyu) Kang | High density 3d package |
WO2014167871A1 (ja) | 2013-04-10 | 2014-10-16 | 株式会社村田製作所 | 半導体装置 |
US9678490B2 (en) * | 2014-06-23 | 2017-06-13 | Dell Products L.P. | Systems and methods for temperature-based performance optimization of memory devices |
US20190326249A1 (en) * | 2016-12-29 | 2019-10-24 | Intel Corporation | Multi-point stacked die wirebonding for improved power delivery |
-
2018
- 2018-02-08 DE DE112018000762.6T patent/DE112018000762T5/de active Pending
- 2018-02-08 CN CN201880018770.5A patent/CN110914982A/zh active Pending
- 2018-02-08 WO PCT/US2018/017469 patent/WO2018148444A1/en active Application Filing
- 2018-02-08 US US15/891,775 patent/US10741507B2/en active Active
- 2018-02-09 TW TW107104781A patent/TW201901882A/zh unknown
-
2020
- 2020-08-05 US US16/947,530 patent/US11476208B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6121070A (en) * | 1996-12-03 | 2000-09-19 | Micron Technology, Inc. | Flip chip down-bond: method and apparatus |
US20040113253A1 (en) * | 2002-10-08 | 2004-06-17 | Chippac, Inc. | Semiconductor stacked multi-package module having inverted second package |
CN101809733A (zh) * | 2007-09-26 | 2010-08-18 | 费查尔德半导体有限公司 | 层叠双管芯封装及其制造方法以及纳入该封装的系统 |
US20100013066A1 (en) * | 2007-10-11 | 2010-01-21 | Yong-Hoon Kim | Semiconductor package |
US20150130053A1 (en) * | 2013-11-08 | 2015-05-14 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
Also Published As
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US20180233463A1 (en) | 2018-08-16 |
WO2018148444A1 (en) | 2018-08-16 |
DE112018000762T5 (de) | 2019-12-19 |
US10741507B2 (en) | 2020-08-11 |
TW201901882A (zh) | 2019-01-01 |
US11476208B2 (en) | 2022-10-18 |
US20200365530A1 (en) | 2020-11-19 |
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