CN101809733A - 层叠双管芯封装及其制造方法以及纳入该封装的系统 - Google Patents

层叠双管芯封装及其制造方法以及纳入该封装的系统 Download PDF

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CN101809733A
CN101809733A CN200880109392A CN200880109392A CN101809733A CN 101809733 A CN101809733 A CN 101809733A CN 200880109392 A CN200880109392 A CN 200880109392A CN 200880109392 A CN200880109392 A CN 200880109392A CN 101809733 A CN101809733 A CN 101809733A
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semiconductor element
substrate
semiconductor
attached
die package
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CN200880109392A
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English (en)
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Y·刘
H·艾伦
钱秋晓
J·居
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Publication of CN101809733A publication Critical patent/CN101809733A/zh
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Abstract

一种半导体管芯封装。它包括：具有第一表面和第二表面的衬底；第一半导体管芯，其正面面对着衬底的第一表面；设置在第一半导体管芯和衬底的第一表面之间的导电粘合剂；以及位于第一半导体管芯上的第二半导体管芯。第二半导体管芯的正面面朝着远离第一半导体管芯的方向，并且背面面朝着第一半导体管芯。多个导电结构将第二半导体管芯的正面处的区域电耦合到衬底的第一表面处的导电区域。

Description

层叠双管芯封装及其制造方法以及纳入该封装的系统
有关申请的交叉参照
无
背景技术
小型半导体管芯封装正越来越多地被用在便携式电子设备中，比如无线电话、MP3播放器、无线头戴式耳机等。作为一般的趋势，这种设备正变得尺寸越来越小而功能越来越多。这些趋势通常是矛盾的，因为功能的增多通常需要增加部件数目和部件布线。期望提供一些方式能缓减这些相互矛盾的趋势，使得两者均能不被牺牲而继续发展。
发明内容
作为本发明的一部分，发明人已认识到，设备设计者通常使用信号处理电路和功率控制电路的组合从而在便携式电子设备中实现新的功能，其中信号处理电路可以是模拟电路、数字电路或它们的组合。处理电路和功率控制电路通常被隔离在分开的半导体管芯上，或者可以被隔离开。发明人也已认识到，设备设计者通常使用模拟电路和数字电路的组合从而在便携式电子设备中实现新的功能，其中模拟电路和数字电路通常被隔离在分开的半导体管芯上。已经发现，如果可以使用单个半导体管芯封装来使多个电路的组合互连起来而不增大该封装的物理尺寸，则上述的电路组合就能被实现在更小的空间中。
相应地，本发明的第一一般实施方式涉及一种半导体管芯封装，包括：具有第一表面和第二表面的衬底；第一半导体管芯；设置在第一半导体管芯和衬底的第一表面之间的导电粘合剂；以及位于第一半导体管芯上的第二半导体管芯。第二半导体管芯包括第一表面和第二表面，该第一表面面朝着远离第一半导体管芯的方向，而该第二表面面朝着第一半导体管芯。该半导体管芯进一步包括多个导电结构，用于将第二半导体管芯的第一表面处的区域电耦合到衬底的第一表面处的导电区域。
本发明的这一一般实施方式使设备设计者能够将设备的两个半导体管芯堆叠在单个封装中，这些管芯的背面(例如，非作用表面)则彼此面对面。然后，设计者可以用第一管芯和衬底之间的导电粘合剂中的图案来实现对第一管芯的正面(比如作用表面)的电连接，比如通过使用倒装接合。对第二管芯的正面(比如作用表面)的电连接可以用上述导电结构来实现。管芯之间的电互连可以用衬底中的电迹线与上述导电结构的组合来实现。在本实施例进一步的实施方式中，一个或多个导热纵向路径(比如“热通孔”)可以被纳入在衬底中并且被热耦合到第一管芯上的一个或多个热焊盘以增进从该封装的排热。在此进一步的实施方式中，产生较多热量的管芯可以被选作第一管芯。在其它实施方式中，接地平面可以被纳入在衬底中，并且任选地耦合到第一管芯上的接地平面从而为第一管芯提供电屏蔽。在其它实施方式中，导热纵向路径和接地平面可以作为单个结构而被提供。
本发明的另一个一般实施方式涉及一种用于形成半导体管芯封装的方法，该方法包括：用导电粘合剂将第一半导体管芯和衬底附接到一起；用粘合剂将第一半导体管芯和第二半导体管芯附接到一起；其中第二半导体管芯具有第一表面和第二表面，该第一表面面朝着远离第一半导体管芯的方向，而该第二表面面朝着第一半导体管芯；以及将多个导电结构附接到第二半导体管芯的第一表面和所述衬底。第一和第二半导体管芯可以在第一半导体管芯和衬底被附接到一起之前或之后被附接到一起。此外，第一和第二半导体管芯可以是在第一半导体管芯和衬底被附接到一起的同时被附接到一起的。
本发明的另一个一般实施方式涉及一种系统，比如便携式电子设备，它包括根据本发明的半导体管芯封装。这种系统的实现方式可以包括一种通用串行总线控制器，用于电耦合到所述封装的一个或多个管芯。
结合附图，在具体实施方式部分详细描述了本发明的这些和其它实施方式。在附图中，相同的标号可以指代相同的元件，一些元件的描述可能不重复。
附图说明
图1-3分别示出了根据本发明的示例性半导体管芯封装的顶视图、侧视图和底视图；图3也示出了可用在根据本发明的示例性半导体封装中的示例性衬底的底面的平面图。
图4示出了可用在根据本发明的示例性半导体封装中的示例性衬底的顶面的平面图。
图5示出了图4所示示例性衬底的电迹线和连接焊盘的顶部平面图。
图6示出了图4和5所示示例性衬底的电迹线和连接焊盘的半透明的透视图。
图7-11示出了在根据本发明的制造实施方式的示例性步骤期间示例性的半导体管芯封装的透视图。
图12示出了使用根据本发明的示例性半导体管芯的示例性系统的示意图。
具体实施方式
本发明的第一示例性实施方式涉及图1和2中的10所示的半导体管芯封装。封装10包括：衬底12；第一半导体管芯30；设置在第一半导体管芯30和衬底12之间的导电粘合剂25(如图2所示)；以及第二半导体管芯40，其被设置在第一半导体管芯30上并且通过粘合剂50与其粘合在一起。第一半导体管芯30的正面最好面对着基板12，而第二半导体管芯40的背面最好面朝着远离衬底12和第一半导体管芯30两者的方向。管芯30和40的背面最好彼此面对着，并且通过粘合剂50而接合到一起。在本文中，管芯的“正面”是导电区域(比如互连焊盘或“连接盘”)的个数最多的表面，而“背面”是导电区域的个数最少的表面。通常，背面没有接触点，或者仅有接地接触点，或者仅有一个或少数几个漏极或集电极接触点(在纵向晶体管管芯的情况下)。如本领域已知的那样，半导体管芯的“作用表面”是具有大多数电学部件的表面，而“非作用表面”是具有最少电学部件的表面(电学部件的定义包括诸如晶体管、电阻器、电容器、电感器、布线等)。通常，但并非总如此，管芯的作用表面也将是上述正面，并且非作用表面将是上述背面。
根据本发明各实施方式的半导体管芯封装中的管芯也可以包括功率晶体管或其它类型的器件，这些器件至少在一个表面处具有一个输入端并且在相反表面处具有输出端。这种器件可以被描绘成“纵向”器件。一些纵向器件的示例包括纵向功率MOSFET、纵向二极管等等。
更一般地讲，且参照图3和4，衬底12具有：第一表面13(图4)；第二表面14(图3)；多个第一导电区域15，被设置在其第一表面13上并且适于耦合到第一半导体管芯30上的导电区域；多个第二导电区域16，被设置在其第一表面13上；以及多个第三导电区域17，被设置在其第二表面14上。回到图2，第一半导体管芯30具有：第一表面31(比如背面)，其面朝着远离衬底12的方向；以及第二表面32(比如正面)，其面朝着衬底12的第一表面13。第一半导体管芯30具有多个导电区域，通过导电粘合剂25(它可以包括焊料)将这些导电区域粘合到衬底12的第一导电区域15(如图4所示)。第二半导体管芯40具有：第一表面41(比如正面)，其面朝着远离第一半导体管芯30的方向；以及第二表面42(比如背面)，其面朝着第一半导体管芯30，该第二背面42通过粘合剂50而被粘合到管芯30的第一表面31。粘合剂50最好包括电绝缘粘合剂材料，比如环氧树脂粘合剂。
参照图1和2，半导体管芯封装10还包括多个导电结构60，用于将第二半导体管芯40的第一表面41处的多个导电区域45电耦合到衬底12的多个第二导电区域16。导电区域45可以包括常规的IC焊盘，而导电结构60可以包括线接合、条带楔键接合、带式自动接合(“TAB接合”)、导电夹等等。导电结构60以及衬底12中的布线(下文会描述)提供了在半导体管芯30与40之间的电互连以及在半导体管芯40与利用封装10的系统之间的电互连。较佳地，半导体管芯封装10还包括电绝缘材料体70，该电绝缘材料体70被设置在导电结构60上以及衬底12和半导体管芯30、40的露出的第一表面上，较佳地，电绝缘材料体70用于包封导电结构60。体70为导电结构60提供机械支承，防止它们因外力而弯曲或被扯掉，并且与衬底12一起为半导体管芯封装10提供坚固的壳。封装10具有无引线配置，这意味着没有实质上延伸到该封装的尺寸外的引线。在衬底12的第二表面14处的导电区域17处，实现对封装10的电连接。
衬底12能包括预先模制的引线框、层压件或带有电互连的任何其它类型的衬底结构。示例性的预先模制的引线框可以包括嵌入在模制材料中的引线框，其中模制材料的厚度大致等于引线框结构的厚度。在一些实施方式中，预先模制的衬底可以包括：第一表面和/或相反的第二表面，这些表面可以包括引线表面和/或管芯附接表面；以及外部模制材料表面，它与所述引线表面和/或管芯附接表面共面。
除了上述导电区域15-17以外，衬底12最好还包括多条迹线20和纵向导体22，用于提供在各个导电区域15、16、17之间的多个互连。在本文中，术语“纵向导体”宽泛地涵盖任何横跨在衬底或管芯的两个表面之间的电连接。在叠层衬底技术中，纵向导体可以通过通孔来实现。术语“迹线”宽泛地涵盖任何具有除了纵向导体或互连焊盘以外的电学功能的导电材料段。通常，但并非总如此，迹线将下列之中的两项或多项电连接：纵向导体；互连焊盘(即导电区域)；以及其它迹线。图5和6示出了一示例中的迹线20和纵向导体22，在该示例中衬底12包括预先模制的引线框。图5示出了顶部平面图，图6示出了顶部半透明的透视图，在图中没有示出引线框的非导电模制材料，以使得迹线20和纵向导体22可以被更清晰地看到。在本示例中，通过使所选的区域16与所选的区域17相抵接就能形成纵向的导体22，通过在引线框中设置内部金属段以使该金属段的一个或多个部分接触上述区域15-17中所选的区域就可以形成迹线。第一迹线20a将第一区域15a电耦合到第二区域16a，第二区域16a和第三区域17a彼此相抵接以在它们之间形成纵向导体22a。与导电结构60一起，这些部件就能提供在管芯30、40和利用封装10的系统之间的电互连。第二迹线20b使两个第一区域15b和第二区域16b电耦合到一起，并且第二区域16b和第三区域17b彼此相抵接以在它们之间形成纵向导体22b。这些部件与导电结构60一起也能提供在管芯30、40和利用封装10的系统之间的电互连。
第三迹线20c将两个第一区域15c以及第二区域16c电耦合到一起。与导电结构60一起，这些部件就能提供在管芯30和40之间的电互连。第四迹线20d将第一区域15d、第二区域16d和第三区域17d电耦合到一起，在区域16d和17d之间形成了纵向导体22d。第五迹线20e将第一区域15e和第二区域16e电耦合到一起，第一区域15e和第三区域17e彼此相抵接以在它们之间形成纵向导体22e。与导电结构60相结合，这最后两组部件提供了在管芯30、40和利用封装10的系统之间的电互连。最终，多个纵向导体22f由彼此相抵接的各对区域16f和17f来形成(为了视觉上的清晰，图6仅为纵向导体22f之一示出参考标号)。纵向导体22f与各个导电结构60相结合，提供了在管芯40和利用封装10的系统之间的电互连。作为额外的特征，区域15e和17e(相对于16f和17f)以及纵向导体22e很大的相对面积以及它们在管芯30下方的位置提供了穿过衬底12的表面的很大的导热纵向路径(比如热通孔)，该路径能将来自管芯30、40的热传导至利用封装10的系统。区域15-17各自通常包括一种或多种金属，每种金属的导热性一般高于上述材料体70的导热率以及衬底12的绝缘材料的导热率。作为额外的特征，区域15e和17e可以被用作管芯30的接地平面。
如此，设计者就能使用迹线20、纵向导体22、导电区域15-17和导电结构60来提供在管芯30和40之间、以及在管芯30、40各自与使用半导体管芯封装10的系统之间期望的一组电互连。这些互连以及管芯30、40能被一起设置在单个普通半导体管芯封装的空间中，由此使设备设计者能够增加这些设备的功能，而不增大其尺寸，并且在某些情况下还可减小其尺寸。用于衬底12的引线框或层压件可以很容易被设计和大量生产，其中迹线与纵向导体的配置在与导电结构60相结合的情况下为期望的应用提供互连。此外，衬底12的表面14上的导电区域17的布局与尺寸可以符合标准图案(比如在仙童半导体公司的MicroPak 10封装中所见的标准图案)，以促成将封装10纳入到现存的设计与制造流程中。在进一步的实施方式中，可以在衬底12中包括冗余的迹线、纵向导体以及导电区域，从而能够容易实现设计变化和/或使一个衬底设计能够在两种或多种不同的半导体管芯组合中使用。在这两种进一步的实施方式中，导电结构60的放置都可以被改变，并且一些导电结构60可以被添加或被去除。
现在描述本发明的示例性制造方法实施方式。图7-11示出了在该方法实施方式的示例性步骤期间的示例性半导体管芯封装的透视图。参照图7，从衬底12开始，将导电材料25敷设到衬底12的导电区域15，或者敷设到第一半导体管芯30的正面上相应的导电区域，或者敷设到这两组导电区域。导电材料25可以包括常规的基于金属的焊料，并且可以通过若干种技术来敷设，这包括膏状焊料的丝网印刷、焊球附接、拾放工艺等。然后，管芯30的正面被设置成在区域15的面积中面对着衬底12，并且该组装件被加热以使导电材料25将导电区域15接合到管芯30的正面上的导电区域。图8示出了所得的组装件。后一步骤通常被称为倒装接合。当导电粘合剂包括常规的基于金属的焊料时，该组装件的加热过程使导电粘合剂重熔。本段落所描述的两个一般的步骤合而包括：用导电粘合剂25将第一半导体管芯30和衬底12附接到一起。
参照图9，粘合剂50被设置在第一半导体管芯30的背面(即图9中露出的表面)上。粘合剂50也可以被设置在第二半导体管芯40的背面上，或被设置在这两个背面上。粘合剂50可以包括环氧树脂材料，并且其形式可以最初是材料片、材料体、或一个或多个液滴或凝胶滴。接下来，使第二半导体管芯40的背面接触到第一管芯30的背面，用的是处于这两个背面之间的粘合剂50。如果粘合剂50需要加热才能凝固或固化，则上述组装件被加热到比室温高的温度以凝固或固化粘合剂50。图10示出了所得的组装件。本段所描述的两个一般步骤合而包括：将第二半导体管芯40与第一半导体管芯30附接到一起，其中第二半导体管芯40的正面面朝着远离半导体管芯30的方向，而管芯40的背面面朝着管芯30。
尽管示例性方法实施方式示出了先将管芯30与衬底12附接到一起然后将管芯30和40附接到一起，但是可以理解这些步骤能按相反的顺序来执行，或者基本上同时执行。在前一种情况下，粘合剂50可以具有也可以不具有转变温度，该转变温度高于将第一半导体管芯30和衬底12附接到一起所使用的任何高温。在后一种情况下，衬底12以及管芯30、40可以彼此相堆叠，而粘合剂25和50则置于其间，之后，在加热的同时将它们压在一起从而使粘合性材料实现其接合。
参照图11，上述示例性方法实施方式还包括：在第二半导体管芯40的正面41处的导电区域45与衬底12的各个区域16之间，附接多个导电结构60。导电结构60可以包括线接合、条带楔键接合、带式自动接合(“TAB接合”)等，并且可以用任何已知的附接方法来进行附接。在一般意义上，这一步骤将多个导电结构附接到第二半导体管芯40的正面和衬底12。在导电结构60被附接之后，该示例性方法可以还包括：在导电结构60以及衬底12和半导体管芯30、40的露出的表面上，设置电绝缘材料体70，从而将导电结构60包封起来。该步骤可以使用注模技术，以提供封装10的期望的形状。所得的封装具有无引线配置(即，没有引线实质上延伸到该封装的尺寸之外)，其中对其的电连接是在衬底12的第二表面14处的导电区域17处实现的。
在半导体管芯封装10的一些实现方式中，第一半导体管芯30可以包括一个或多个背侧接触点，这些接触点在该管芯的背面31的周缘附近。在这种情况下，第二半导体管芯40可以相对于管芯30而放置，使得在管芯被附接之后，所有的或部分的背侧接触点是露出来的。通过使用这种构造，就可以在管芯30的背侧接触点与衬底12的各个导电区域16之间附接导电结构60。
图12示出了第一示例性系统100的示意图，该系统使用了根据本发明的示例性半导体管芯封装10′。系统100包括：主控制器120，用于提供系统100的整体服务；通用串行总线(USB)连接器110，用于提供到外部设备的通信连接；USB控制器130，用于提供在主控制器120以及USB连接器110和与其相连的外部设备之间的接口。USB连接器110具有如下四个连接点：功率连接，用于接收来自USB电缆的电能供给Vusb；接地连接，用于接收接地电势GND；第一数据连接D+/R和第二数据连接D-/L，用于接收数据信号。系统100还包括：副控制器140，用于产生和/或接收替换信号，这些替换信号能被多路复用到USB连接器110的数据连接D+/R和D-/L上；以及根据本发明的半导体管芯封装10′，其促成实现系统100的补充功能而在空间需求上没有显著增加，这在下文中可以看出。
当USB电缆没有连接到USB连接器110时，比如当替换电缆耦合到连接器110时，系统100被配置成发送和/或接收与副控制器140相关联的替换信号。在一个实现方式中，当音频电缆被连接到USB连接器110时，系统100可以在副控制器140之间发送和/或接收音频信号，其中这种音频电缆可以耦合到麦克风、扬声器或其它音频处理设备。在这种情况下，副控制器140可以包括音频编码器/解码器(CODEC)。可以使用连接器110的连接Vusb和GND之间的电势差来确定是USB电缆还是替换电缆被耦合到USB连接器110，或者可以使用数据连接D+/R和D-/L处存在的信号的频率值来进行这种确定。在图12所示的实现方式中，存在约3.5伏或更大的电势差就指示了连接器110处出现的是USB电缆，没有电势差就指示了出现的是音频电缆或没有任何电缆。另外，当USB电缆没有连接到USB连接器110时，系统100可以被配置成自供电，并且当USB电缆连接到其USB连接器110时，系统100可以进一步被配置成从USB电缆获取部分或全部的自用电能。
以功率控制器管芯30′(例如功率控制电路)作为第一半导体管芯30并且以信号多路复用器管芯40′(例如信号处理电路)作为第二半导体管芯40的半导体管芯封装10′促成了上述示例性功能的实现。功率控制器管芯30′检测在控制器110的连接Vusb和GND之间有没有电势差，并且据此产生经调节的电压源Vout，该电压源Vout进而被用于给USB控制器130(以及系统100的任选其它部件)供电并且向多路复用器管芯40′指示USB电路是否存在。管芯30′包括：输入焊盘Vin，用于接收总线供给电压Vusb；接地焊盘GND，用于接收总线接地；控制焊盘ON，用于接收起动信号以起动工作；输出供给焊盘Vout，用于将经调节的电能供给提供给系统100的USB控制器130和其它部件(任选)；以及限流焊盘ISET，用于接收指示焊盘Vout处所提供的最大输出电流的限值的信号。控制焊盘ON可以通过高值电阻器而耦合到Vusb，限流焊盘ISET可以通过电阻器而耦合到接地。另外，管芯30′包括功率晶体管，其两个传导端子分别耦合到焊盘Vin和Vout，其调制端子则耦合到控制器。该功率晶体管被配置成负载晶体管，用于将电能从源切换到负载，并且可以包括PMOS晶体管。该控制器接收来自焊盘Vin、ON、ISET和GND的信号以及来自电流感测设备的信号，该电流感测设备耦合到功率晶体管的传导端子之一。根据这些信号，控制器产生用于该功率晶体管的调制端子的控制信号，以使该功率晶体管以期望的方式调节去往焊盘Vout的功率(例如，将焊盘Vout处所提供的最大电流限制到一数值，该数值是由耦合在焊盘ISET和接地之间的电阻器所设定的)。管芯30′可以包括仙童半导体公司的型号为FPF2125的IntelliMAXTM高级负载管理产品。FPF2125的数据表通过参引纳入在此。
多路复用器管芯40′包括双极双掷多路复用器，用于将USB控制器110的数据连接D+/R和D-/L多路复用在一方面来自USB控制器130的数据信号D+和D-以及另一方面来自副控制器140的信号L和R之间。多路复用器的选择是受管芯40′上的开关控制器控制的，该控制器接收三种输入：Vbus；Vaudio；和Asel。当信号Vbus是有效的时候，开关控制器将数据连接D+/R和D-/L分别耦合到数据信号D+和D-。当信号Vaudio和信号Asel是无效的时候，开关控制器将数据连接D+/R和D-/L分别耦合到数据信号R和L。当信号Vaudio是有效而信号Asel也是有效的时候，开关控制器将数据连接D+/R和D-/L分别耦合到数据信号R和L(这样，Asel就充当超驰输入)。当所有的输入信号都是无效的时候，使数据连接D+/R和D-/L与所有信号D+、D-、R和L解耦合。输入Asel被偏置到无效状态，为此可以任其处于浮置状态，正如图所示那样。开关控制器包括数字逻辑，用于接收这些输入并产生到多路复用器的开关的部件的控制信号。在系统100的示例性实现方式中，输入Vbus被耦合到半导体管芯30′的输出Vout，输入Vaudio被耦合到来自主控制器120的信号。由此，当管芯30′检测到连接器110处存在USB电缆时，管芯40′的多路复用器将连接器110的数据连接D+/R和D-/L分别耦合到USB控制器130的数据信号D+和D-。当USB电缆不存在时，主控制器120可以通过激活信号Vaudio来指导管芯40′的多路复用器将数据连接D+/R和D-/L分别耦合到副控制器140的数据信号R和L。管芯40′可以包括仙童半导体公司的USB2.0高速(480Mbps)和带负信号能力的音频开关产品，型号是FSA201或FSA221。FSA201或FSA221的数据表通过参引纳入在此。
在上述两个示例性管芯30′和40′中，管芯30′通常产生更多的热(因其功率流的调节所导致)，并且被有利地放置在衬底12旁边，其一部分表面能被附接到很大的中心纵向导体22e(图6)，该导体同时充当纵向导体和导热纵向通路。管芯30′既包括模拟电路又包括数字电路，并且管芯40′也既包括模拟电路又包括。在其它示例性系统中，管芯30′可以主要包括数字电路，管芯40′可以主要包括模拟电路，反之亦然。
上述半导体管芯封装可以被用在电学组装件中，这些电学组装件包括其上搭载有所述封装的电路板。它们也可以被用在诸如电话、计算机等系统中。
上述一些示例涉及“无引线”类型的封装，比如MLP型封装(微引线框封装)，其中引线的端子末端并不延伸超过模制材料的横向边缘。本发明的实施方式也可以包括有引线的封装，其中引线延伸超过模制材料的横向表面。
在本文中，“某”、“一”和“所述”等表述旨在意指一个或多个，除非另有说明。
本文所使用的术语和表达被用作描述而非限制，使用这些术语和表达并不意味着排除所示和所描述的特征的等效物，应认识到在本发明的范围之内各种修改都是可能的。
此外，本发明一个或多个实施方式的一个或多个特征可以与本发明其它实施方式的一个或多个特征组合起来，而不会偏离本发明的范围。
尽管已经结合所示的实施方式对本发明作了具体的描述，但是应该理解，基于本文所揭示的内容可以作出各种改变、修改、调适和等效的安排，并且旨在落在本发明和所附权利要求书的范围中。

Claims (25)

1.一种半导体管芯封装，包括：
具有第一表面和第二表面的衬底；
第一半导体管芯；
设置在所述第一半导体管芯和所述衬底的第一表面之间的导电粘合剂；
位于所述第一半导体管芯上的第二半导体管芯，所述第二半导体管芯包括第一表面和第二表面，所述第一表面面朝着远离所述第一半导体管芯的方向，所述第二表面面朝着所述第一半导体管芯；以及
多个导电结构，用于将所述第二半导体管芯的第一表面处的导电区域电耦合到所述衬底的第一表面处的导电区域。
2.如权利要求1所述的半导体管芯封装，其特征在于，
所述导电结构包括布线，并且所述导电粘合剂包括焊料。
3.如权利要求1所述的半导体管芯封装，其特征在于，
所述衬底还包括：
多个第一导电区域，被设置在其第一表面处并且通过所述导电粘合剂的各个部分而电耦合到所述第一半导体管芯的导电区域；
多个第二导电区域，被设置在所述衬底的第一表面处；以及
电迹线，用于使所述第一导电区域中的至少一个电耦合到所述第二导电区域中的至少一个；并且
其中至少一个所述导电结构被附接到与所述迹线电耦合的第二导电区域。
4.如权利要求3所述的半导体管芯封装，其特征在于，
所述衬底还包括：
多个第三导电区域，被设置在其第二表面处，并且
其中所述电迹线被进一步电耦合到所述多个第三导电区域中的至少一个。
5.如权利要求1所述的半导体管芯封装，其特征在于，
所述衬底包括跨越在其第一和第二表面之间的纵向导体，其中所述纵向导体通过所述导电粘合剂的至少一部分而耦合到第一半导体管芯的至少一个区域。
6.如权利要求1所述的半导体管芯封装，还包括：
模制材料，用于覆盖所述第一半导体管芯和所述第二半导体管芯的至少一部分。
7.如权利要求1所述的半导体管芯封装，其特征在于，
所述衬底包括预先模制的衬底，它具有引线框和模制材料。
8.如权利要求1所述的半导体管芯封装，其特征在于，
所述半导体管芯封装具有无引线配置。
9.如权利要求1所述的半导体管芯封装，还包括：
在所述第一半导体管芯和所述第二半导体管芯之间的绝缘层。
10.如权利要求1所述的半导体管芯封装，其特征在于，
所述第一半导体管芯包括至少一个负载开关，并且所述第二半导体管芯包括双极双掷多路复用器。
11.如权利要求1所述的半导体管芯封装，其特征在于，
所述第一半导体管芯包括功率晶体管，并且所述第二半导体管芯包括至少一个控制电路。
12.如权利要求1所述的半导体管芯封装，其特征在于，
所述第一半导体管芯包括功率控制电路，并且所述第二半导体管芯包括信号处理电路。
13.如权利要求12所述的半导体管芯封装，其特征在于，
所述衬底还包括从其第一表面跨越到其第二表面的纵向导体，并且其中所述纵向导体通过所述导电粘合剂的至少一部分而耦合到所述第一半导体管芯的至少一个区域。
14.一种系统，包括USB控制器以及耦合到该USB控制器的如权利要求1所述的半导体管芯封装。
15.一种方法，包括：
用导电粘合剂将第一半导体管芯和衬底附接到一起；
用粘合剂将所述第一半导体管芯和第二半导体管芯附接到一起，其中所述第二半导体管芯具有第一表面和第二表面，所述第一表面面朝着远离所述第一半导体管芯的方向，所述第二表面面朝着所述第一半导体管芯；以及
将多个导电结构附接到所述第二半导体管芯的第一表面和所述衬底。
16.如权利要求15所述的方法，其特征在于，
所述衬底包括预先模制的衬底。
17.如权利要求15所述的方法，其特征在于，
将所述第一半导体管芯和所述衬底附接到一起包括将导电材料至少敷设于所述衬底的导电区域。
18.如权利要求15所述的方法，其特征在于，
将所述第一半导体管芯和所述衬底附接到一起包括将导电材料至少敷设于所述第一半导体管芯的导电区域。
19.如权利要求15所述的方法，其特征在于，
将所述第一半导体管芯和所述衬底附接到一起包括将焊料膏敷设于多个导电区域，所述导电区域位于所述衬底和所述第一半导体管芯之一之上或者位于所述衬底和所述第一半导体管芯这两者之上，之后使所述第一半导体管芯和衬底接触到一起并且加热。
20.如权利要求15所述的方法，其特征在于，
将所述第一和第二半导体管芯附接到一起包括在所述第一半导体管芯上放置粘合剂。
21.如权利要求15所述的方法，其特征在于，
将所述第一和第二半导体管芯附接到一起包括将所述第一和第二半导体管芯的非作用表面附接到一起。
22.如权利要求15所述的方法，其特征在于，
将多个导电结构附接到所述第二半导体管芯的第一表面和所述衬底包括：在所述衬底上的导电区域和所述第二半导体管芯的第一表面上的导电区域之间附接线接合。
23.如权利要求15所述的方法，其特征在于，
在所述第一和第二半导体管芯被附接到一起之前，所述第一半导体管芯和所述衬底被附接到一起。
24.如权利要求15所述的方法，其特征在于，
在所述第一半导体管芯和所述衬底被附接到一起之前，所述第一和第二半导体管芯被附接到一起。
25.如权利要求15所述的方法，还包括：
在所述导电结构上以及所述衬底和各半导体管芯的露出的表面上，放置电绝缘材料体。
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Cited By (3)

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CN103633075A (zh) * 2012-08-24 2014-03-12 台湾积体电路制造股份有限公司 叠层封装半导体器件
CN110914982A (zh) * 2017-02-10 2020-03-24 微芯片技术股份有限公司 背面偏置式半导体管芯的接地技术以及相关的设备、系统和方法
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7899946B2 (en) * 2008-01-11 2011-03-01 Modu Ltd. Audio and USB multiplexing
US7825502B2 (en) 2008-01-09 2010-11-02 Fairchild Semiconductor Corporation Semiconductor die packages having overlapping dice, system using the same, and methods of making the same
US20090256245A1 (en) * 2008-04-14 2009-10-15 Yong Liu Stacked Micro-Module Packages, Systems Using the Same, and Methods of Making the Same
US20090315163A1 (en) * 2008-06-20 2009-12-24 Terry Johnson Semiconductor Die Packages with Stacked Flexible Modules Having Passive Components, Systems Using the Same, and Methods of Making the Same
US7973393B2 (en) * 2009-02-04 2011-07-05 Fairchild Semiconductor Corporation Stacked micro optocouplers and methods of making the same
JP2010192680A (ja) * 2009-02-18 2010-09-02 Elpida Memory Inc 半導体装置
US8063654B2 (en) * 2009-07-17 2011-11-22 Xilinx, Inc. Apparatus and method for testing of stacked die structure
US20120326287A1 (en) 2011-06-27 2012-12-27 National Semiconductor Corporation Dc/dc convertor power module package incorporating a stacked controller and construction methodology
CN103646942B (zh) * 2010-02-25 2016-01-13 万国半导体有限公司 一种应用于功率切换器电路的半导体封装结构
US8421204B2 (en) 2011-05-18 2013-04-16 Fairchild Semiconductor Corporation Embedded semiconductor power modules and packages
US8332545B1 (en) * 2011-05-31 2012-12-11 Smsc Holdings S.A.R.L. USB switch which allows primary USB connection in response to USB signaling
US8525321B2 (en) * 2011-07-06 2013-09-03 Fairchild Semiconductor Corporation Conductive chip disposed on lead semiconductor package
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US11476232B2 (en) 2019-03-25 2022-10-18 Analog Devices International Unlimited Company Three-dimensional packaging techniques for power FET density improvement
KR102172689B1 (ko) * 2020-02-07 2020-11-02 제엠제코(주) 반도체 패키지 및 그 제조방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
SG97938A1 (en) 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
US6798044B2 (en) 2000-12-04 2004-09-28 Fairchild Semiconductor Corporation Flip chip in leaded molded package with two dies
JP2002222914A (ja) 2001-01-26 2002-08-09 Sony Corp 半導体装置及びその製造方法
US6777786B2 (en) 2001-03-12 2004-08-17 Fairchild Semiconductor Corporation Semiconductor device including stacked dies mounted on a leadframe
JP2002359346A (ja) 2001-05-30 2002-12-13 Sharp Corp 半導体装置および半導体チップの積層方法
US6885093B2 (en) 2002-02-28 2005-04-26 Freescale Semiconductor, Inc. Stacked die semiconductor device
US6969914B2 (en) * 2002-08-29 2005-11-29 Micron Technology, Inc. Electronic device package
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
TWI303873B (en) 2005-09-23 2008-12-01 Freescale Semiconductor Inc Method of making stacked die package

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633075A (zh) * 2012-08-24 2014-03-12 台湾积体电路制造股份有限公司 叠层封装半导体器件
CN103633075B (zh) * 2012-08-24 2016-12-28 台湾积体电路制造股份有限公司 叠层封装半导体器件
CN110914982A (zh) * 2017-02-10 2020-03-24 微芯片技术股份有限公司 背面偏置式半导体管芯的接地技术以及相关的设备、系统和方法
CN111615624A (zh) * 2017-11-17 2020-09-01 希奥检测有限公司 应力敏感集成电路管芯的附接
CN111615624B (zh) * 2017-11-17 2022-04-01 希奥检测有限公司 应力敏感集成电路管芯的附接
US11548781B2 (en) 2017-11-17 2023-01-10 Sciosense B.V. Attachment of stress sensitive integrated circuit dies

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