CN100438016C - 采用接地拱顶进行引线接合焊球阵列的方法 - Google Patents

采用接地拱顶进行引线接合焊球阵列的方法 Download PDF

Info

Publication number
CN100438016C
CN100438016C CNB200480022476XA CN200480022476A CN100438016C CN 100438016 C CN100438016 C CN 100438016C CN B200480022476X A CNB200480022476X A CN B200480022476XA CN 200480022476 A CN200480022476 A CN 200480022476A CN 100438016 C CN100438016 C CN 100438016C
Authority
CN
China
Prior art keywords
ground connection
vault
encapsulation
ground
impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB200480022476XA
Other languages
English (en)
Other versions
CN1833317A (zh
Inventor
C·怀兰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1833317A publication Critical patent/CN1833317A/zh
Application granted granted Critical
Publication of CN100438016C publication Critical patent/CN100438016C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73229—Wire and TAB connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1616—Cavity shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/1617—Cavity coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/166—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

提供了一种结构来控制接合线的阻抗。在一个示例性实施例中，集成电路器件(110)包括：集成电路(130)，其具有多个(115)接地焊盘、信号焊盘和电源焊盘；以及用于安装该集成电路的封装(110)，其包括具有至少一个围绕着集成电路的基准迹线(140)的导电路径。在集成电路(130)之上设有由涂覆了介质的金属带所形成的接地拱顶(170)，其与接地焊盘相连以提供散热和电磁干扰屏蔽。

Description

采用接地拱顶进行引线接合焊球阵列的方法
技术领域
本发明涉及集成电路封装的领域，尤其涉及降低高针数半导体封装中的接合线阻抗。
背景技术
随着集成电路技术的改进以提高可布置在给定衬底面积上的器件的密度和复杂性，对这些器件的封装提出了重大的挑战。例如在计算机应用中，数据总线的宽度从16位、32位、64位提高到128位及更高。在数据于系统内传输的期间，总线具有瞬时切换输出(SSO)并不罕见。SSO经常由于SSO期间存在的较大瞬态电流而导致芯片的电源和接地干线产生噪音。如果这种噪音比较严重，那么接地和电源干线将偏离其预定电压，导致芯片产生无法预测到的动作。
在BGA(焊球阵列)封装中，通常采用接合线来将器件管芯与封装上的接地部分相连。在高针数的BGA中通常使用接地环。这些接合线有时设置成与信号接合线紧密相邻，以便通过形成共面的波导结构来控制信号接合线的阻抗。
美国专利5872403和6083772涉及一种在衬底上安装功率半导体管芯的结构和方法，它们大体上涉及到功率电子器件，更具体地涉及用于功率器件的低阻抗大电流导体及其制造方法。
美国专利6319775B1涉及一种制造集成电路封装的方法，尤其涉及一种用于将导电带连接到集成电路管芯和引线框架上的工艺。该专利以及上面提到的两项专利通过引用结合于本文中。
在传统工艺中，使用通常称为插入式散热片的帐篷式结构来降低阻抗。这些插入式散热片可以接地，也可以不接地。然而，从插入式散热片到接合线的距离可能太远，使得无法对接合线的阻抗产生显著的影响。因此，对接合线阻抗的控制很低。存在着尤其是在高频高性能应用中提供对接合线阻抗的控制的需求。
发明内容
在一个示例性实施例中，提供了结构来控制接合线阻抗。这涉及到一种集成电路器件，包括具有多个接地焊盘、信号焊盘和电源焊盘的集成电路，以及用于安装该集成电路的封装，该封装包括导电路径，其具有至少一个围绕着集成电路的基准迹线。在集成电路上设有接地拱顶，该实施例的一个特征是，基准迹线与电压基准和接地基准中的至少一个相连。该实施例的另一特征是，接地拱顶包括与介质材料层合在一起的金属带。
在另一实施例中，讨论了一种用于在将半导体器件管芯封装到封装中时控制接合线的阻抗的方法，所述方法包括：在所述器件管芯上限定信号和电源/接地焊盘的位置；在所述封装上限定接地迹线的位置；接合所述器件管芯的信号焊盘和电源/接地焊盘；提供包括位于接合线之上的接地拱顶和接地迹线位置的导电路径，将所述封装旋转预定的量，并且提供另外的接地拱顶；以及密封所述器件管芯、所述接地拱顶和所述另外的接地拱顶。
其它的优点和新颖特征将在下面的描述中进行阐述，本领域的技术人员在理解了下述描述后可对其有一定程度的了解，或者可通过实施本发明来领会。
附图说明
本发明将通过示例并参考附图来进一步说明，在图中：
图1是接合线阻抗相对于接地拱顶距离的曲线图；
图2A是根据本发明一个实施例的用于BGA的接地拱顶结构的侧视图；
图2B是图2A所示接地拱顶结构的特写剖视图；
图3是根据本发明另一实施例的用于BGA的另一接地拱顶结构的侧视图；
图4是根据本发明另一实施例的用于BGA的另一接地拱顶结构的侧视图；
图5是根据本发明的一个示例性实施例的封装器件管芯的流程图；和
图6是根据本发明的另一示例性实施例的举例说明用于封装器件的一种方法的流程图。
具体实施方式
本发明在降低将器件和BGA封装的电源或接地部分相连的路径中的阻抗方面是有利的。此外，本发明可通过在离信号接合线为预定距离之处设置接地拱顶来控制信号接合线的阻抗。
本发明在降低将器件和BGA封装的电源或接地部分相连的路径中的阻抗方面是有利的，此外，本发明可通过在离信号接合线为预定距离之处设置接地拱顶来控制信号接合线的阻抗。这在高频应用、例如接近1GHz的高频存储器应用中是有帮助的，另外，还存在信号上升时间比经过封装的传播延迟更快的高速应用。通过使接合线的阻抗较小，可以在管芯焊盘处得到较快的上升时间，这是因为焊盘处的上升时间由封装互连特征阻抗乘以焊盘电容来限定。包括接合线的较小封装互连阻抗可导致更快的上升时间，从而得到更快的IC器件。
在其它应用中，可将接地拱顶连接到稳定的基准电压下，而不是连接到接地部分。这种应用由特定的器件管芯特征和电压供给要求来驱动。
如图1所示，曲线图50显示了作为接合线离接地拱顶的距离的函数的接合线阻抗。曲线60显示了在变化的距离处的接合线阻抗。各个距离处的阻抗由曲线上各数据点处的数值65来表示。例如，在50微米的距离处，接合线阻抗约为61欧。在另一未示出的例子中，在约500微米的距离处，阻抗约为119欧。对于无屏蔽的接合线来说，阻抗约为125欧。
在一个示例性实施例中，在集成电路(IC)器件和接合线之上紧密地形成了铜带，以便降低接合线阻抗。另外，减小的接合线阻抗可以降低接合线电感和电磁干扰(EMI)。使用薄铜带可针对特定的接合线和管芯结构来定制接地拱顶。
现在来看图2A，在根据本发明的一个示例性实施例中，在管芯和封装之间紧密相邻于接合线而形成了低阻抗的电源或接地连接。这便降低了接合线的阻抗。在BGA封装结构100中封装了IC器件。在衬底110上连接了管芯130。管芯焊盘115通过引线120与封装连接区125引线接合。焊球105连接在接地迹线140上。该接地迹线140可以是BGA中常用的接地环，以便为IC管芯130提供至接地的连接。在已接合的IC管芯130上设有接地拱顶170，其经由导电接合部150a和150b与接地迹线140相连。接地拱顶170具有导电材料160和介质材料145。导电材料160可包括任何可与用来制造IC器件的工艺以及用来封装该器件的工艺兼容的金属。这种材料包括但不限于铜、金、银、铝及其合金。
图2B是接地拱顶170的特写剖视图。导电材料160和介质材料145具有适合于特定封装类型的厚度。例如，本发明可应用于具有特殊设计的引线框架的陶瓷和塑料针栅阵列(PGA)中。引线框架设计成使得接地引线宽得足以允许与拱顶电接触。
在一个示例性实施例中，导电材料160可以是铜带。铜带以方便的方式形成，并且可针对给定的管芯尺寸以及接合线的高度和长度来有效地定制。然而，铜带必须具有足够的厚度，以便提供可承受封装冲击的自支撑结构。例如，25微米的厚度便足够了，或者在其它情况下可以使用250微米的厚度。该厚度取决于封装的程度以及所制造的产品。导电接合部150a和150b可以是导电粘合剂、焊料或压力接合部，但不必限于提供电连接的这些方法。
介质材料145可防止导电材料160接触到接合线120而导致短路。有很多种介质可应用到拱顶上以防止意外短路。介质的类型基于按照可能的成本最大限度地减小介电常数来选择。这种材料包括但不限于环氧树脂、聚酰亚胺、聚酰胺、焊接掩膜、PTFE和TEFLONTM。当然，介质必须能耐受在模制工艺期间所遇到的温度。
现在来看图3，其为不希望使导电接合部接地的应用。在根据本发明的另一实施例中，结构200具有接合到衬底210上的管芯230。管芯230利用引线220从焊盘连接区215引线接合到封装连接区225。在衬底210上通过接合部250a，250b，250c连接了拱顶270，其包括在其上设有绝缘材料245的导电部分260。拱顶270在其中心处弯曲，提供了额外的接合点。在该例中，拱顶在其绝缘材料245上形成接合。接合部250a和250c并不通过接地迹线与焊球205相连，因此拱顶并不电接地，可以将其连接到具有有源电路的管芯的中心的周围。然而，拱顶中的导电材料提供了耗散IC器件230所产生热量的路径。器件设计和封装工艺决定非电连接式接合的需要性。采用适于为拱顶提供充分的机械连接的粘合剂来粘结接合部250a，250b，250c。介质材料选择成具有所需的传热特性以及与所用粘合剂的相容性。
参见图4，在本发明的另一实施例中，图3所示类型的拱顶可与封装电连接。结构300具有与衬底310相连的管芯330。接合线320将管芯焊盘连接区315与封装连接区325相连。焊球305连接在接地迹线340a和340b上。在这些接地迹线340a和340b上，接地拱顶370在特定点处经由导电接合部350a和350b而连接到其上，在这些点处，接地拱顶370的介质材料245敞开以露出接地拱顶的导电材料260。除了导电接合部350a和350b以外，管芯330具有围绕着其中心的接地区域380，另一导电接合部350c连接在其上。为了实现这种结构，使用者可将其IC设计的布局制订成使得接地区域380构建成围绕着管芯330的中心。该接地部分可在设计工艺的早期结合到特定IC器件的设计中。如果设计不允许处于中心的接地区域，那么例如可将接地区域布置在管芯的不同象限部分中。
在另一实施例中，这类接地拱顶370可在350a和350b处与接地迹线340a和340b电连接。如果没有中心接地迹线380的话，那么可以省略350c处的电连接。350c处的拱顶370可附着在管芯中心的周围，但不与之电连接。因此，接地拱顶370在340a，350a和340b，350b处提供了额外的接地，而在350c处提供了散热。
通过减小电源部分或接地部分上的因I/O开关电流而引起的感应噪音，低阻抗的接地拱顶便可改善信号完整性。在构建接地拱顶中使用的带可以是实心的或网式的。在拱顶不接地的情况下，由于拱顶提供了降低的热阻并可耗散掉管芯所产生的热量，因此可以实现封装热性能的提高。在接地式应用中，拱顶通过在管芯上方提供屏蔽而降低了EMI。管芯被接地屏蔽与封装相结合地包围起来。
图5显示了将上述实施例应用于具有高针数且封装在相应的高球/针数封装中的给定器件管芯的流程图。
在一个示例性实施例中，可遵循一系列步骤500来在器件管芯和封装上执行本发明。设计者已在器件上限定了信号和电源/接地焊盘的位置。前期设计工作集中在降低器件上的噪音影响范围，同时增强器件的性能。在已经选择了合适的封装后，使用者将器件的信号焊盘和电源/接地焊盘与相应的封装连接区相接合510。在完成了接合510之后，将接地拱顶设在接合线上515。接地拱顶中的介质材料降低了形成短路的可能性。利用导电接合部将接地拱顶连接在封装上520。在已经连接了接地拱顶之后，使用者将器件管芯和接地拱顶组件密封起来550。如上所述，接地拱顶可形成为具有围绕中心的凹陷(图3和4)，使得可采用传热性粘合剂来将接地拱顶连接到管芯中心的周围。
可采用多种方法来在拱顶和接地部分之间形成电接触。例如，可以在拱顶铜带和封装接地部分之间使用导电胶，例如导电管芯连接材料Ablestik 2000BTM。
在另一示例性实施例中，拱顶可钎焊在封装上。在这种情况下，可在封装接地连接上施加钎焊膏，并且拱顶与钎焊膏相接触。可对钎焊膏进行回流焊以形成连接。通常使用回流温度高于模塑料固化温度的钎焊膏。
在另一示例性实施例中，连接机构可以是金热压接合，其中接地焊盘和拱顶镀有金，然后通过热量和压力相连，从而形成热压接合。其它方法可以是用来将硅管芯连接到封装上或者将管芯焊盘与封装连接区引线接合起来的方法。
图6的流程图显示了按照上述实施例来执行的用于制造半导体器件的一种方法。在另一示例性实施例中，预计需要有额外的接地和散热的设计者在器件管芯上限定信号焊盘、电源/接地焊盘和芯上接地拱顶连接的位置605。步骤605通常在任何涉及到硅的实际设计进行之前进行。然而，本发明也可应用于任何器件和封装的组合。在限定了器件管芯焊盘的布置和封装之后，将器件的信号和电源/接地焊盘接合到相应的封装连接区上610，然后将接合用接地带设在器件接地焊盘和封装接地部分上615。根据封装的类型，可以使用如图3所示地围绕着器件管芯的接合焊盘或接地环。另外，可在器件/封装结构中使用多个接地带。在与接地带相接合之后，可将接地带附近的器件信号焊盘引线接合到相应的封装连接区上620。在与接地拱顶相接合之后，密封该封装625。
虽然本发明主要适用于BGA封装，然而它也可应用于具有其上可连接接地拱顶的区域的任何封装中。
另外，可以使用超过一个接地拱顶。在一个示例性实施例中，在第一方向上构建接地拱顶。将封装/管芯组件旋转90度，然后连接另一接地拱顶。
在另一示例性实施例中，接地拱顶可构建为两个接地拱顶的组合，其中一个接地拱顶连接在器件管芯中心的周围，在将封装/管芯组件旋转90度之后，在管芯接合的中心以外之处连接第二接地拱顶。
可采用超过两个接地拱顶来提供增强的接合线阻抗。设计者可确定实现所希望的阻抗控制所需的接地拱顶的数量。接地拱顶的数量可与管芯尺寸、封装、引线接合的数量等相关。
在另外一个示例性实施例中，将多个接合线编织在一起，以便在信号引线接合部和器件管芯上形成网。该网可与接地位置相接合以提供屏蔽。
在另一示例性实施例中，可以构建出半拱顶，其仅与封装接地部分相连，并且延伸过接合线以提供屏蔽，但不与器件接触。在该实施例的一个变型中，半拱顶可设计成仅与管芯接触，以便提供下降的热阻，但它不与封装电连接。
虽然已经参考若干特定的示例性实施例来介绍了本发明，然而本领域的技术人员可以认识到，在不脱离在所附权利要求中阐述的本发明的精神和范围的前提下，可对其进行许多修改。

Claims (4)

1.一种用于在将半导体器件管芯封装到封装中时控制接合线的阻抗的方法，所述方法包括：
在所述器件管芯上限定信号和电源/接地焊盘的位置；
在所述封装上限定接地迹线的位置；
接合所述器件管芯的信号焊盘和电源/接地焊盘；
提供包括位于接合线之上的接地拱顶和接地迹线位置的导电路径，将所述封装旋转预定的量，并且提供另外的接地拱顶；以及
密封所述器件管芯、所述接地拱顶和所述另外的接地拱顶。
2.根据权利要求1所述的方法，其特征在于，所述预定的量为约90度。
3.根据权利要求1所述的方法，其特征在于，提供另外的接地拱顶与器件设计、封装尺寸、接合线的数量以及所需的阻抗有关。
4.根据权利要求3所述的方法，其特征在于，所需阻抗与接地拱顶离接合线的距离有关。
CNB200480022476XA 2003-07-30 2004-07-30 采用接地拱顶进行引线接合焊球阵列的方法 Expired - Lifetime CN100438016C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49133803P 2003-07-30 2003-07-30
US60/491,338 2003-07-30

Publications (2)

Publication Number Publication Date
CN1833317A CN1833317A (zh) 2006-09-13
CN100438016C true CN100438016C (zh) 2008-11-26

Family

ID=34103017

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200480022476XA Expired - Lifetime CN100438016C (zh) 2003-07-30 2004-07-30 采用接地拱顶进行引线接合焊球阵列的方法

Country Status (6)

Country Link
US (1) US7217997B2 (zh)
EP (1) EP1652234B1 (zh)
JP (1) JP5058599B2 (zh)
CN (1) CN100438016C (zh)
TW (1) TWI376756B (zh)
WO (1) WO2005010989A1 (zh)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7303113B2 (en) * 2003-11-28 2007-12-04 International Business Machines Corporation Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers
US20060007171A1 (en) * 2004-06-24 2006-01-12 Burdi Roger D EMI resistant balanced touch sensor and method
JP4494175B2 (ja) * 2004-11-30 2010-06-30 新光電気工業株式会社 半導体装置
US7355289B2 (en) 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
US8030760B2 (en) * 2006-12-05 2011-10-04 Kabushiki Kaisha Toyota Jidoshokki Semiconductor apparatus and manufacturing method thereof
US7667321B2 (en) * 2007-03-12 2010-02-23 Agere Systems Inc. Wire bonding method and related device for high-frequency applications
US8018042B2 (en) * 2007-03-23 2011-09-13 Microsemi Corporation Integrated circuit with flexible planar leads
US8058719B2 (en) * 2007-03-23 2011-11-15 Microsemi Corporation Integrated circuit with flexible planer leads
US7829997B2 (en) 2007-04-04 2010-11-09 Freescale Semiconductor, Inc. Interconnect for chip level power distribution
US8129226B2 (en) 2007-05-10 2012-03-06 Freescale Semiconductor, Inc. Power lead-on-chip ball grid array package
US8589832B2 (en) * 2007-08-24 2013-11-19 International Business Machines Corporation On chip shielding structure for integrated circuits or devices on a substrate and method of shielding
US8566759B2 (en) * 2007-08-24 2013-10-22 International Business Machines Corporation Structure for on chip shielding structure for integrated circuits or devices on a substrate
US8517990B2 (en) 2007-12-18 2013-08-27 Hospira, Inc. User interface improvements for medical devices
US8138024B2 (en) * 2008-02-26 2012-03-20 Stats Chippac Ltd. Package system for shielding semiconductor dies from electromagnetic interference
TWI382519B (zh) * 2008-04-21 2013-01-11 Advanced Semiconductor Eng 利用外蓋之電子元件封裝模組
US8410584B2 (en) * 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
WO2010020836A1 (en) 2008-08-22 2010-02-25 Taiwan Semiconductor Manufacturing Co., Ltd Impedance controlled electrical interconnection employing meta-materials
JP2010108980A (ja) * 2008-10-28 2010-05-13 Elpida Memory Inc 半導体装置
US10691860B2 (en) 2009-02-24 2020-06-23 Rambus Inc. Secure logic locking and configuration with camouflaged programmable micro netlists
US9735781B2 (en) 2009-02-24 2017-08-15 Syphermedia International, Inc. Physically unclonable camouflage structure and methods for fabricating same
KR100950511B1 (ko) * 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
KR100935854B1 (ko) * 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
US8362607B2 (en) * 2009-06-03 2013-01-29 Honeywell International Inc. Integrated circuit package including a thermally and electrically conductive package lid
US8008785B2 (en) * 2009-12-22 2011-08-30 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
US8791582B2 (en) 2010-07-28 2014-07-29 Freescale Semiconductor, Inc. Integrated circuit package with voltage distributor
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8222725B2 (en) 2010-09-16 2012-07-17 Tessera, Inc. Metal can impedance control structure
AU2012299169B2 (en) 2011-08-19 2017-08-24 Icu Medical, Inc. Systems and methods for a graphical interface including a graphical representation of medical data
WO2013090709A1 (en) 2011-12-16 2013-06-20 Hospira, Inc. System for monitoring and delivering medication to a patient and method of using the same to minimize the risks associated with automated therapy
US9018742B2 (en) * 2012-01-19 2015-04-28 Infineon Technologies Ag Electronic device and a method for fabricating an electronic device
EP2830687B1 (en) 2012-03-30 2019-07-24 ICU Medical, Inc. Air detection system and method for detecting air in a pump of an infusion system
US8674509B2 (en) * 2012-05-31 2014-03-18 Freescale Semiconductor, Inc. Integrated circuit die assembly with heat spreader
US10463788B2 (en) 2012-07-31 2019-11-05 Icu Medical, Inc. Patient care system for critical medications
US10046112B2 (en) 2013-05-24 2018-08-14 Icu Medical, Inc. Multi-sensor infusion system for detecting air or an occlusion in the infusion system
ES2838450T3 (es) 2013-05-29 2021-07-02 Icu Medical Inc Sistema de infusión que utiliza uno o más sensores e información adicional para hacer una determinación de aire en relación con el sistema de infusión
ES2845748T3 (es) 2013-05-29 2021-07-27 Icu Medical Inc Sistema de infusión y método de uso que impiden la sobresaturación de un convertidor analógico-digital
ES2776363T3 (es) 2014-02-28 2020-07-30 Icu Medical Inc Sistema de infusión y método que utiliza detección óptica de aire en línea de doble longitud de onda
CA2947045C (en) 2014-05-29 2022-10-18 Hospira, Inc. Infusion system and pump with configurable closed loop delivery rate catch-up
US11344668B2 (en) 2014-12-19 2022-05-31 Icu Medical, Inc. Infusion system with concurrent TPN/insulin infusion
US10850024B2 (en) 2015-03-02 2020-12-01 Icu Medical, Inc. Infusion system, device, and method having advanced infusion features
KR20160120074A (ko) * 2015-04-07 2016-10-17 (주)와이솔 반도체 패키지 및 그 제조 방법
WO2017171859A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Semiconductor package with electromagnetic interference shielding structures
EP4085944A1 (en) 2016-05-13 2022-11-09 ICU Medical, Inc. Infusion pump system with common line auto flush
CA3027176A1 (en) 2016-06-10 2017-12-14 Icu Medical, Inc. Acoustic flow sensor for continuous medication flow measurements and feedback control of infusion
US10204842B2 (en) * 2017-02-15 2019-02-12 Texas Instruments Incorporated Semiconductor package with a wire bond mesh
US10256193B1 (en) 2017-11-29 2019-04-09 Nxp Usa, Inc. Methods and devices with enhanced grounding and shielding for wire bond structures
US10089055B1 (en) 2017-12-27 2018-10-02 Icu Medical, Inc. Synchronized display of screen content on networked devices
IT201800004209A1 (it) * 2018-04-05 2019-10-05 Dispositivo semiconduttore di potenza con relativo incapsulamento e corrispondente procedimento di fabbricazione
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same
IT201900013743A1 (it) 2019-08-01 2021-02-01 St Microelectronics Srl Dispositivo elettronico di potenza incapsulato, in particolare circuito a ponte comprendente transistori di potenza, e relativo procedimento di assemblaggio
US11278671B2 (en) 2019-12-04 2022-03-22 Icu Medical, Inc. Infusion pump with safety sequence keypad
IT202000016840A1 (it) 2020-07-10 2022-01-10 St Microelectronics Srl Dispositivo mosfet incapsulato ad alta tensione e dotato di clip di connessione e relativo procedimento di fabbricazione
WO2022020184A1 (en) 2020-07-21 2022-01-27 Icu Medical, Inc. Fluid transfer devices and methods of use
US11135360B1 (en) 2020-12-07 2021-10-05 Icu Medical, Inc. Concurrent infusion with common line auto flush
TWM615377U (zh) * 2020-12-28 2021-08-11 丁肇誠 具有包覆層之導線的半導體元件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0435530A2 (en) * 1989-12-21 1991-07-03 General Electric Company Hermetic high density interconnected electronic system or other body
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6229702B1 (en) * 1999-06-02 2001-05-08 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability
US20030089983A1 (en) * 2001-11-15 2003-05-15 Siliconware Precision Industries Co., Ltd. Ball grid array semiconductor package

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083772A (en) * 1978-08-14 1992-01-28 Brown Lawrence G Exercising apparatus
US4814943A (en) * 1986-06-04 1989-03-21 Oki Electric Industry Co., Ltd. Printed circuit devices using thermoplastic resin cover plate
JPH02198158A (ja) * 1989-01-27 1990-08-06 Hitachi Ltd 半導体装置
US5166722A (en) * 1990-08-14 1992-11-24 Nikon Corporation Camera image shake detecting apparatus
JPH04165655A (ja) * 1990-10-29 1992-06-11 Sanyo Electric Co Ltd 高周波半導体装置
US5309321A (en) * 1992-09-22 1994-05-03 Microelectronics And Computer Technology Corporation Thermally conductive screen mesh for encapsulated integrated circuit packages
JP2948039B2 (ja) * 1992-12-28 1999-09-13 株式会社日立製作所 回路基板
JPH07326685A (ja) * 1994-05-31 1995-12-12 Fujitsu Ltd 半導体装置とその製造方法
JP2874595B2 (ja) * 1995-05-11 1999-03-24 日本電気株式会社 高周波回路装置
US5872403A (en) * 1997-01-02 1999-02-16 Lucent Technologies, Inc. Package for a power semiconductor die and power supply employing the same
JP3082905B2 (ja) * 1997-01-28 2000-09-04 富士通電装株式会社 チップ・オン・ボード遮蔽構造およびその製造方法
US5851337A (en) * 1997-06-30 1998-12-22 Caesar Technology Inc. Method of connecting TEHS on PBGA and modified connecting structure
JPH11204679A (ja) * 1998-01-08 1999-07-30 Mitsubishi Electric Corp 半導体装置
US6373127B1 (en) * 1998-09-29 2002-04-16 Texas Instruments Incorporated Integrated capacitor on the back of a chip
US6319775B1 (en) * 1999-10-25 2001-11-20 Advanced Micro Devices, Inc. Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
JP2001210761A (ja) * 2000-01-24 2001-08-03 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2001339016A (ja) * 2000-05-30 2001-12-07 Alps Electric Co Ltd 面実装型電子回路ユニット
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
US7196415B2 (en) 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0435530A2 (en) * 1989-12-21 1991-07-03 General Electric Company Hermetic high density interconnected electronic system or other body
US5166772A (en) * 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
US5977626A (en) * 1998-08-12 1999-11-02 Industrial Technology Research Institute Thermally and electrically enhanced PBGA package
US6229702B1 (en) * 1999-06-02 2001-05-08 Advanced Semiconductor Engineering, Inc. Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability
US20030089983A1 (en) * 2001-11-15 2003-05-15 Siliconware Precision Industries Co., Ltd. Ball grid array semiconductor package

Also Published As

Publication number Publication date
JP5058599B2 (ja) 2012-10-24
EP1652234A1 (en) 2006-05-03
JP2007500441A (ja) 2007-01-11
EP1652234B1 (en) 2018-12-26
US20060180916A1 (en) 2006-08-17
TW200507132A (en) 2005-02-16
TWI376756B (en) 2012-11-11
US7217997B2 (en) 2007-05-15
CN1833317A (zh) 2006-09-13
WO2005010989A1 (en) 2005-02-03

Similar Documents

Publication Publication Date Title
CN100438016C (zh) 采用接地拱顶进行引线接合焊球阵列的方法
CN102201386B (zh) 方形扁平无引线半导体封装及其制作方法
CN1065662C (zh) 半导体芯片封装及其制造方法
CN1124652C (zh) 半导体器件装配构造和半导体器件装配方法
CN102428557B (zh) 其中通过使用连接到参考电势的额外接合线对接合线进行阻抗控制的微电子组件
US20070238205A1 (en) Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
JPH10294418A (ja) 半導体装置
US7015591B2 (en) Exposed pad module integrating a passive device therein
CN1723557A (zh) 高密度封装的互连电源和地线条及其方法
US20060125079A1 (en) High density package interconnect wire bond strip line and method therefor
CN100505244C (zh) 封装结构
US20110147928A1 (en) Microelectronic assembly with bond elements having lowered inductance
US6806581B2 (en) Bonded anisotropic conductive film
CN100552946C (zh) 电子封装结构
CN217655869U (zh) 半导体封装组件
CN218160365U (zh) 封装结构
JP3030605B2 (ja) 半導体装置
CN115799228A (zh) 集成模块及其制造方法
KR100195511B1 (ko) 리드 프레임을 이용한 볼 그리드 어레이 패키지
TWI495068B (zh) 結合有導腳及基板之半導體封裝件及其製法
CN117352480A (zh) 封装结构及其制作方法
CN102376666A (zh) 一种球栅阵列封装结构及其制造方法
JPH03232265A (ja) リードフレーム
KR19980025623A (ko) 반도체 패키지
JPH03211761A (ja) リードフレーム

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20070810

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20070810

Address after: Holland Ian Deho Finn

Applicant after: NXP B.V.

Address before: Holland Ian Deho Finn

Applicant before: Koninklijke Philips Electronics N.V.

C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: TAIWAN SEMICONDUCTOR MFG

Free format text: FORMER OWNER: NXP CO., LTD.

Effective date: 20091023

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20091023

Address after: Taiwan, Hsinchu, China Science Industry Park, Hsinchu Road, force six, No. eight

Patentee after: Taiwan Semiconductor Manufacturing Co.,Ltd.

Address before: Holland Ian Deho Finn

Patentee before: NXP B.V.

CX01 Expiry of patent term

Granted publication date: 20081126

CX01 Expiry of patent term