CN101127331A - 包括半导体芯片的电子封装及其制造方法 - Google Patents

包括半导体芯片的电子封装及其制造方法 Download PDF

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CN101127331A
CN101127331A CNA2007101399536A CN200710139953A CN101127331A CN 101127331 A CN101127331 A CN 101127331A CN A2007101399536 A CNA2007101399536 A CN A2007101399536A CN 200710139953 A CN200710139953 A CN 200710139953A CN 101127331 A CN101127331 A CN 101127331A
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杰弗里·P.·冈比诺
马克·D.·贾菲
詹姆士·W.·阿迪克森
理查德·约翰·雷塞尔
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Abstract

一种电子封装，其具有至少一个位于芯片上的焊盘，用于实现与集成电路的贯通晶片连接。所述电子封装在焊盘区和有源电路区之间配备有边缘密封件，并且包括裂纹停止部，其适于保护该布置以避免有害的潮气和化合物进入包含焊盘的芯片的有源区。

Description

包括半导体芯片的电子封装及其制造方法
技术领域
本发明涉及提供一种用于实现与集成电路或电子封装的贯通晶片(through-wafer)连接的焊盘，其中所述焊盘包括高表面积铝焊盘以由此获得在焊盘和电引线之间的高可靠性、低电阻连接。具体地，本发明的目的是在焊盘区和有源电路区之间增加边缘密封件，本发明包括裂纹停止部，其适于保护装置以避免有害的潮气和化合物进入包含焊盘的芯片的有源区。
背景技术
在当前技术条件下，贯通晶片连接被频繁用于形成高级类型的电子封装，例如但不限于：3D封装、MEMS封装或CMOS成像器封装。具体地，用于这些连接的工艺被设计为蚀刻通孔通过所述晶片的背面并通过焊盘，以暴露相应焊盘的边缘。然后形成引线来连接焊盘的边缘和焊球，所述焊球被布置在电子封装的背面上。这样，对于多层铝(Al)布线而言，应用多层以形成在引线和焊盘之间的连接从而能够获得低电阻电连接。但是，当应用(Cu)铜布线时，这种特定的方法在应用于多Cu层以形成焊盘和引线之间的连接时会导致差的或相当低的可靠度，其原因是铜材料的氧化和腐蚀。在Cu互连工艺中经常使用单个铝焊盘作为最后金属层。
最近，为了改善上述技术，已经出现了新的结构，如2004年11月23日申请的题为“High Surface Area Aluminum Bond Pad ForThrough-Wafer Connections To An Electronic Package”的、已经共同转让给本受让人的共同在审美国专利申请No.10/904,677中描述和要求保护的，此公开在此并入全文作为参考。
在上面提到的共同在审申请中详细描述的具体结构可以使用单个铝焊盘，但由于在焊盘的下方形成了W(通孔条宽度＜W的厚度的2倍)或W+Al(通孔条宽度＞W的厚度的2倍)的通孔条(via bar)，或是通过在该焊盘顶上增加金属，而增大了该焊盘的表面积。
使用标准通孔掩模或是通过使用另外的掩模可以容易地形成通孔条。两种方式可以用来增加所述通孔条的深度：(1)通过使用RIE(反应离子蚀刻)延时来获得和通孔相比更大的通孔条蚀刻深度，或者(2)通过使用另外的掩模以在形成通孔之前形成通孔条。因此，使用相对于金属有选择性的电介质的各向同性蚀刻(对于SiO2电介质为稀释的HF，对于有机电介质为O2等离子体)也可以增大表面积，从而相对于所述金属而使封装通孔的边缘凹陷。
现有技术的讨论
大体上，尽管这可以涉及到各种不同的元件，所述封装布置，封装可能在其背面或侧面遭到污染和潮气的进入，其中，当使用新的封装方法时，传统的裂纹停止部和边缘密封件在试图保护芯片方面效率低，比如那些公开的用于作为CMOS图像传感器器件的封装方法，包括已知的Schott封装，如在Jiirgen Leib和Michael Tpper在2004年Electronic Components and Technology Conference Preceedings(电子元件和技术会议学报)，第843-847页中的“NewWafer-Level-Packaging Technology Using Silicon-Via-Contacts forOptical and Other Sensor Applications”的公开中所描述的；以及Shellcase封装，如D.Teomin，A.Badihi和G.Zilber(Shellcase Ltd.，Manhat Technology Park)在Solid State Technology(固态技术)V.45，nl，2002年1月，第57-62页的“An Innovative Approach to Wafer-levelMEMS packaging”中所描述的。这些封装从晶片的背面或侧面接入(access)焊盘。因此，在该技术中使用这些新的封装布置和方法时，传统裂纹停止部和边缘密封件一般不足以保护芯片。
在其它类型的传统器件结构中，裂纹停止部和边缘密封件也常常不足以能够避免潮气和污染物的进入，这将不利地影响焊盘和传统电子组件的功能。
此外，Shellcase封装阐明了裂纹停止部，且同样地，密封件或边缘密封件被布置在焊盘区内部，而在Schott封装中，如该技术中所知，含有密封件的保护环被布置在由焊盘围绕的区域内，然后所述焊盘被保护环从外部围绕。
发明内容
因此，在一种情况下，作为防止潮气和污染物的入侵的保护措施，本发明使用边缘密封件和裂纹停止部，其位于由在半导体表面上的焊盘包围的区域的内部。
对于其它类型的封装，比如Shellcase封装，裂纹停止部和边缘密封件都被布置在焊盘的内部，其中通过最后金属层接入所述焊盘，最后金属层优选地由铝构成。通过边缘密封件并通过在最上铜(Cu)层的顶上的SiN盖层来保护有源区中的有源铜(Cu)互连(以及Si中的器件)免受潮气和污染影响。
根据本发明，有如下若干保护措施：
根据第一个方面，将贯通孔(through-via)连接到最后金属层(铝)，并且裂纹停止部位于焊盘的外部而边缘密封件位于焊盘区的内部。
根据另一个实施例，就Schott封装的保护而言，将贯通孔连接到由钨接触形成的本地互连，并且边缘密封件位于焊盘的内部。在边缘密封件中提供了开口，使得焊盘可以连接到芯片的内部而不用和边缘密封件电连接。
此外，根据对于Schott封装的保护的另一个特征，将贯通孔连接到钨(W)接触，其通过M1或更高的金属层和器件区连接。所述贯通孔蚀刻停止于位于Si顶上的SiN层。此SiN层防止铜(Cu)和器件受到和贯通孔制造工艺有关的污染物的污染。所述边缘密封件防止铜(Cu)和器件受到芯片边缘的污染物的污染。
这样前述结构相当清楚地提供了在本发明的实施中有优势的特征。
附图说明
现在可以结合附图参考下面对本发明的优选实施例的详细说明，附图中：
图1A到1C图示了形成使用焊盘下方的通孔条的结构的先后步骤，其可以应用于根据本发明的裂纹停止部和边缘密封件的结合；
图2是传统电子封装结构的示意性平面图；
图3是根据本发明的Shellcase封装结构的示意性平面图；
图4是根据本发明的Schott封装的示意性平面图；
图5是穿过传统电子封装的部分的示意性剖面侧视图；
图6是穿过图3的Shellcase封装的部分的示意性剖面侧视图；
图7是穿过图4的Schott封装的部分的示意性剖面侧视图；
图8是围绕焊盘延伸的边缘密封件的示意性平面图；
图9是穿过根据本发明的变型的Schott封装的部分的示意性剖面侧视图；
图10是图9的一部分的顶视平面图；
图11是穿过根据本发明的另一个变型的Schott封装的部分的示意性剖面侧视图；
图12是图11的一部分的平面图。
具体实施例
如上面所提到的序列号为No.10/904,677的共同在审申请中所描述的，下面的电子封装结构被视为所关心的，被应用到：
图1A到1C图示了第一种电子封装实施例(W+Al通孔条，无另外的掩模)。
回来参见附图的细节，尤其如图1A到1C所示例的，在图1A中示意性地图示了电子封装60的侧视图，其中已经形成了槽以暴露焊盘。提供了玻璃板62，其背面包括聚合物层64，且沿其一侧边缘包括二氧化硅或硝酸硅(silicon nitrate)，其背面和A1或铝焊盘66接触。通孔68位于焊盘66下方。钨(W)通孔条68位于焊盘66的一端，以提供到电路的连接。钨(W)通孔条70位于焊盘66的下方，钨(W)通孔条70的下方是通过环氧树脂与其接合的另一玻璃板，其形成用于附着于其上的BGA焊球(未示出)的背面。如图1B的侧视图所示，已经对电子封装60实施通孔蚀刻，图中示出在电子封装60的结构中可以提供可选的各向同性蚀刻76穿过一个边缘对角地延伸以增大焊盘66的表面积。所述通孔条还可以由金属形成，例如：钨，钨和铝的组合、Cr、Au、Ni、NiMop、Co、CoWP或CoWB。铜引线可以在第一BCB钝化层的顶上形成重分配并由第二BCB层覆盖。
另外，下面要描述的结构还可以包括晶片级封装布置，比如已知的Schott封装，如上所述，其中有通孔穴(via hole)和通道(street)的讨论，其通过高度专门化的等离子体蚀刻工艺以减缩的侧壁形成，且其中接触焊盘从封装的背侧开口蚀刻通过中间电介质层。
电子封装60的边缘82以相对于法线成一角度被切割以定位与焊盘互连的引线。这就使得无需应用为现有技术所提供的另外的掩模。
可以使用RIE延迟(lag)，这样通孔条70比通孔68更深，可以与所使用的金属的类型相关地提供对电介质选择性的各向同性蚀刻(其中稀释的HF用于SiO2电介质，而O2等离子体用于有机电介质)，以使封装的边缘相对于金属凹进或成角度。和现有技术相比，这也使得无需另外的掩模。
可以在形成端部通孔后在焊盘顶上添加另外的金属层，比如铝、金、银、硅基焊料、铅基焊料、钯、铂、铬、镍、铜或它们的合金。该另外的金属通过使用遮蔽掩模来淀积金属而形成，其中铝被蒸发，而且，如果被要求，淀积阻挡层，比如钛、钽、钨、硝酸钽(tantalumnitrate)、硝酸钨(tungsten nitrate)或钛钨。附图中未示出这些材料。可以使用合适的电镀或无电镀来添加所述金属层，由此无电镀不需要另外的掩模。另一方面，电镀可以要求一到两个另外的掩模，其限定用于电镀金属的籽层，如本领域所知。此后，可以在电子封装蚀刻之后应用可选各向同性蚀刻，以相对于法线基本上成角的关系来增大焊盘表面。
参见图2的顶视图，其示意性地表示了根据现有技术的传统电子封装90，图中芯片92包括多个焊盘94，靠近芯片周边排列，其中裂纹停止部96和保护环98比如密封件围绕焊盘94的外部延伸。此配置不能阻止潮气通过封装90的侧面或背面进入，且其可能不利于连接到焊盘94的封装电路(未示出)功能的效力。
具体转到Shellcase封装100的实施例，如图3的示意图所示，其中有半导体芯片102，包括焊盘104的外围阵列，并且其中裂纹停止部106和形成密封件的保护环108都布置为在焊盘104的周边内部延伸。在此情况下，鉴于元件106、108被布置在焊盘104区的内部，这使得能够保护Shellcase封装100免受潮气或污染物的入侵。
关于Schott封装110，如图4的示意性平面图所示，在此情况下，半导体芯片112具有多个沿周边布置的焊盘116，并且其中环形的裂纹停止部118从外部围绕焊盘阵列，而其中形成密封件的保护环120位于焊盘114周边内部，从而根据发明构思保护焊盘免受潮气和/或任何污染物的入侵。
更具体地参见图5的局部剖面侧视图，在此情况下，图5图示了传统半导体或电子封装130，其具有布置在上层136上的探测器132和焊盘134，其中Si衬底138支承上层136。如当前所公知的，在切割通道140的内部提供有焊盘附近的边缘密封件142，在其附近延伸的是所知的连续密封件形式的裂纹停止部144。这种布置基本上不能提供足以阻止潮气和/或污染物入侵到元件或焊盘和电子封装连接的结构。
下面将参考图6到图12说明关于Shellcase和Schott封装的各种用于边缘密封件和裂纹停止部的可选布置。为了清晰起见，用附图标记只适当地标识和本发明相关的封装元件。
如图6所示，图中表示了用于Shellcase封装150的边缘密封件和裂纹停止部的创造性布置。有源铜连接154和中间SiO2层156位于硅衬底152上。铝最后层158使得便于接入焊盘160，如在沿切割通道形成的切割切口162的边缘内所示。在此情况下，同样如图3所示，边缘密封件164和裂纹停止部166(用以密封由切割工艺形成的裂纹)都位于焊盘160区(或图3中的焊盘阵列104)内。因此，通过边缘密封件164以及通过位于最上面的Cu层172的顶上的Si3N4盖层170保护在封装150的有源区中的有源铜(Cu)互连154和在Si层或衬底152中的器件168免受潮气和/或污染物影响。
下面将说明为Schott封装配备用于阻止潮气和/或污染物向封装内入侵的边缘密封件和裂纹停止部布置的各种选择。
参见图7和图8，其中图示了Schott封装180，本实施例和随后的实施例中的与图6的封装150中的元件相似或相同的元件以相同的附图标记标识。在本发明的该特定实施例中(同样参考图4的配置)，Schott封装180包括贯通孔182，用于封装其与最上或最后金属层184连接的引线，其可以由铝(Al)构成。根据此实施例的结构，如图8的平面图所具体图示的那样，裂纹停止部186位于焊盘188(或图4的焊盘阵列114)的外部，朝向封装(或芯片112)的边缘或周边。相反，边缘密封件190，位于焊盘188的内部，沿其三边附近延伸(如图8所示)。
在前述的封装结构中，边缘密封件190朝着封装内部围绕焊盘的三边，并通过邻近切割切口182的裂纹停止部186密封外部周边，该封装结构防止潮气和潜在污染物向Schott封装的电子元件内入侵。
转向图9和图10，其通过侧视剖面图和平面图图示了变型的Schott封装200。在此实施例中，贯通孔202通过衬底Si层204向从钨(W)接触206形成的局部互连延伸。如图所示，边缘密封件208A的较低部分位于焊盘210的内部，开口212形成在边缘密封件中以使得焊盘210连接到芯片内部而不电连接到边缘密封件，其后者具有向上延伸的其余部分208B。如上述的实施例中一样，裂纹停止部214在封装结构的周边附近的焊盘向外部延伸。这样又提供了新的结构来保护电子封装元件免受潮气和/或污染物的入侵。
如图11和图12的另一个Schott封装220的部分的局部和顶视图所示，根据封装结构，贯通孔222延伸通过衬底Si层224和焊盘226到钨(W)接触228，或到更高的金属层(优选地由Cu连接/层构成)。贯通孔边缘密封件232停止在Si3N4层236，而Si3N4层236位于Si衬底层224的顶上，因此Si2N4层保护在封装中的Cu接触和层以及器件免受在贯通孔形成过程中产生的污染物影响。边缘密封件232和向外位于封装(或半导体芯片)外周边缘处的裂纹停止部234接近形成切割通道的切割切口238，保护封装220中的Cu元件和电子器件以避免其边缘处的污染物和水的进入。
从前面所述十分清楚应用于各种类型的电子封装结构的裂纹停止部和边缘密封件或环的新布置和位置提供了避免潮气和/或污染物入侵的安全保护，所述潮气和污染物趋于负面地影响电子封装的运转和可靠性。
尽管已经具体地图示和结合优选实施例描述了本发明，本领域普通技术人员会理解，在不脱离本发明的精神和范围的前提下，可以作出形式和细节上的上述和其它改变。因此，本发明并不限于上面描述和图示的精确的形式和细节，而是涵盖所有落入所附权利要求书的精神和范围的内容。

Claims (24)

1.一种电子封装，其包括半导体芯片，所述半导体芯片具有多个布置在衬底上的电连接层和至少一个定位于所述半导体芯片的上表面上的焊盘，所述电子封装包括在所述至少一个焊盘和所述衬底之间延伸并用于保护其中所包含的电连接和元件免受潮气和污染物的入侵的结构，其中所述保护性结构包括边缘密封件和裂纹停止部，所述边缘密封件和裂纹停止部都在所述至少一个焊盘的外围附近形成以相互间隔开的关系延伸的环形布置。
2.如权利要求1所述的电子封装，其中所述边缘密封件和所述裂纹停止部在限定在所述焊盘阵列内的区域内在外围延伸，且所述外围裂纹停止部在环形边缘密封件附近向外间隔开而延伸。
3.如权利要求2所述的电子封装，其中所述外围裂纹停止部在所述焊盘阵列附近在外部延伸，而所述边缘密封件在所述焊盘阵列内部延伸。
4.如权利要求3所述的电子封装，其中用于封装引线的贯通孔穿过所述半导体芯片的所述衬底层和有源层延伸到所述焊盘。
5.如权利要求3所述的电子封装，其中所述边缘密封件部分地在位于所述衬底层上的有源层中的各个焊盘的边缘部分附近延伸。
6.如权利要求3所述的电子封装，其中所述焊盘阵列位于所述衬底层上，且至少一个探测器焊盘包括所述电子封装的顶层，所述边缘密封件具有与边缘密封件下部形成开口的上部，以便于在不与所述边缘密封件电连接的情况下将所述焊盘连接到所述半导体芯片的内部。
7.如权利要求3所述的电子封装，其中所述贯通孔穿过所述衬底层和焊盘延伸到电子封装中的钨接触或更高金属层；所述边缘密封件从顶层延伸到位于所述衬底层上的Si3N4层，以和裂纹停止部一起保护封装中的电子元件和器件免受潮气和污染物的入侵。
8.如权利要求1所述的电子封装，其中所述边缘密封件和裂纹停止部阻止来自所述电子封装的背部边缘和侧面的潮气和污染物的入侵。
9.如权利要求8所述的电子封装，其中所述裂纹停止部阻止在从晶片上切割分离所述半导体芯片时产生的裂纹和裂缝向所述电子封装中的蔓延。
10.如权利要求2所述的电子封装，其中所述边缘密封件和裂纹停止部在所述焊盘阵列和所述衬底层之间的盖层之间延伸。
11.如权利要求10所述的电子封装，其中所述盖层包括Si3N4，且位于最上面的导电金属层上。
12.如权利要求10所述的电子封装，其中所述衬底层包括Si，并且包含由所述边缘密封件和裂纹停止部布置保护的有源器件。
13.一种具有电子封装的方法，该电子封装包括半导体芯片，所述半导体芯片具有多个布置在衬底上的电连接层和至少一个定位于所述半导体芯片的上表面上的焊盘，其中所述方法包括为所述电子封装配备在所述至少一个焊盘和所述衬底之间延伸并用于保护其中所包含的电连接和元件免受潮气和污染物的入侵的结构，其中所述保护性结构包括边缘密封件和裂纹停止部，所述边缘密封件和裂纹停止部都在所述至少一个焊盘的外围附近形成以相互间隔开的关系延伸的环形布置。
14.如权利要求13所述的方法，其中所述边缘密封件和所述裂纹停止部在限定在所述焊盘阵列内的区域内在外围延伸，且所述外围裂纹停止部在环形边缘密封件附近向外间隔开而延伸。
15.如权利要求14所述的方法，其中所述外围裂纹停止部在所述焊盘阵列附近在外部延伸，而所述边缘密封件在所述焊盘阵列内部延伸。
16.如权利要求15所述的方法，其中用于封装引线的贯通孔穿过所述半导体芯片的所述衬底层和有源层延伸到所述焊盘。
17.如权利要求15所述的方法，其中所述边缘密封件部分地在位于所述衬底层上的有源层中的各个焊盘的边缘部分附近延伸。
18.如权利要求15所述的方法，其中所述焊盘阵列位于所述衬底层上，且至少一个探测器焊盘包括所述电子封装的顶层，所述边缘密封件具有与边缘密封件下部形成开口的上部，以便于在不与所述边缘密封件电连接的情况下将所述焊盘连接到所述半导体芯片的内部。
19.如权利要求15所述的方法，其中所述贯通孔穿过所述衬底层和焊盘延伸到电子封装中的钨接触或更高金属层；所述边缘密封件从顶层延伸到位于所述衬底层上的Si3N4层，以和裂纹停止部一起保护封装中的电子元件和器件免受潮气和污染物的入侵。
20.如权利要求13所述的方法，其中所述边缘密封件和裂纹停止部阻止来自所述电子封装的背部边缘和侧面的潮气和污染物的入侵。
21.如权利要求20所述的方法，其中所述裂纹停止部阻止在从晶片上切割分离所述半导体芯片时产生的裂纹和裂缝向所述电子封装中的蔓延。
22.如权利要求14所述的方法，其中所述边缘密封件和裂纹停止部在所述焊盘阵列和所述衬底层之间的盖层之间延伸。
23.如权利要求22所述的方法，其中所述盖层包括Si3N4，且位于最上面的导电金属层上。
24.如权利要求22所述的方法，其中所述衬底层包括Si，并且包含由所述边缘密封件和裂纹停止部布置保护的有源器件。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867812A (zh) * 2011-07-07 2013-01-09 英飞凌科技股份有限公司 裂缝检测线器件和方法
CN103151360A (zh) * 2011-12-06 2013-06-12 奥普蒂兹公司 用于cmos图像传感器的线结合内插板封装及其制造方法
CN107068627A (zh) * 2016-02-10 2017-08-18 台湾积体电路制造股份有限公司 装置封装件以及用于形成装置封装件的方法
CN108735708A (zh) * 2018-07-18 2018-11-02 北京比特大陆科技有限公司 芯片结构、及其封装方法以及电子设备
CN109786435A (zh) * 2017-11-15 2019-05-21 奕力科技股份有限公司 晶圆结构
CN112309991A (zh) * 2019-07-26 2021-02-02 华为技术有限公司 芯片及其制备方法、电子设备
TWI782549B (zh) * 2020-06-09 2022-11-01 華邦電子股份有限公司 半導體晶粒的邊緣裂紋檢測裝置及其方法

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547969B2 (en) 2004-10-29 2009-06-16 Megica Corporation Semiconductor chip with passivation layer comprising metal interconnect and contact pads
US7397121B2 (en) * 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US9601443B2 (en) * 2007-02-13 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Test structure for seal ring quality monitor
JP5106933B2 (ja) * 2007-07-04 2012-12-26 ラピスセミコンダクタ株式会社 半導体装置
JP5034740B2 (ja) * 2007-07-23 2012-09-26 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7732932B2 (en) * 2007-08-03 2010-06-08 International Business Machines Corporation Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners
US8102027B2 (en) * 2007-08-21 2012-01-24 Broadcom Corporation IC package sacrificial structures for crack propagation confinement
JP5027605B2 (ja) * 2007-09-25 2012-09-19 パナソニック株式会社 半導体装置
US8159254B2 (en) * 2008-02-13 2012-04-17 Infineon Technolgies Ag Crack sensors for semiconductor devices
US8772156B2 (en) * 2008-05-09 2014-07-08 International Business Machines Corporation Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications
US7956466B2 (en) 2008-05-09 2011-06-07 International Business Machines Corporation Structure for interconnect structure containing various capping materials for electrical fuse and other related applications
JP5324822B2 (ja) * 2008-05-26 2013-10-23 ラピスセミコンダクタ株式会社 半導体装置
JP4862017B2 (ja) * 2008-07-10 2012-01-25 ルネサスエレクトロニクス株式会社 中継基板、その製造方法、プローブカード
US8581423B2 (en) 2008-11-17 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Double solid metal pad with reduced area
US9070670B2 (en) 2009-01-29 2015-06-30 International Rectifier Corporation Electrical connectivity of die to a host substrate
JP5439901B2 (ja) * 2009-03-31 2014-03-12 富士通セミコンダクター株式会社 半導体装置及びその製造方法
DE102009034532A1 (de) * 2009-07-23 2011-02-03 Msg Lithoglas Ag Verfahren zum Herstellen einer strukturierten Beschichtung auf einem Substrat, beschichtetes Substrat sowie Halbzeug mit einem beschichteten Substrat
US9018768B2 (en) * 2010-06-28 2015-04-28 Samsung Electronics Co., Ltd. Integrated circuit having through silicon via structure with minimized deterioration
US20120007211A1 (en) * 2010-07-06 2012-01-12 Aleksandar Aleksov In-street die-to-die interconnects
US8692360B1 (en) 2010-07-06 2014-04-08 International Rectifier Corporation Electrical connectivity for circuit applications
US9093411B2 (en) 2010-10-19 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure having contact bars extending into substrate and wafer having the pad structure
US8409925B2 (en) * 2011-06-09 2013-04-02 Hung-Jen LEE Chip package structure and manufacturing method thereof
JP2013123000A (ja) * 2011-12-12 2013-06-20 Sony Corp 固体撮像装置およびその製造方法
NL2008633C2 (nl) 2012-04-13 2013-10-16 Ip4Ss B V Beveiligingssysteem voor een betaal- of geldautomaat.
US8710607B2 (en) 2012-07-12 2014-04-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
JP5968711B2 (ja) * 2012-07-25 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
FR2996354A1 (fr) * 2012-10-01 2014-04-04 St Microelectronics Crolles 2 Dispositif semiconducteur comprenant une structure d'arret de fissure
US8937009B2 (en) 2013-04-25 2015-01-20 International Business Machines Corporation Far back end of the line metallization method and structures
US9245846B2 (en) 2014-05-06 2016-01-26 International Business Machines Corporation Chip with programmable shelf life
US9620460B2 (en) 2014-07-02 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor chip, semiconductor package and fabricating method thereof
US9493346B2 (en) * 2014-07-29 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. Capacitor with planarized bonding for CMOS-MEMS integration
CN105448857B (zh) * 2014-09-02 2018-04-17 中芯国际集成电路制造(上海)有限公司 一种芯片密封环结构及其制作方法
JP2016139711A (ja) * 2015-01-28 2016-08-04 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20160268166A1 (en) * 2015-03-12 2016-09-15 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US9812404B2 (en) * 2015-12-30 2017-11-07 Globalfoundries Inc Electrical connection around a crackstop structure
US10475753B2 (en) * 2018-03-28 2019-11-12 International Business Machines Corporation Advanced crack stop structure
US10490513B2 (en) * 2018-03-28 2019-11-26 International Business Machines Corporation Advanced crack stop structure
JP7378335B2 (ja) 2020-03-31 2023-11-13 エイブリック株式会社 半導体装置及びその製造方法
US11127700B1 (en) 2020-05-28 2021-09-21 United Microelectronics Corp. Integrated circuit device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0602422A1 (en) 1992-12-15 1994-06-22 International Business Machines Corporation Dynamic frequency shifting with divide by one clock generators
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US6130383A (en) * 1995-05-31 2000-10-10 Sgs-Thomson Microelectronics, S.A. Solder ball array package and a method of encapsulation
US5994762A (en) * 1996-07-26 1999-11-30 Hitachi, Ltd. Semiconductor integrated circuit device including boron-doped phospho silicate glass layer and manufacturing method thereof
JP3482779B2 (ja) * 1996-08-20 2004-01-06 セイコーエプソン株式会社 半導体装置およびその製造方法
US5834829A (en) * 1996-09-05 1998-11-10 International Business Machines Corporation Energy relieving crack stop
US6509622B1 (en) * 2000-08-23 2003-01-21 Intel Corporation Integrated circuit guard ring structures
US7187742B1 (en) 2000-10-06 2007-03-06 Xilinx, Inc. Synchronized multi-output digital clock manager
US6951801B2 (en) * 2003-01-27 2005-10-04 Freescale Semiconductor, Inc. Metal reduction in wafer scribe area
JP4303547B2 (ja) * 2003-01-30 2009-07-29 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6914490B2 (en) 2003-05-29 2005-07-05 Ibtel Corporation Method for clock generator lock-time reduction during speedstep transition
US20050026397A1 (en) 2003-07-28 2005-02-03 International Business Machines Corporation Crack stop for low k dielectrics
US20050095835A1 (en) * 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
JP2005129717A (ja) * 2003-10-23 2005-05-19 Renesas Technology Corp 半導体装置
TWI227936B (en) * 2004-01-14 2005-02-11 Taiwan Semiconductor Mfg Sealed ring for IC protection
DE602005006422T2 (de) 2004-06-21 2009-06-18 Koninklijke Philips Electronics N.V. Strom-management
US7777338B2 (en) * 2004-09-13 2010-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structure for integrated circuit chips
JP4689244B2 (ja) * 2004-11-16 2011-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US7361581B2 (en) * 2004-11-23 2008-04-22 International Business Machines Corporation High surface area aluminum bond pad for through-wafer connections to an electronic package
US7741715B2 (en) * 2005-03-14 2010-06-22 Infineon Technologies Ag Crack stop and moisture barrier
JP2007067372A (ja) * 2005-08-03 2007-03-15 Matsushita Electric Ind Co Ltd 半導体装置
US20070102791A1 (en) * 2005-11-07 2007-05-10 Ping-Chang Wu Structure of multi-layer crack stop ring and wafer having the same
WO2007083366A1 (ja) * 2006-01-18 2007-07-26 Fujitsu Limited 半導体装置、半導体ウエハ構造、及び半導体ウエハ構造の製造方法
US7948060B2 (en) * 2008-07-01 2011-05-24 Xmos Limited Integrated circuit structure

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102867812A (zh) * 2011-07-07 2013-01-09 英飞凌科技股份有限公司 裂缝检测线器件和方法
CN103151360A (zh) * 2011-12-06 2013-06-12 奥普蒂兹公司 用于cmos图像传感器的线结合内插板封装及其制造方法
CN107068627A (zh) * 2016-02-10 2017-08-18 台湾积体电路制造股份有限公司 装置封装件以及用于形成装置封装件的方法
CN107068627B (zh) * 2016-02-10 2020-05-15 台湾积体电路制造股份有限公司 装置封装件以及用于形成装置封装件的方法
US10698994B2 (en) 2016-02-10 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US10878073B2 (en) 2016-02-10 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
CN109786435A (zh) * 2017-11-15 2019-05-21 奕力科技股份有限公司 晶圆结构
CN108735708A (zh) * 2018-07-18 2018-11-02 北京比特大陆科技有限公司 芯片结构、及其封装方法以及电子设备
CN108735708B (zh) * 2018-07-18 2024-01-19 北京比特大陆科技有限公司 芯片结构、及其封装方法以及电子设备
CN112309991A (zh) * 2019-07-26 2021-02-02 华为技术有限公司 芯片及其制备方法、电子设备
WO2021017961A1 (zh) * 2019-07-26 2021-02-04 华为技术有限公司 芯片及其制备方法、电子设备
TWI782549B (zh) * 2020-06-09 2022-11-01 華邦電子股份有限公司 半導體晶粒的邊緣裂紋檢測裝置及其方法

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