CN107068627A - 装置封装件以及用于形成装置封装件的方法 - Google Patents

装置封装件以及用于形成装置封装件的方法 Download PDF

Info

Publication number
CN107068627A
CN107068627A CN201710073702.6A CN201710073702A CN107068627A CN 107068627 A CN107068627 A CN 107068627A CN 201710073702 A CN201710073702 A CN 201710073702A CN 107068627 A CN107068627 A CN 107068627A
Authority
CN
China
Prior art keywords
dielectric layer
sensor die
packaging part
array
electrod
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710073702.6A
Other languages
English (en)
Other versions
CN107068627B (zh
Inventor
黄育智
戴志轩
郑余任
陈志华
陈玉芬
蔡豪益
刘重希
余振华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107068627A publication Critical patent/CN107068627A/zh
Application granted granted Critical
Publication of CN107068627B publication Critical patent/CN107068627B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
    • G06F21/31—User authentication
    • G06F21/32—User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

本揭露实施例涉及一种装置封装件以及一种用于形成装置封装件的方法，其中，该装置封装件包含传感器裸片；一或多个额外裸片，其相邻于所述传感器裸片；以及模塑料，其圈住所述传感器裸片及所述一或多个额外裸片。所述装置封装件进一步包含重布层，所述重布层在所述传感器裸片、所述一或多个额外裸片、及所述模塑料上方。所述重布层包含第一导电构件，所述第一导电构件在第一介电层中。所述第一导电构件电连接所述传感器裸片到所述一或多个额外裸片。所述重布层进一步包含电极阵列，所述电极阵列在第二介电层中且电连接到所述传感器裸片，所述第二介电层是在所述第一介电层上方。

Description

装置封装件以及用于形成装置封装件的方法
技术领域
本揭露涉及一种装置封装件以及一种用于形成装置封装件的方法。
背景技术
由于用户装置变得更小且更便于携带，让有不轨企图的人变得更容易窃取用户装置。当这些装置携带用户的敏感数据，除非已有放置阻障到用户装置中，否则窃贼可能能够存取这些数据。一但这种阻障是指纹传感器，其可用以读取试图存取装置的人的指纹，且如果所述指纹与使用者的指纹不相同，存取可能被拒绝。
然而，由于用户装置诸如手机变得更小，对于在用户装置内个别组件的各者也同时看到大小减小上有压力。因此，对于减少含有指纹传感器的指纹封装件的大小但没有看到性能减少而言有压力。
发明内容
根据一实施例，一种装置封装件包含传感器裸片；一或多个额外裸片，其相邻于所述传感器裸片；以及模塑料，其圈住所述传感器裸片及所述一或多个额外裸片。所述装置封装件进一步包含重布层，所述重布层在所述传感器裸片、所述一或多个额外裸片、及所述模塑料上方。所述重布层包含第一导电构件，所述第一导电构件在第一介电层中。所述第一导电构件电连接所述传感器裸片到所述一或多个额外裸片。所述重布层进一步包含电极阵列，所述电极阵列在第二介电层中且电连接到所述传感器裸片，所述第二介电层在所述第一介电层上方。
根据另一实施例，一种装置封装件包含传感器裸片；模塑料，其沿着所述传感器裸片的侧壁延伸；以及第一介电层，其在所述传感器裸片及所述模塑料上方。所述装置封装件进一步包含电极阵列，所述电极阵列在所述第一介电层中且电连接到所述传感器裸片。所述电极阵列侧向延伸超过所述传感器裸片。所述装置封装件进一步包含手指驱动环，所述手指驱动环在所述第一介电层中且圈住所述电极阵列。所述手指驱动环电连接到所述传感器裸片。
根据又一实施例，一种用于形成半导体装置的方法包含囊封传感器裸片及一或多个额外裸片在模塑料中，沉积第一介电层在所述模塑料、所述传感器裸片、及所述一或多个额外裸片上方，以及形成导电构件在所述第一介电层中。所述导电构件电连接所述传感器裸片到所述一或多个额外裸片。所述方法进一步包含沉积第二介电层在所述第一介电层及所述导电构件上方，以及形成电极阵列在所述第二介电层上方。所述电极阵列电连接到所述传感器裸片。所述方法进一步包含沉积第三介电层在所述电极阵列上方，以及附接传感器表面材料到所述第三介电层。
附图说明
本揭露的方面将在与随附图式一同阅读下列详细说明下被最佳理解。请注意，根据业界标准作法，各种特征未依比例绘制。事实上，为了使讨论内容清楚，各种特征的尺寸可刻意放大或缩小。
图1A及1B根据一些实施例绘示指纹传感器装置封装件的剖面图；
图2A及2B根据一些其它实施例绘示指纹传感器装置封装件的剖面图；
图3A至3C根据一些实施例绘示指纹传感器装置封装件的部分的俯视图；
图4A至4E根据一些其它实施例绘示指纹传感器装置封装件的部分的俯视图；
图5A至5S根据一些实施例绘示制造指纹传感器装置封装件的中间阶段的剖面图；以及
图6A至6G根据一些其它实施例绘示制造指纹传感器装置封装件的中间阶段的剖面图。
具体实施方式
下列揭露提供许多用于实施本揭露的不同特征的不同实施例、或实例。为了简化本揭露，于下描述件及配置的具体实例。当然这些仅为实例而非意图为限制性。例如，在下面说明中，形成第一特征在第二特征上方或上可包含其中第一及第二特征经形成为直接接触的实施例，以及也可包含其中额外特征可形成在第一与第二特征之间而使得第一及第二特征不可直接接触的实施例。此外，本揭露可重复参考编号及/或字母于各种实例中。这个重复是为了简单与清楚的目的且其本身并不决定所讨论的各种实施例及/或构形之间的关系。
再者，空间相关词汇，诸如“在…之下”、“下面”、“下”、“上面”、“上”和类似词汇，可为了使说明书便于描述如图式绘示的一个组件或特征与另一个(或多个)组件或特征的相对关系而使用于本文中。除了图式中所画的方位外，这些空间相对词汇也意图用来涵盖装置在使用中或操作时的不同方位。所述设备可以其它方式定向(旋转90度或于其它方位)，据此在本文中所使用的这些空间相关说明符可以类似方式加以解释。
实施例现将关于在封装件解决方案的系统中或整合扇出(integrated fan out，InFO)结构中的指纹传感器描述。然而，实施例可用于合适的装置，诸如具有像素阵列的装置。
首先参考图1A，绘示实施例指纹传感器装置封装件100的剖面图。封装件100可用以确定用于生物特征识别及/或验证的上覆手指的轮廓172。在一实施例中，封装件100作为装置(如，手机、平板装置、膝上型计算机、桌面计算机、智能卡、物联网(internet ofthings，IoT)装置、或任何其中想要感应生物特征的其它装置)的一部分被整合，且封装件100可视需要地用以将上覆手指的轮廓172与储存指纹图像比较并确定存取所述装置是否被授权。例如，当封装件100作为手机的部分被整合时，封装件100可位于手机的外表面以验证使用者并基于指纹验证解锁手机。
封装件100包含传感器裸片102A、高电压(high voltage，HV)裸片102B、及微控制器裸片102C。传感器裸片102A包含逻辑电路以确定施加到封装件100的手指的轮廓172并输出手指的轮廓172到微控制器裸片102C。例如，使用者可施加手指到传感器表面材料114，且传感器裸片102A可从电极阵列108A所检测的电容及/或电压变化确定手指的轮廓172。因此，传感器裸片102A也可称作指纹传感器裸片，其需要来自电极阵列的电讯号以感应施加到封装件100的手指的指纹。手指驱动环108B可进一步用以增加指纹检测的精确度及/或灵敏性。下面提供传感器102A、电极阵列108A、及手指驱动环108B的操作的更详细描述。在各种实施例中，电极阵列108A及手指驱动环108B可设置在形成在裸片102上方的扇出重布层(redistribution layer，RDL)104中，如下面更详细描述。
HV裸片102B经设计与连接以供给高电压，诸如在约5伏特(V)与约50V之间，诸如约33V到传感器裸片102A以放大传感器裸片102A的灵敏度。例如，通过将HV裸片102B与传感器裸片102A整合而使得高电压可被供给到传感器裸片102A，传感器裸片102A的灵敏度可通过将输入电压从如3.3V提高到33V来增加十倍。
微控制器裸片102C经设计与连接以(如，从传感器裸片102A)接收所测量的施加手指的轮廓172并确定所测量的轮廓172是否匹配储存指纹。例如，微控制器裸片102C包含用以比较指纹的微控制器单元(microcontroller unit，MCU)以及用以储存经授权指纹的闪存。在一实施例中，微控制器裸片102C基于所感应手指轮廓172与储存且经授权指纹之间的比较来确定是否授权存取与封装件100整合化的装置。通过包含微控制器裸片102C在指纹感应封装件100内，改善的灵敏度可被达成。例如，指纹感应封装件100不需传输所测量的施加手指的轮廓172到用于认证的外部芯片，这减少被骇的传输风险及不当存取装置。
虽然称作单一“裸片”，但微控制器裸片102C可以是整合裸片(如，具有逻辑及内存电路二者)或分开且电连接的裸片(如，具有分开配置的逻辑及/或内存电路)。在其它实施例中，封装件100可包含其它裸片，包含处理器、逻辑电路、内存、模拟电路、数字电路、混合讯号、及类似裸片。又者，在其它实施例封装件中，HV裸片102B与微控制器裸片102C的任一者或二者可被省略及/或以其它裸片置换。
各裸片102A、102B、及102C(合称作裸片102)可以是半导体裸片且可包含衬底、有源装置、及互连结构(未个别绘示)。裸片102的衬底可包括，例如经掺杂或未经掺杂的主体硅、或绝缘体上半导体(semiconductor-on-insulator，SOI)衬底的有源层。一般，SOI衬底包括形成在绝缘体层上的一层半导体材料，诸如硅。绝缘体层可以是(例如)埋藏氧化物(buried oxide，BOX)层或氧化硅层。绝缘体层提供在衬底诸如硅或玻璃衬底上。替代地，衬底可包含另一元素型半导体，诸如锗；化合物半导体，其包含碳化硅、砷镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs，GaInP、及/或GaInAsP；或其组合。也可使用其它衬底，诸如多层或梯度衬底。
有源装置诸如晶体管、电容器、电阻、二极管、光电二极管、熔丝、及类似物可形成在衬底的顶部表面。互连结构可形成在有源装置及衬底上方。互连结构可包含使用任何合适的方法形成的含有导电构件(如，包括铜、铝、钨、其组合、及类似物的导线及导电通路)的层间介电(inter-layer dielectric，ILD)及/或金属间介电(inter-metal dielectric，IMD)层。ILD及IMD层可包含设置在这些导电构件之间的具有k值，例如低于约4.0或甚至2.0的低k介电材料。在一些实施例中，ILD及IMD层可由例如磷硅酸盐玻璃(phosphosilicateglass，PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass，BPSG)、氟硅酸盐玻璃(fluorosilicate glass，FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、其化合物、其复合物、其组合、或类似物所制，通过任何合适的方法形成，诸如纺丝、化学气相沉积(chemical vapor deposition，CVD)、及等离子增强化学气相沉积(plasma-enhanced CVD，PECVD)。互连结构电连接各种有源装置以在裸片102内形成功能电路。这些电路所提供的功能可包含内存结构、处理结构、传感器、放大器、功率分配、输入/输出电路、或类似物。所属领域的技术人员将了解上面实例仅为了说明目的提供以进一步解释各种实施例的应用且不意图以任何方式限制实施例。对于给定应用，适当时可使用其它电路。
输入/输出(input/output，I/O)及钝化构件可形成在各裸片102的互连结构上方。例如，接触垫103可形成在互连结构上方且可透过在互连结构中的各种导电构件电连接到有源装置。接触垫103可包括诸如铝、铜、及类似物的导电材料。又者，钝化层105可形成在互连结构及接触垫103上方。在一些实施例中，钝化层105可由诸如氧化硅、未经掺杂硅酸盐玻璃、氧氮化硅、及类似物的非有机材料形成。也可使用其它合适的钝化材料。钝化层的部分可覆盖接触垫103的边缘部分。
额外互连构件诸如额外钝化层、导电柱、及/或凸块下金属(under bumpmetallurgy，UBM)层也可视需要地形成在接触垫103上方。例如，图1B绘示实施例封装件150，其中裸片102(传感器102A、HV裸片102B、及微控制器裸片102C)进一步包含接触柱111，在接触垫102上方且电连接到接触垫102。诸如介电材料109的保护层可围绕接触柱111形成。
裸片102的各种构件可通过任何合适的方法形成且不在此处进一步详述。又者，上述裸片102的一般构件及构形仅是一个实例的实施例，且裸片102可包含任何数目的上述构件与其它构件的任何组合。
回头参考图1A，模塑料116是围绕且圈住裸片102A、102B、及102C设置。在实施例中，模塑料116包括环氧化物、树脂、可模塑聚合物诸如聚苯并恶唑(polybenzoxazole，PBO)、经模塑底胶填充(molded underfill，MUF)、或另一模塑材料。模塑料116可使用任何合适的工艺围绕裸片102A、102B、及102C形成，诸如压缩成型或曝光成型。如下面更详细解释，压缩成型一般可在裸片102包括在接触垫103上方的导电柱111(见图1B)时使用，而曝光成型一般是当在扇出RDL 104中的导电构件直接连接到裸片102的接触垫103(见图1A)时使用。在其中使用曝光成型工艺的实施例中，模塑料116的顶部表面可与裸片102的顶部表面实质上齐平或较低(见图1A)。在其中使用压缩成型工艺形成模塑料116的实施例中，模塑料116的顶部表面与设置在裸片102上的导电柱111的顶部表面实质上齐平(见图1B)。在本文中使用时，词汇“实质上”用以考虑由于制造工艺期间生产变化所致数学精准度的偏差。
扇出RDL 104设置在裸片102及模塑料116上方。RDL 104可侧向延伸超过裸片102的边缘而在模塑料116的顶部表面上方。RDL 104可包含形成在多个介电层110中的导电构件106及108。介电层110可由任何合适的材料(如聚酰亚胺(polyimide，PI)、聚苯并恶唑(PBO)、苯并环丁烷(benzocyclobutene，BCB)、环氧化物、聚硅氧、丙烯酸酯、奈米填充的酚树脂、硅氧烷、氟化聚合物、聚降冰片烯、诸如氮化硅的氮化物；诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(borosilicate glass，BSG)、硼掺杂磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、或类似物)所形成。介电层110可通过任何可接受的沉积工艺形成，诸如旋转涂覆、化学气相沉积(CVD)、层压、类似物、或其组合。
导电构件106(如导线106A及/或导电通路106B)可形成在介电层110中。导电构件106设置在RDL 104的下层104B中。下层104B用以描述最靠近裸片102的RDL 104的层。在一些实施例中，导电构件用来作为电气路由，以在传感器裸片102A、HV裸片102B、及微控制器裸片102C之间传输讯号。导电构件106可进一步电连接裸片102到导电贯穿通路118，导电贯穿通路118延伸贯穿模塑料116。导电贯穿通路118在扇出RDL 104中的导电构件与在背侧RDL 120中的导电构件122之间提供电连接。
在图1A与1B的实施例中，焊球126(或其它合适的连接件)设置导电构件122，以接合并电连接封装件100到在另一封装件组件130的导电构件128。在各种实施例中，封装件组件130可以是另一装置裸片、插置件、封装件衬底、印刷电路板、母板、或类似物。为了结构支撑，底胶填充124可视需要地围绕焊球126设置。
RDL 104可进一步在介电层110中包含电极阵列108A及手指驱动环108B。电极阵列108A及手指驱动环108B通过导电通路108C及导电构件106的方式电连接到裸片102。手指驱动环108B可圈住电极阵列108A(见如图3A)，且在一些实施例中,手指驱动环108B也可用来作为密封环以保护在RDL 104中的构件避开外部污染物。然而，不像密封环电隔离，手指驱动环108B电连接到在封装件100中的传感器裸片102B及(视需要地)额外裸片。
电极阵列108A及手指驱动环108B设置在RDL 104的上层104B中。上层104B设置在下层104A上方，且上层104B可用以描述较远离裸片102且较靠近施加到封装件100的具有轮廓172的手指的RDL 104的层。在一些实施例中，电极阵列108A及手指驱动环108B设置在RDL104的最上层中，以减少在电极阵列108A/手指驱动环108B与所施加手指之间的距离。已观察到通过减少这个距离，轮廓172能以增加的灵敏度确定。在图1A中，距离T6被界定成在聚合物层110的顶部表面与电极阵列108A/手指驱动环108B的顶部表面之间的距离。在一些实施例中，距离T6是在约1μm到约5μm之间。
传感器裸片102A电连接到电极阵列108A及手指驱动环108B(如，使用导电构件106及导电通路108C)。所施加手指的轮廓172可通过传感器裸片102使用形成在手指与电极阵列108B之间的有效电容器确定。例如，手指可作为有效电容器的顶板且电极阵列108B可作为有效电容器的底板。传感器裸片102A(有时称作指纹传感器裸片)可使用电极阵列108A所产生的电讯号来确定所施加手指的轮廓172。
在一些实施例中，传感器裸片102A(有时称作指纹传感器裸片)使用直接电容式法来确定所施加手指的轮廓172。例如，手指的凹谷174及凸脊176可对应于具有不同电容的有效电容器。通过测量在电极阵列108A中的电容改变，可确定手指的轮廓172。然而，直接电容式法一般假设有效电容的介电电容率与空气相同。因此，直接电容式法可能受到死掉的皮肤细胞(如，通过线172A所表示)、汗水、及在真皮与电极阵列108A之间的其它杂质(如，通过线172B所表示)所造成的干扰。
因此，在想要改善的灵敏度及精确度的实施例中，传感器裸片102A(有时称作指纹传感器裸片)可使用有源电容法(也称作射频(radio frequency，RF)法)来检测所施加手指的轮廓172。在RF法中，手指驱动环108B是在测量发生之前用以施加RF电压到手指的真皮。电压的应用会改变形成在真皮与电极阵列108A之间的有效电容器。电场在手指与电极阵列之间产生，且所述电场遵循手指真皮中的轮廓172。在放电循环上，跨真皮与电极阵列108A的电压与参考电压做比较，以便计算电容。接着根据式数学计算距离值(如，距离D1及D2)，其中U表示电位能，q表示电荷，及V表示电位(如，电压)。RF法的优点是距离值被直接计算以及杂质可不显著地干扰这些测量。因此，手指驱动环108B提供以改善的灵敏度与精确度来确定指纹的机制。
如图1A中进一步所绘示，电极阵列108A及手指驱动环108B可被间隔而更远离导电构件106。例如，在电极阵列108A/手指驱动环108B与对于电极阵列108A/手指驱动环108B而言导电构件106的最近层之间的纵向距离表示成T1。在不同层中的导电构件106之间的纵向距离表示成T2。裸片102与对于裸片102A而言导电构件106的最近层之间的纵向距离表示成T3。在一些实施例中，距离T2及T3二者都小于距离T1。距离T2及T3可相同或不同。例如，在一些实施例中，距离T2及T3为约2μm到约11μm，而距离T1为约3μm到约15μm。已发现通过更远离导电构件106地间隔电极阵列108A/手指驱动环108B，在RDL 104中的讯号干扰可有利地减少。
现在回到图1A，传感器表面材料114在胶层112的帮助下粘附到扇出RDL 104的顶部表面。在一实施例中，胶层112是色膜或粘合胶，诸如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合。然而，可利用任何其它合适的材料。在一实施例中，胶层112可被施加以具有厚度T4在约2μm与约20μm之间，诸如约10μm。
传感器表面材料114与胶层112接触放置并用以将像素阵列108A与上覆手指分开。在一实施例中，传感器表面材料114是诸如蓝宝石或玻璃的材料，其允许像素阵列108A与上覆手指之间的电容式及/或电压的变化的测量以确定手指的轮廓172。在一实施例中，传感器表面材料114可具有宽度W1是在约5mm与约15mm之间，诸如约10mm，其够大以适当容置手指而使得可获取指纹图像。额外地，传感器表面材料103可具有厚度T5是在约50μm与约1000μm之间，诸如约100μm。
图2A及2B根据一些实施例绘示指纹传感器装置封装件200及250的剖面图。封装件200及250可与封装件100及150相似，其中类似参考符号表示类似组件。封装件200及250可被整合到装置202的壳中。在一些实施例中，装置202是智能卡或类似物。裸片102A、102B、及102C通过粘合剂107粘附到支撑衬底134。在一些实施例中，支撑衬底134是印刷电路板，其在封装件200与各种其它电子构件(未分开绘示)之间提供电连接，各种其它电子构件可包含其它逻辑裸片、内存裸片、电源裸片、离散裸片、整合被动装置、及类似物。粘合剂107可包括裸片附接膜(die attached film，DAF)，诸如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合，且使用层压技术施加。
不像其中电连接到其它装置使用背侧RDL 120达成的封装件100(见图1A)，封装件200通过焊线132电连接到其它装置构件。在一些实施例中，焊线132包含导线或导电指状物，其电连接到设置在接触垫136上的焊球124。接触垫136设置在RDL 104内，例如在RDL104内的最上金属化层。在一些实施例中，接触垫136设置在与电极阵列108A及手指驱动环108B相同的水平。在一些实施例中，手指驱动环108B圈住接触垫136(见如图2A及2B)。在其它实施例中，接触垫136相邻于被手指驱动108B圈住的区域且在被手指驱动108B圈住的区域之外设置(见如图2B及3C)。
图3A至3C根据一些实施例绘示指纹感应装置封装件(诸如封装件100、150、200、或250)的俯视图。图3A绘示在实施例装置封装件中的扇出RDL 104的下层104A的俯视图。裸片102A、102B、及102C的位置是以虚线显示成虚影。在图3A中，裸片102A、102B、及102C的位置可不匹配图1A、1B、2A、或2B的剖面图。应了解，裸片102A、102B、及102C可相对于彼此设置在任何合适的位置中(如，图1A至3C所绘示)或任何其它合适的位置。如图3A所绘示，裸片102A、102B、及102C通过在扇出RDL 104的下层104A中的导电构件106电互连。
图3B及3C绘示在实施例装置封装件中的扇出RDL 104的上层104B的俯视图。如图3B所绘示，扇出RDL 104的上层104B包含电极阵列108A及手指驱动环108B。电极阵列108A包含具有电极108A的行与列的网格。介电层110可设置在电极108A的相邻者之间。虽然绘示特定数目的电极108A，但在各种实施例中，任何数目的电极108A可排列在任何数目的行与列中。又者，阵列的整体大小可足够大以测量手指的轮廓。电极阵列108具有在第一方向上的相对外边缘之间测量的长度L1以及在垂直第一方向的第二方向上的相对外边缘之间测量的宽度W1。在一些实施例中，长度L1为约3.5mm到约10mm而宽度W1为约3.5mm到约10mm。其它尺寸可用在其它实施例中。因为电极阵列108A设置在延伸超过传感器裸片102A的边缘的扇出RDL 104中，所以电极阵列108A的整体大小不限于传感器裸片102A的底面积。例如，在所绘示的实施例中，电极阵列108A占据俯视图中较大于传感器裸片102的底面积，且电极阵列108A可直接延伸在指纹传感器装置封装件中的其它裸片诸(如HV裸片108B及/或微控制器裸片108C)上方。因此，配置电极阵列108A在扇出RDL 104中有利地允许使用较小传感器裸片102A同时仍提供足够大电极阵列108A以获取指纹读取。又者，因为传感器裸片102A的大小可减少，装置封装件可容置额外裸片，诸如HV裸片108B及微控制器裸片108C。
手指驱动环108B圈住电极阵列108A。如上所述，可包含手指驱动环108B以增加指纹传感器的灵敏度及精确度。例如，手指驱动环108B可用以产生可变电压到施加到指纹传感器的手指。在一些实施例中，手指驱动环108B具有宽度W2(如，在外周长与内周长之间所获取者)大于约50μm。已观察到通过组态手指驱动环108B以具有大于50μm的宽度，可有利地增加指纹传感器的灵敏度。例如，具有上述大小的手指驱动环足够大以驱动合适的电压通过手指，以便如上所述地使用有源电容指纹感应方法。
在一些实施例中，上层104B进一步包含接触垫136以电连接到其它装置构件。在图3B的实施例中，手指驱动环108B可圈住接触垫136。在其它实施例中，接触垫136可设置在被手指驱动108B圈住的区域之外(如图3C所绘示)。
图3B及3C绘示具有单一环且大于约50μm的宽度的手指驱动环108B。其它实施例可包含具有不同形状及/或大小的手指驱动环。例如，图4A至4E绘示具有其它构形的手指驱动环108B的俯视图。各手指驱动环108B圈住电极阵列108A，且各手指驱动环108B也可视需要地圈住接触垫136。在其它实施例中，接触垫136可省略或设置在被手指驱动108B圈住的区域之外。
在图4A中，手指驱动环108B包含外环402及内环404。外环402圈住内环404，且介电层110的一部份设置在内环404与外环402之间。外环402及内环404二者都是连续环，这二者都圈住电极阵列108A。又者，内环404及外环402通过设置在外环402与内环404之间的导电材料带406电连接与实体连接。各环402及404可或不可具有大于约50μm的宽度。可包含额外内环以增加手指驱动环108的表面面积并改善灵敏度。又者，外环402的宽度可大于、相同于、或小于内环404的宽度。
在图4B中，手指驱动环108B包含外环402及内环404。外环402圈住内环404，且介电层110的一部份设置在内环404与外环402之间。外环402是连续环而内环404是以各种间距不连续。例如，内环404包含个别区段404'，其与相邻区段404'被介电层110的一部份实体分开。在一些实施例中，内环进一步在手指驱动环108B的转角包含L形区段404”。区段404'及404”的各者通过设置在外环402与内环404之间的导电材料带406电连接到与实体连接到外环402。
在图4C中，手指驱动环108B包含具有第一区段402A、第二区段402B、第三区段402C、及第四区段402D的单一环402。第一区段402A及第二区段402B垂直于第三区段402C及第四区段402D设置。又者，第一区段402A及第二区段402B设置在电极阵列108A的相对侧上，以及第三区段402C及第四区段402D设置在电极阵列108A的相对侧上。手指驱动环108B进一步包含十字形部分408，其连接环402的不同区段。例如，十字形部分408跨越第一区段402A到第二区段402B之间的距离且连接第一区段402A到第二区段402B。十字形部分408进一步跨越第三区段402B到第四区段402D之间的距离且连接第三区段402B到第四区段402D。可包含十字形部分408以增加手指驱动环108B的表面面积并改善灵敏度。在一些实施例中，环404具有宽度W2，其可以大于50μm。在其它实施例中，环404具有宽度W2，其可以小于50μm，诸如在约20μm到约40μm之间取决于布局设计。十字形部分408可进一步并入到具有多个环的实施例中，诸如具有连续内环404(见图4D)或区段化内环404(见图4E)的实施例中。
图5A至5S根据一些实施例绘示制造指纹传感器装置封装件150(见图1B)的中间步骤的剖面图。图5A绘示载体衬底500以及形成在载体衬底500上的离型层502。
载体衬底500可以是玻璃载体衬底、陶瓷载体衬底、或类似物。载体衬底500可以是晶圆，而使得多个封装件可同时形成在载体衬底100上。离型层502可由聚合物系材料所形成，其可连同载体衬底500从将在后续步骤中形成的上覆结构移除。在一些实施例中，离型层502是环氧系热离型材料，所述材料在加热时丧失它的粘合剂性质，诸如光热转换(Light-to-Heat-Conversion，LTHC)离型涂料。在其它实施例中，离型层502可以是紫外光(ultra-violet，UV)胶，其在暴露到UV光时丧失它的粘合剂性质。离型层502可呈液体分注并固化、可以是层压到载体衬底500上的层压膜。离型层502的顶部表面可经整平且具可有高度共平面性。
如图5A所绘示，介电层504形成在离型层502上。介电层504的底部表面可与离型层502的顶部表面接触。在一些实施例中，介电层504是由聚合物诸如PBO、聚酰亚胺、BCB或类似物所形成。在其它实施例中，介电层504是由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、BSG、或BPSG；或类似物所形成。也可使用其它材料。介电层504可通过任何可接受的沉积工艺形成，诸如旋转涂覆、化学气相沉积(CVD)、层压、类似物、或其组合。
如图5B所绘示，导电构件122形成在介电层504上。作为用于形成导电构件122的一实例，晶种层(未显示)形成在介电层504上方。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层及在钛层上方的铜层。晶种层可使用例如PVD或类似物形成。接着光阻形成并图案化在晶种层上。光阻可通过旋转涂覆或类似物形成且可使光阻曝光以兹图案化。光阻的图案对应于导电构件122的图案。图案化形成贯穿光阻的开口，以暴露晶种层。导电材料形成在光阻的开口中且在晶种层的暴露的部份上。导电材料可通过镀覆形成，诸如电镀或无电式电镀、或类似物。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。接着，光阻及其上未有导电材料形成的晶种层的部分被移除。光阻可通过可接受的灰化或剥除工艺移除，诸如使用氧等离子或类似物。一但光阻被移除，晶种层的暴露的部分诸如通过使用可接受的蚀刻工艺移除，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分与导电材料形成如所绘示的导电构件122。
在图5C中，介电层508形成在导电构件122及介电层504上。在一些实施例中，介电层508是由聚合物所形成，所述聚合物可以是可使用光刻屏蔽图案化的光敏材料，诸如PBO、聚酰亚胺、BCB、或类似物。在其它实施例中，介电层508是由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、BSG、或BPSG；或类似物所形成。介电层508可通过旋转涂覆、层压、CVD、类似物、或其组合形成。接着介电层508被图案化，以形成开口，以暴露导电构件122的部分。图案化可通过可接受的工艺，诸如在介电层是光敏材料时通过将介电层508曝光或通过使用例如非等向性蚀刻剂的蚀刻。
因此，背侧RDL 120被形成以包含介电层504及508以及导电构件122。如所绘示，背侧RDL 120包含两个介电层以及一个金属化图案(如，导电构件122的图案)。在其它实施例中，背侧RDL 120可包含任何数目的介电层、金属化图案、及通路。一或更多个额外金属化图案及介电层可通过重复用于形成导电构件122及介电层508的工艺而形成在背侧RDL 120中。通路可在通过形成晶种层及导电构件的导电材料的金属化图案的形成期间被形成在下方介电层的开口中。通路因此可互连及电耦合各种导电构件。
接下来参考图5D，贯穿通路118被形成。作为用于形成贯穿通路118的一实例，晶种层形成在背侧RDL 120上方。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层及在钛层上方的铜层。晶种层可使用例如PVD或类似物形成。光阻形成并图案化在晶种层上。光阻可通过旋转涂覆或类似物形成且可使光阻曝光以兹图案化。光阻的图案对应于贯穿通路118。图案化形成贯穿光阻的开口，以暴露晶种层。导电材料形成在光阻的开口中且在晶种层的暴露的部份上。导电材料可通过镀覆形成，诸如电镀或无电式电镀、或类似物。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。光阻及其上未有导电材料形成的晶种层的部分被移除。光阻可通过可接受的灰化或剥除工艺移除，诸如使用氧等离子或类似物。一旦光阻被移除，晶种层的暴露的部分诸如通过使用可接受的蚀刻工艺移除，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分与导电材料形成贯穿通路118。
在图5E中，集成电路裸片102(标示为裸片102A、102B、及102C)通过粘合剂107粘附到介电层508。裸片102可包含如上所述的传感器裸片102A(如，具有指纹传感器逻辑电路)、微控制器裸片102B(如，具有指纹比较及验证逻辑电路)、及HV裸片102C。除了微控制器裸片102B及/或HV裸片102C之外或替代微控制器裸片102B及/或HV裸片102C，也可包含其它裸片。在粘附到介电层508之前，裸片102可根据可应用的制造工艺加工，以在裸片102中形成集成电路并包含如上所述的各种裸片构件。
如进一步所绘示，视需要的介电材料109设置在各集成电路裸片102上方，诸如在钝化膜105及接触垫103上。介电材料109侧向囊封视需要的导电柱111，导电柱111设置在接触垫103上且电连接到接触垫103。在一些实施例中，介电材料109与相应裸片102在侧向具有相同边界。介电材料109可以是聚合物，诸如PBO、聚酰亚胺、BCB、或类似物；氮化物，诸如氮化硅、或类似物；氧化物，诸如氧化硅、PSG、BSG、BPSG、或类似物；或其组合，且可通过例如旋转涂覆、层压、CVD、或类似物形成。在其它实施例中，(如，见图1A)，导电柱111及介电材料109可被省略。
粘合剂107设置在裸片102的背侧上并粘附裸片102到背侧RDL 120，诸如绘示说明中的介电层508。粘合剂107可以是任何合适的粘合剂、环氧化物、DAF、或类似物。粘合剂107可施加到裸片102的背侧，诸如到相应半导体晶圆的背侧、或可施加在载体衬底500的表面上方。裸片102可诸如通过锯切或切丁而单粒化，并使用例如拾取和放置工具而通过粘合剂107粘附到介电层502。
在图5F中，各种组件囊封在模塑料116中。在一实施例中，模塑料116可通过压缩成型、转印成型、类似物施加。在一实施例中，模塑料116可被施加以覆盖裸片102的顶部表面。在固化之后，模塑料116可经历研磨工艺，以暴露贯穿通路118及导电柱111。贯穿通路118的顶部表面、导电柱111的顶部表面、及模塑料116的顶部表面在研磨工艺之后共平面。在一些实施例中，研磨可省略，例如如果贯穿通路118及导电柱111已暴露时。
在另一实施例中，模塑料116可使用曝光成型工艺施加，例如在其中导电柱111及介电材料109被省略的实施例中。在一实施例曝光成型工艺中，具有离型膜(如，包含聚对苯二甲酸乙酯(polyethylene terephthalate，PET)、铁氟龙、或其它合适的材料)的模具套施加到裸片102的顶部表面，且模塑料116围绕裸片102注入。因为在模塑料116被注入同时离型膜施加到裸片102的顶部表面，模塑料116不形成在裸片102上方。因此，模塑料116不需在后续被平坦化，以暴露电连接体给裸片102。在一些实施例中，离型膜可进一步覆盖贯穿通路118的顶部表面。在其它实施例中，贯穿通路118在成型后形成，例如通过图案化开口在模塑料116中以及以导电材料填充开口。图案化开口可包含激光蚀刻工艺、光光刻及/或蚀刻的组合、及类似物。在其中使用曝光成型工艺的实施例中，模塑料116的顶部表面可与裸片102的顶部表面齐平或较低。
在图5G至5P中，前侧RDL 104被形成。如将于图5P中绘示，RDL 104包含多个介电层110、导电构件106、电极阵列108A、及手指驱动环108B。
在图5G中，介电层110A沉积在模塑料116、贯穿通路118、及导电柱111上。在一些实施例中，介电层110A可以是可使用光刻屏蔽图案化的光敏材料，诸如PBO、聚酰亚胺、BCB、或类似物。在其它实施例中，介电层110A可由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、BSG、或BPSG；或类似物所形成。介电层110A可通过旋转涂覆、层压、CVD、类似物、或其组合形成。
在图5H中，介电层110A接着被图案化。图案化形成开口，以暴露贯穿通路118的部分及导电柱111的部分(或在其中排除导电柱111的实施例中的接触垫103的部分)。图案化可通过可接受的工艺，诸如在介电层110A是光敏材料时通过将介电层110A曝光或通过使用例如非等向性蚀刻剂的蚀刻。如果介电层110A是光敏材料，介电层110A可在曝光后被显影。
在5I中，具有通路的导电构件106形成在介电层110A上。作为用于形成导电构件的一实例，晶种层(未显示)形成在介电层110A上方以及在贯穿介电层110A的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层及在钛层上方的铜层。晶种层可使用例如PVD或类似物形成。接着光阻形成并图案化在晶种层上。光阻可通过旋转涂覆或类似物形成且可使光阻曝光以兹图案化。光阻的图案对应于导电构件106。图案化形成贯穿光阻的开口，以暴露晶种层。导电材料形成在光阻的开口中且在晶种层的暴露的部份上。导电材料可通过镀覆形成，诸如电镀或无电式电镀、或类似物。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。接着，光阻及其上未有导电材料形成的晶种层的部分被移除。光阻可通过可接受的灰化或剥除工艺移除，诸如使用氧等离子或类似物。一但光阻被移除，晶种层的暴露的部分诸如通过使用可接受的蚀刻工艺移除，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分与导电材料形成导线106A及导电通路106B。导电通路106B形成在贯穿介电层110A到如贯穿通路118及/或导电柱111(或在其中排除导电柱111的实施例中的接触垫103)的开口中。在各种实施例中，导电构件106在个别裸片102之间提供电路由，以及使用贯穿通路118在裸片102与在背侧RDL 120之间提供电路由接。
在图5J中，介电层110B沉积在导电构件106及介电层110A上。在一些实施例中，介电层110B是由聚合物所形成，所述聚合物可以是可使用光刻屏蔽图案化的光敏材料，诸如PBO、聚酰亚胺、BCB、或类似物。在其它实施例中，介电层110B可由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、BSG、或BPSG；或类似物所形成。介电层110B可通过旋转涂覆、层压、CVD、类似物、或其组合形成。
在图5K中，介电层110B接着被图案化。图案化形成开口，以暴露导电构件106的部分。图案化可通过可接受的工艺，诸如在介电层是光敏材料时通过将介电层110B曝光或通过使用例如非等向性蚀刻剂的蚀刻。如果介电层110B是光敏材料，介电层110B可在曝光后被显影。
在5L中，具有通路的额外导电构件106形成在介电层110B上。作为用于形成额外导电构件106的一实例，晶种层(未显示)形成在介电层110B上方以及在贯穿介电层110B的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层及在钛层上方的铜层。晶种层可使用例如PVD或类似物形成。接着光阻形成并图案化在晶种层上。光阻可通过旋转涂覆或类似物形成且可使光阻曝光以兹图案化。光阻的图案对应于额外导电构件106的金属化图案。图案化形成贯穿光阻的开口，以暴露晶种层。导电材料形成在光阻的开口中且在晶种层的暴露的部份上。导电材料可通过镀覆形成，诸如电镀或无电式电镀、或类似物。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。接着，光阻及其上未有导电材料形成的晶种层的部分被移除。光阻可通过可接受的灰化或剥除工艺移除，诸如使用氧等离子或类似物。一但光阻被移除，晶种层的暴露的部分诸如通过使用可接受的蚀刻工艺移除，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分与导电材料形成额外导电构件106。额外导电构件106的通路形成在贯穿介电层110B到如在介电层110A中的下导电构件106的部分的开口中。
在图5M中，介电层110C沉积在导电构件106及介电层110B上。在一些实施例中，介电层110C是由聚合物所形成，所述聚合物可以是可使用光刻屏蔽图案化的光敏材料，诸如PBO、聚酰亚胺、BCB、或类似物。在其它实施例中，介电层110C可由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、BSG、或BPSG；或类似物所形成。介电层110C可通过旋转涂覆、层压、CVD、类似物、或其组合形成。在一些实施例中，为了改善隔离，介电层110C厚于介电层110A或110B，而使得后续形成的电极阵列108A(见图1B及5O)可被间隔而更远离导电构件106。
在图5N中，介电层110C接着被图案化。图案化形成开口，以暴露导电构件106的部分。图案化可通过可接受的工艺，诸如在介电层是光敏材料时通过将介电层110C曝光或通过使用例如非等向性蚀刻剂的蚀刻。如果介电层110C是光敏材料，介电层110C可在曝光后被显影。
在图5O中，具有通路的金属化图案108形成在介电层148上。作为用于形成金属化图案108的一实例，晶种层(未显示)形成在介电层110C上方以及在贯穿介电层110C的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括多个由不同材料形成的子层的复合层。在一些实施例中，晶种层包括钛层及在钛层上方的铜层。晶种层可使用例如PVD或类似物形成。接着光阻形成并图案化在晶种层上。光阻可通过旋转涂覆或类似物形成且可使光阻曝光以兹图案化。光阻的图案对应于金属化图案108。图案化形成贯穿光阻的开口，以暴露晶种层。导电材料形成在光阻的开口中且在晶种层的暴露的部份上。导电材料可通过镀覆形成，诸如电镀或无电式电镀、或类似物。导电材料可包括金属，像是铜、钛、钨、铝、或类似物。接着，光阻及其上未有导电材料形成的晶种层的部分被移除。光阻可通过可接受的灰化或剥除工艺移除，诸如使用氧等离子或类似物。一但光阻被移除，晶种层的暴露的部分诸如通过使用可接受的蚀刻工艺移除，诸如通过湿蚀刻或干蚀刻。晶种层的剩余部分与导电材料形成金属化图案108。
金属化图案108包含电极阵列108A、手指驱动环108B、及通路108C。如上所述，电极阵列可被传感器裸片102A使用来检测施加到指纹传感器封装件100的手指的指纹。手指驱动环108B可用以施加电压到施加到指纹传感器封装件的手指并改善整体指纹传感器灵敏度。通路108C形成在贯穿介电层110的开口中且用以电连接电极阵列108A及手指驱动108B到裸片102。因为介电层110C相对较厚地沉积，通路108C可具有大于导电构件106的通路106B(见图5I)的纵向尺寸。电极阵列108A及手指驱动108B可具有合适的构形，诸如上面关于图3A至4E描述的构形。
在图5P中，介电层110D沉积在金属化图案件108及介电层110C上。在一些实施例中，介电层110D是由聚合物所形成，所述聚合物可以是可使用光刻屏蔽图案化的光敏材料，诸如PBO、聚酰亚胺、BCB、或类似物。在其它实施例中，介电层110D可由氮化物诸如氮化硅；氧化物诸如氧化硅、PSG、B SG、或BP SG；或类似物所形成。介电层110D可通过旋转涂覆、层压、CVD、类似物、或其组合形成。在一些实施例中，介电层110D作为钝化层，以在指纹传感器装置封装件150的后续加工及/或操作期间保护下方金属化图案108。
在图5Q中，载体衬底去接合被实施以将载体衬底500从背侧RDL 120，如介电层504去附接(去接合)。根据一些实施例，去接合包含将光诸如激光或UV光投射在离型层502上，以便离型层502在光的热下分解且载体衬底500可被移除。所述结构接着被翻转且放置在胶带510上。
如图5Q中进一步所绘示，在载体衬底500去接合之后，开口贯穿介电层504形成，以暴露导电构件122的部分。开口可通过例如激光钻孔、蚀刻、或类似物形成。连接件126'可设置在介电层504中的开口中。在一些实施例中，连接件126'包括在后续工艺步骤中用以与焊球连接的焊料糊。又者，单粒化工艺(未绘示)可沿着切割线区，如在相邻装置封装件150(未绘示)之间实施。锯切将封装件150与其它封装件(未绘示)单粒化。
在图5R中，另一封装件组件130(另一装置裸片、插置件、封装件衬底、印刷电路板、母板、或类似物)通过连接件126接合到背侧RDL 120。在一实施例中，连接件126是焊球，其施加到在导电构件122上的焊料糊126(见图5Q)。连接件126电连接导电构件122到在封装件组件130中的导电构件128。底胶填充124也可围绕连接件126分注。
在图5S中，传感器表面材料114(如，蓝宝石、玻璃、或类似物)在胶层112的帮助下粘附到扇出RDL 104的顶部表面(如，与裸片102相对的扇出RDL 104的表面)。在一实施例中，胶层112是色膜或粘合胶，诸如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合。然而，可利用任何其它合适的材料。因此，整合扇出(InFO)指纹装置封装件150可被完成以在扇出RDL 104中具有电极阵列108A及手指驱动环108B。
图6A至6G根据一些实施例绘示制造指纹传感器装置封装件250(见图2B)的中间步骤的剖面图。图6A绘示载体衬底600以及形成在载体衬底600上的粘合剂107。在各种实施例中，载体衬底600可与载体衬底500(见图5A)实质上相同。粘合剂107可包括DAF，诸如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合，且使用层压技术施加到载体衬底600。
在图6B中，裸片102通过粘合剂107附接到载体衬底600。裸片102可包含如上所述的传感器裸片、微控制器裸片、及HV裸片。也可包含其它裸片。裸片102可视需要包含导电注111及围绕导电注111形成的介电材料109。值得注意的是，裸片102附接到载体衬底600而没有先形成任何贯穿通路或背侧RDL。
在图6C中，模塑料116使用与如上面关于图5F描述者相似的工艺而围绕裸片102形成。例如，模塑料116可通过压缩成型、转印成型、类似物施加。在固化之后，模塑料116可经历研磨工艺，以暴露贯穿通路118及导电柱111。贯穿通路118的顶部表面、导电柱111的顶部表面、及模塑料116的顶部表面在研磨工艺之后共平面。作为另一实例，模塑料116可使用曝光成型工艺施加。在一实施例曝光成型工艺中，具有离型膜(如，包含PET、铁氟龙、或其它合适的材料)的模具套施加到裸片102的顶部表面，且模塑料116围绕裸片102注入。因为在模塑料116被注入同时离型膜施加到裸片102的顶部表面，模塑料116不形成在裸片102上方。因此，模塑料116不需在后续被平坦化，以暴露电连接体给裸片102。在其中使用曝光成型工艺的实施例中，模塑料116的顶部表面可与裸片102的顶部表面齐平或较低。
在图6D中，扇出RDL 104使用例如与如上面关于图5G至5P描述的那些相似的工艺形成在裸片102及模塑料116上方。扇出RDL 104包含具有导电构件106设置于其中之下介电层110A及110B。导电构件106电互连在装置封装件250内的各种裸片102。扇出RDL 104进一步包含具有电极阵列108A及手指驱动环108B设置于其中的上介电层110C及110D。导电通路电连接电极阵列108A及手指驱动环108B到导电构件106及裸片102。
上介电层110C进一步包含接触垫136以提供电连接到其它装置构件。接触垫136可与电极阵列108A及手指驱动环108B实质上齐平。虽然图6D将接触垫136绘示成被设置在被手指驱动108B圈住的区域之外，在其它实施例中，手指驱动108B圈住接触垫136(见如图2A)。
在图6E中，最顶部介电层110D被图案化。图案化形成开口，以暴露接触垫136的部分。图案化可通过可接受的工艺，诸如在介电层是光敏材料时通过将介电层110D曝光或通过使用例如非等向性蚀刻剂的蚀刻。如果介电层110D是光敏材料，介电层110D可在曝光后被显影。
在图6F中，连接件126可设置在介电层110D中的开口中。在一些实施例中，连接件126包括焊料糊、焊球、或类似物。又者，单粒化工艺(未绘示)可沿着切割线区，如在相邻装置封装件100(未绘示)之间实施。锯切将封装件250与其它封装件(未绘示)单粒化。
在图6G中，传感器表面材料114(如，蓝宝石、玻璃、或类似物)在胶层112的帮助下粘附到扇出RDL 104的顶部表面(如，与裸片102相对的扇出RDL 104的表面)。在一实施例中，胶层112是色膜或粘合胶，诸如环氧树脂、酚树脂、丙烯酸系橡胶、二氧化硅填料、或其组合。然而，可利用任何其它合适的材料。因此，InFO指纹装置封装件250可被完成以在扇出RDL 104中具有电极阵列108A及手指驱动环108B。在后续工艺步骤中，焊线可用以电连接其它封装件组件到连接件126(见图2B)。
因此如上所述，实施例指纹传感器装置封装件包含传感器裸片；以及电极阵列，其形成在设置在所述传感器裸片上方的扇出RDL中。实施例封装件可进一步包含额外裸片，且所述电极阵列也可延伸在其它裸片上方。在一些实施例中，手指驱动环圈住所述电极阵列以便有源电容法可用以确定施加到所述指纹传感器装置封装件的手指的轮廓。各种实施例可达成一或多个下列非限制性优点：由于在所施加手指传感器像素阵列(如，电极阵列)之间减少的间距所致改善的灵敏度、由于控制电路的芯片大小减少所致较低制造成本及/或较小形状因子、由于在扇出RDL内整合所致手指驱动环的成本减少、增进使用RF讯号法来指纹检测的灵敏度，由于HV芯片整合所致增加的灵敏度、以及由于整合在传感器模块中的微控制器裸片所致增加的安全性水平。
根据一实施例，一种装置封装件包含传感器裸片；一或多个额外裸片，其相邻于所述传感器裸片；以及模塑料，其圈住所述传感器裸片及所述一或多个额外裸片。所述装置封装件进一步包含重布层，所述重布层在所述传感器裸片、所述一或多个额外裸片、及所述模塑料上方。所述重布层包含第一导电构件，所述第一导电构件在第一介电层中。所述第一导电构件电连接所述传感器裸片到所述一或多个额外裸片。所述重布层进一步包含电极阵列，所述电极阵列在第二介电层中且电连接到所述传感器裸片，所述第二介电层在所述第一介电层上方。
根据另一实施例，一种装置封装件包含传感器裸片；模塑料，其沿着所述传感器裸片的侧壁延伸；以及第一介电层，其在所述传感器裸片及所述模塑料上方。所述装置封装件进一步包含电极阵列，所述电极阵列在所述第一介电层中且电连接到所述传感器裸片。所述电极阵列侧向延伸超过所述传感器裸片。所述装置封装件进一步包含手指驱动环，所述手指驱动环在所述第一介电层中且圈住所述电极阵列。所述手指驱动环电连接到所述传感器裸片。
根据又一实施例，一种用于形成半导体装置的方法包含囊封传感器裸片及一或多个额外裸片在模塑料中，沉积第一介电层在所述模塑料、所述传感器裸片、及所述一或多个额外裸片上方，以及形成导电构件在所述第一介电层中。所述导电构件电连接所述传感器裸片到所述一或多个额外裸片。所述方法进一步包含沉积第二介电层在所述第一介电层及所述导电构件上方，以及形成电极阵列在所述第二介电层上方。所述电极阵列电连接到所述传感器裸片。所述方法进一步包含沉积第三介电层在所述电极阵列上方，以及附接传感器表面材料到所述第三介电层。
前面列述了数个实施例的特征以便所属领域的技术人员可更佳地理解本揭露的方面。所属领域的技术人员应了解，它们可轻易地使用本揭露作为用以设计或修改其它工艺及结构的基础以实现本文中所介绍实施例的相同目的及/或达成本文中所介绍实施例的相同优点。所属领域的技术人员也应认识到这些均等构造不会背离本揭露的精神及范围，以及它们可在不背离本揭露的精神及范围下做出各种改变、取代、或替代。
符号说明
100 指纹传感器装置封装件
102 裸片
102A 传感器裸片
102B 高电压裸片
102C 微控制器裸片
103 接触垫
104 扇出重布层
104A 下层
104B 上层
105 钝化层
106 导电构件
106A 导线
106B 导电通路
107 粘合剂
108 导电构件
108A 电极阵列
108B 手指驱动环
108C 导电通路
109 介电材料
110 介电层
110A 介电层
110B 介电层
110C 介电层
110D 介电层
111 接触柱
112 胶层
114 传感器表面材料
116 模塑料
118 贯穿通路
120 背侧RDL
122 导电构件
124 底胶填充
126 焊球
126' 连接件
128 导电构件
130 封装件组件
132 焊线
134 支撑衬底
136 接触垫
148 介电层
150 封装件
172 轮廓
172A 线
127B 线
174 凹谷
176 凸脊
200 指纹传感器装置封装件
202 装置
250 指纹传感器装置封装件
402 外环
402A 第一区段
402B 第二区段
402C 第三区段
402D 第四区段
404 内环
404' 区段
404” L形区段
406 导电材料带
408 十字形部分
500 载体衬底
502 离型层
504 介电层
508 介电层
510 胶带
600 载体衬底
T1 距离
T2 距离
T3 距离
T4 距离
T5 距离
T6 距离
D1 距离
D2 距离
W1 宽度
W2 宽度
L1 长度

Claims (10)

1.一种装置封装件，其包括：
传感器裸片；
一或多个额外裸片，其相邻于所述传感器裸片；
模塑料，其圈住所述传感器裸片及所述一或多个额外裸片；以及
第一重布层，其在所述传感器裸片、所述一或多个额外裸片、及所述模塑料上方，其中所述第一重布层包括：
第一导电构件，其在第一介电层中，其中所述第一导电构件电连接所述传感器裸片到所述一或多个额外裸片；以及
电极阵列，其在第二介电层中且电连接到所述传感器裸片，其中所述第二介电层设置在所述第一介电层上方。
2.根据权利要求1所述的装置封装件，其中所述第一重布层进一步包括手指驱动环，所述手指驱动环在所述第二介电层中且圈住所述电极阵列，其中所述手指驱动环电连接到所述传感器裸片。
3.根据权利要求2所述的装置封装件，其中所述第一重布层进一步包括：
接触垫，其在所述第二介电层中，其中所述手指驱动环圈住所述接触垫；以及
外部连接件，其在所述接触垫上。
4.根据权利要求2所述的装置封装件，其中所述第一重布层进一步包括：
接触垫，其在所述第二介电层中，其中所述接触垫设置在被所述手指驱动圈住的区域之外；以及
外部连接件，其在所述接触垫上。
5.根据权利要求1所述的装置封装件，其中所述电极阵列直接延伸在所述一或多个额外裸片的至少一者上方。
6.一种装置封装件，其包括：
传感器裸片；
模塑料，其沿着所述传感器裸片的侧壁延伸；
第一介电层，其在所述传感器裸片及所述模塑料上方；
电极阵列，其在所述第一介电层中且电连接到所述传感器裸片，其中所述电极阵列侧向延伸超过所述传感器裸片；以及
手指驱动环，其在所述第一介电层中且圈住所述电极阵列，其中所述手指驱动环电连接到所述传感器裸片。
7.根据权利要求6所述的装置封装件，其中所述手指驱动环包括：
外环；
内环，其被所述外环圈住，其中所述第一介电层的一部分设置在所述内环与所述外环之间；以及
一或多个导电材料带，其连接所述内环到所述外环。
8.根据权利要求7所述的装置封装件，其中所述内环是围绕所述电极阵列的连续环。
9.根据权利要求7所述的装置封装件，其中所述内环包括多个不连续区段，其中所述第一介电层的一部分设置在所述不连续片段的各者之间，其中所述不连续片段的各者通过所述一或多个导电材料带连接到外环。
10.一种用于形成装置封装件的方法，其包括：
囊封传感器裸片及一或多个额外裸片在模塑料中；
沉积第一介电层在所述模塑料、所述传感器裸片、及所述一或多个额外裸片上方；
形成导电构件在所述第一介电层中，其中所述导电构件电连接所述传感器裸片到所述一或多个额外裸片；
沉积第二介电层在所述第一介电层及所述导电构件上方；
形成电极阵列在所述第二介电层上方且电连接到所述传感器裸片；
沉积第三介电层在所述电极阵列上方；以及
附接传感器表面材料到所述第三介电层。
CN201710073702.6A 2016-02-10 2017-02-10 装置封装件以及用于形成装置封装件的方法 Active CN107068627B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662293732P 2016-02-10 2016-02-10
US62/293,732 2016-02-10
US15/200,871 2016-07-01
US15/200,871 US9904776B2 (en) 2016-02-10 2016-07-01 Fingerprint sensor pixel array and methods of forming same

Publications (2)

Publication Number Publication Date
CN107068627A true CN107068627A (zh) 2017-08-18
CN107068627B CN107068627B (zh) 2020-05-15

Family

ID=59497796

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710073702.6A Active CN107068627B (zh) 2016-02-10 2017-02-10 装置封装件以及用于形成装置封装件的方法

Country Status (4)

Country Link
US (4) US9904776B2 (zh)
KR (1) KR101913913B1 (zh)
CN (1) CN107068627B (zh)
TW (1) TWI596550B (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108155160A (zh) * 2018-01-29 2018-06-12 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN109817587A (zh) * 2017-11-22 2019-05-28 台湾积体电路制造股份有限公司 形成半导体结构的方法及封装件
CN113496961A (zh) * 2020-04-02 2021-10-12 富泰华工业（深圳）有限公司 指纹识别芯片封装结构及其制作方法
CN114556452A (zh) * 2021-02-05 2022-05-27 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3792960A3 (en) 2016-04-11 2021-06-02 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Batch manufacture of component carriers
US10199318B2 (en) 2016-05-19 2019-02-05 Mediatek Inc. Semiconductor package assembly
US10354114B2 (en) * 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10128201B2 (en) * 2017-02-16 2018-11-13 Globalfoundries Singapore Pte. Ltd. Seal ring for wafer level package
JP6662337B2 (ja) * 2017-03-27 2020-03-11 信越化学工業株式会社 半導体装置及びその製造方法、並びに積層体
TWI628602B (zh) * 2017-09-26 2018-07-01 北京集創北方科技股份有限公司 指紋採集裝置之雜訊抑制方法
CN107609542B (zh) * 2017-10-24 2021-01-26 京东方科技集团股份有限公司 光感器件、显示装置及指纹识别方法
SE1751447A1 (en) * 2017-11-24 2019-05-25 Fingerprint Cards Ab Cost-efficient fingerprint sensor component and manufacturing method
KR101933423B1 (ko) 2017-11-28 2018-12-28 삼성전기 주식회사 팬-아웃 센서 패키지
KR102029099B1 (ko) * 2018-02-05 2019-10-07 삼성전자주식회사 반도체 패키지
US11031358B2 (en) 2018-03-01 2021-06-08 Marvell Asia Pte, Ltd. Overhang model for reducing passivation stress and method for producing the same
TWI678766B (zh) * 2018-04-26 2019-12-01 沅顧科技有限公司 一種製造一系統於一可主動控制基板上的方法
US11380616B2 (en) * 2018-05-16 2022-07-05 Intel IP Corporation Fan out package-on-package with adhesive die attach
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
TWI712959B (zh) * 2018-09-19 2020-12-11 世界先進積體電路股份有限公司 光學感測器及其形成方法
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US10915727B2 (en) 2018-12-28 2021-02-09 Vanguard International Semiconductor Corporation Optical sensor and method for forming the same
KR102595865B1 (ko) * 2019-03-04 2023-10-30 삼성전자주식회사 하이브리드 인터포저를 갖는 반도체 패키지
US11456247B2 (en) * 2019-06-13 2022-09-27 Nanya Technology Corporation Semiconductor device and fabrication method for the same
US11557491B2 (en) * 2019-10-31 2023-01-17 Nxp B.V. Selective underfill assembly and method therefor
US20210202472A1 (en) * 2019-12-27 2021-07-01 Intel Corporation Integrated circuit structures including backside vias
TW202143343A (zh) 2020-04-30 2021-11-16 力成科技股份有限公司 半導體封裝結構及其製造方法
FR3111215B1 (fr) * 2020-06-04 2022-08-12 Linxens Holding Module de capteur biométrique pour carte à puce et procédé de fabrication d’un tel module
TWM612841U (zh) * 2021-02-19 2021-06-01 安帝司股份有限公司 指紋辨識智慧卡
KR20220161767A (ko) * 2021-05-31 2022-12-07 삼성전자주식회사 반도체 패키지 장치
WO2023014670A1 (en) * 2021-08-02 2023-02-09 Resonant Inc. Transversely-excited film bulk acoustic resonator (xbar)
US20230065405A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11963291B2 (en) 2022-04-21 2024-04-16 Nxp B.V. Efficient wave guide transition between package and PCB using solder wall
KR20240018865A (ko) * 2022-08-03 2024-02-14 삼성전자주식회사 지문 센서 패키지 및 이를 포함하는 스마트 카드

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060203403A1 (en) * 2005-03-08 2006-09-14 Schediwy Richard R Strike ring based electrostatic discharge protection
CN101127331A (zh) * 2006-08-18 2008-02-20 国际商业机器公司 包括半导体芯片的电子封装及其制造方法
CN101211903A (zh) * 2006-12-29 2008-07-02 育霈科技股份有限公司 射频模块封装结构及其形成方法
CN102544032A (zh) * 2010-12-10 2012-07-04 三星电子株式会社 晶片规模x射线检测器及其制造方法
US20140138788A1 (en) * 2012-11-20 2014-05-22 Amkor Technology, Inc. Package of finger print sensor and fabricating method thereof
US20140171158A1 (en) * 2012-12-18 2014-06-19 Apple Inc. Biometric finger sensor including array shielding electrode and related methods
TW201428639A (zh) * 2012-10-14 2014-07-16 Synaptics Inc 指紋感測器與按鈕組合及製造方法
US20140367160A1 (en) * 2013-03-12 2014-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Electric magnetic shielding structure in packages

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956415A (en) * 1996-01-26 1999-09-21 Harris Corporation Enhanced security fingerprint sensor package and related methods
JP3947443B2 (ja) 2002-08-30 2007-07-18 Ｔｄｋ株式会社 電子デバイス用基板および電子デバイス
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US7259055B2 (en) 2005-02-24 2007-08-21 Sharp Laboratories Of America, Inc. Method of forming high-luminescence silicon electroluminescence device
US20080179762A1 (en) 2007-01-25 2008-07-31 Au Optronics Corporation Layered structure with laser-induced aggregation silicon nano-dots in a silicon-rich dielectric layer, and applications of the same
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8446017B2 (en) * 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
EP2557597A4 (en) 2010-04-07 2014-11-26 Shimadzu Corp RADIATION DETECTOR AND METHOD FOR MANUFACTURING SAME
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US20150187707A1 (en) 2012-10-14 2015-07-02 Synaptics Incorporated Biometric Image Sensor Packaging and Mounting
KR20140052539A (ko) 2012-10-24 2014-05-07 크루셜텍 (주) 지문센서 패키지 및 이를 구비한 휴대용 전자기기
US9443126B2 (en) * 2012-11-20 2016-09-13 Crucialtec Co., Ltd. Fingerprint sensor module, portable electronic device including same, and method for manufacturing same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
KR20150018350A (ko) * 2013-08-08 2015-02-23 삼성전자주식회사 지문인식장치와 그 제조방법 및 전자기기
TWI594341B (zh) * 2015-01-19 2017-08-01 神盾股份有限公司 指紋辨識裝置封裝及其製造方法
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060203403A1 (en) * 2005-03-08 2006-09-14 Schediwy Richard R Strike ring based electrostatic discharge protection
CN101127331A (zh) * 2006-08-18 2008-02-20 国际商业机器公司 包括半导体芯片的电子封装及其制造方法
CN101211903A (zh) * 2006-12-29 2008-07-02 育霈科技股份有限公司 射频模块封装结构及其形成方法
CN102544032A (zh) * 2010-12-10 2012-07-04 三星电子株式会社 晶片规模x射线检测器及其制造方法
TW201428639A (zh) * 2012-10-14 2014-07-16 Synaptics Inc 指紋感測器與按鈕組合及製造方法
US20140138788A1 (en) * 2012-11-20 2014-05-22 Amkor Technology, Inc. Package of finger print sensor and fabricating method thereof
US20140171158A1 (en) * 2012-12-18 2014-06-19 Apple Inc. Biometric finger sensor including array shielding electrode and related methods
US20140367160A1 (en) * 2013-03-12 2014-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Electric magnetic shielding structure in packages

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817587A (zh) * 2017-11-22 2019-05-28 台湾积体电路制造股份有限公司 形成半导体结构的方法及封装件
CN109817587B (zh) * 2017-11-22 2020-10-30 台湾积体电路制造股份有限公司 形成半导体结构的方法及封装件
US10964650B2 (en) 2017-11-22 2021-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure and method forming same
US11682636B2 (en) 2017-11-22 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure and method forming same
CN108155160A (zh) * 2018-01-29 2018-06-12 中芯长电半导体（江阴）有限公司 指纹识别芯片的封装结构及封装方法
CN113496961A (zh) * 2020-04-02 2021-10-12 富泰华工业（深圳）有限公司 指纹识别芯片封装结构及其制作方法
CN114556452A (zh) * 2021-02-05 2022-05-27 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备
WO2022165775A1 (zh) * 2021-02-05 2022-08-11 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备
CN114556452B (zh) * 2021-02-05 2023-05-02 深圳市汇顶科技股份有限公司 芯片封装结构和电子设备

Also Published As

Publication number Publication date
KR101913913B1 (ko) 2018-10-31
US9904776B2 (en) 2018-02-27
US10698994B2 (en) 2020-06-30
CN107068627B (zh) 2020-05-15
US20170228529A1 (en) 2017-08-10
TW201729139A (zh) 2017-08-16
US10157274B2 (en) 2018-12-18
US20180181738A1 (en) 2018-06-28
US20200327214A1 (en) 2020-10-15
TWI596550B (zh) 2017-08-21
US10878073B2 (en) 2020-12-29
KR20170094483A (ko) 2017-08-18
US20190121952A1 (en) 2019-04-25

Similar Documents

Publication Publication Date Title
CN107068627A (zh) 装置封装件以及用于形成装置封装件的方法
US10853616B2 (en) Fingerprint sensor device and method
US20200168572A1 (en) Semiconductor package assembly having a conductive electromagnetic shield layer
EP3091571B1 (en) Fan-out package structure including a conductive shielding layer
US11043730B2 (en) Fan-out package structure with integrated antenna
EP3163614B1 (en) Stacked fan-out package structure
US9553062B1 (en) Fingerprint identification device
US20170271265A1 (en) Semiconductor device and wafer level package including such semiconductor device
EP3273475B1 (en) Fan-out package structure
US20220319925A1 (en) Integrated circuit component and package structure having the same
TW201505143A (zh) 晶片封裝體及其製造方法
US11257787B2 (en) Package structure and method of fabricating the same
US20230021764A1 (en) Method for forming package structure with cavity substrate
EP3418941B1 (en) Fingerprint recognition module and fingerprint recognition chip packaging structure
US11495507B2 (en) Manufacturing method of a semiconductor package
TWI593069B (zh) 晶片封裝體及其製造方法
TWI688049B (zh) 電子封裝件及其製法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant