CN101065840A - 半导体装置以及制造包括多堆栈混合定向层之半导体装置之方法 - Google Patents

半导体装置以及制造包括多堆栈混合定向层之半导体装置之方法 Download PDF

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CN101065840A
CN101065840A CNA2005800401881A CN200580040188A CN101065840A CN 101065840 A CN101065840 A CN 101065840A CN A2005800401881 A CNA2005800401881 A CN A2005800401881A CN 200580040188 A CN200580040188 A CN 200580040188A CN 101065840 A CN101065840 A CN 101065840A
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A·M·韦特
J·D·奇克
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GlobalFoundries Inc
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Abstract

一种包括具有第一晶向的衬底的半导体装置。第一绝缘材料位于衬底上且多个硅层位于第一绝缘层上。第一硅层包含具有第二晶向和一晶面的硅。第二硅层包含具有该第二晶向和基本上与该第一硅层的晶面垂直的晶面的硅。因为空穴在(110)面比在(100)面具有更高的迁移率，而电子在(100)面比在(110)具有更高的迁移率，故可藉由选择具有某晶面定向的硅层而增进半导体装置的效能。此外，提供形成半导体装置的方法。绝缘体上硅结构键合至第二硅衬底，该绝缘体上硅结构包括有第一绝缘层形成于其上的、具有第一晶向的第一硅衬底，以及位于该第一绝缘层上的具有第二晶向和晶面的第一硅层。该第二硅衬底具有第二晶向和一晶面以及形成于其上的第二绝缘层。该第二硅衬底包括通过注入氢离子至该第二硅衬底而产生的缺陷线。该第二硅衬底的晶面定向为基本上与该第一硅层的晶面垂直。该第二硅衬底沿缺陷线分裂和移除而在绝缘体上硅结构上留下第二绝缘层和第二硅层。通过选择性蚀刻绝缘体上硅结构至不同晶向的硅层、在蚀刻的区域生长选择性外延硅层、以及接着以化学机械研磨方式平坦化绝缘体上硅结构，而可接着形成多个具有不同晶向的装置在单一、平面的绝缘体上硅结构上。

Description

半导体装置以及制造包括多堆栈混合定向层之半导体装置之方法
技术领域
本发明是关于半导体装置以及制造半导体装置的方法，更详而言之，是关于包括绝缘体上硅(silicon-on-insulator，简称SOI)技术的改良半导体装置。
背景技术
在半导体产业中持续研发之重要目标为在增加半导体效能的同时减少半导体装置的功率消耗。诸如金属氧化物半导体场效晶体管(MOSFET)的平面型晶体管(planar transistor)特别适合用于高密度集成电路。当MOSFET以及其它装置的尺寸减小时，该装置的源极/漏极区域、沟道(channel)区域、以及栅极电极的大小亦减小。
具有短沟道长度持续更小的平面型晶体管的设计需要提供非常浅的源极/漏极结(junction)。浅结需要避免注入的掺杂物侧向扩散至沟道内，因为此种扩散不利地造成漏电流(leakage current)以及不佳的击穿(breakdown)效能。通常在短沟道装置中可接受的效能需要深度为1000埃()等级或更小的浅源极/漏极。
绝缘体上硅(SOI)技术允许形成高速、浅结装置。此外，SOI装置通过减少寄生结电容(parasitic junction capacitance)而改进效能。
在SOI衬底中，由氧化硅制成的埋设氧化物(buried oxide)(BOX)膜形成于单晶硅上，而单晶硅薄膜形成于其上。各种制造此种SOI衬底的方法为已知的。其中一种方法为通过注入氧分离(Separation-by-Implanted Oxygen)(SIMOX)的方法，其中离子注入氧至单晶硅衬底以形成埋设氧化物(BOX)膜。
另一种形成SOI衬底的方法为晶圆键合(wafer bonding)，其中将具有氧化硅表面层的两个半导体衬底共同键合在该氧化硅表面以形成BOX层于该等两个半导体衬底间。
另一种SOI技术为Smart Cut，其亦有关经由氧化物层而键合半导体衬底。在Smart Cut方法中，在键合前以氢离子注入其中一个半导体衬底。该氢离子注入接着使经氢离子注入的衬底自键合的衬底中分离，而留下硅薄层在表面上。
可通过选择具有某晶面定向(crystal plane orientations)的硅层而进一步提升半导体装置效能，该晶面定向有利于空穴或电子流动。例如，若将P型MOSFETs(PMOSFETs)制造于(110)硅表面上，且将栅极定向使空穴于(110)/<110>的方向流动，则可改良PMOSFETs的效能。在(110)/<110>方向流动的空穴的迁移率(mobility)比在习知(100)/<110>方向流动的空穴的迁移率的两倍还高。不幸地，在(110)表面上以对(110)/<110>方向之成直角(right angles)移动的空穴在(110)/<100>方向流动。在(110)/<100>方向的空穴的迁移率只有在(110)/<110>方向流动的空穴的迁移率的2/3。此外，在(110)面的电子迁移率比在习知(100)面的电子迁移率低很多。
此处所应用的术语「半导体装置」不限于特定揭露的实施例。此处所应用的半导体装置包含种类广泛的电子装置，其包含覆晶(flipchips)、覆晶/封装组合(package assemblies)、晶体管、电容器、微处理器、随机存取存储器等。通常，半导体装置是指任何包括半导体的电子装置。
发明内容
在半导体装置技艺中存在结合SOI技术的效能改良以及理想硅晶向(crystal orientation)的需求。在此技艺中进一步存在包括MOSFET的半导体装置的需求，其中PMOSFETs和NMOSFETs分别制造于对于空穴(hole)和电子迁移率而言为理想的硅表面上。在此技艺中亦存在形成包括SOI技术及理想硅晶向之半导体装置之方法之需求。此外，在此技艺中存在形成包括MOSFETs之半导体装置之方法之需求，其中PMOSFETs和NMOSFETs制造于对于空穴和电子迁移率而言为理想的硅表面上。
本发明的实施例符合这些及其它需求，其提供包括具有第一晶向的衬底的半导体装置。第一绝缘层应在该衬底上，且多个硅层位于该第一绝缘层上。第一硅层包括具有第二晶向和晶面的硅。第二硅层包括具有该第二晶向及基本上与第一硅层的晶面垂直的晶面的硅。
本发明的实施例还符合这些及其它需求，其提供形成半导体装置的方法，包括：设置绝缘体上硅结构，该绝缘体上硅结构包括有第一绝缘层形成于其上的具有第一晶向的第一硅衬底，以及位于第一绝缘层上的具有第二晶向和一晶面的第一硅层。提供第二硅衬底，其具有该第二晶向及一晶面以及形成于该第二衬底上的第二绝缘层。第二硅衬底包括通过注入氢离子至该第二硅衬底所产生的缺陷线(a line ofdefects)。经由该第二绝缘层及该第一硅层而键合该第二硅衬底至该绝缘体上硅结构，以使该第二硅衬底的晶面定向为基本上垂直于该第一硅层的晶面。该第二硅衬底沿缺陷线分裂和移除，而在该绝缘体上硅结构上留下该第二绝缘层及第二硅层。
本发明满足具有改良电子特性的改良高速半导体装置的需求。
本发明的上述及其它特点、方面、以及优点将在以下本发明的详
附图说明
图1至18说明具有形成于一般衬底上不同晶向的硅层上的MOSFET的SOI半导体装置的形成；
图19说明通过注入氧离子至SOI结构而形成埋设氧化物层；以及
图20说明具有形成于相同衬底上不同晶向的硅层上的MOSFET的SOI半导体装置的替代实施例。
具体实施方式
本发明能够制造具有SOI技术的优点以及形成于一般硅衬底上具有不同晶向之硅层上之MOSFET之改良的高速半导体装置。本发明复以SOI技术之减少的寄生结电容优点提供通过形成于具有(110)/<110>晶向之硅层上之PMOSFET所提供的更高空穴迁移率。
为了使从在(110)面上制造装置获得之完全效能最佳化，必须定向所有PMOSFET栅极以使空穴可在(110)/<110>方向流动。在习知电路布局中制造MOSFET栅极电极以致许多栅极与其它栅极成直角。
根据本发明某些实施例，多堆栈混合定向(hybrid orientation)层提供多个硅层，该等硅层具有形成于一般SOI结构上之基本上相互垂直定向之(110)面。因此，可制造多个PMOSFET，栅极基本上相互垂直。通过适当选择该硅层晶向在所有PMOSFET内之空穴可在高迁移率(110)/<110>方向流动。
本发明将配合以下图式说明之该半导体装置之形成而叙述。然而，此仅为范例，因所请求之发明不限定于图式所示之特定装置之形成。
将叙述利用Smart Cut技术而在SOI衬底上形成半导体装置之方法。然而，根据本发明之替代实施例可利用形成SOI结构之替代技术，例如SIMOX。如图1所示，通过提供例如硅晶圆12之单晶硅(monocrystalline silicon)衬底12而形成上部分17。硅晶圆12包括具有晶向和晶面之硅。在本发明之某些实施例中，硅晶圆12具有<110>晶向和(110)面。绝缘层14形成于该硅晶圆12上。在本发明之某些实施例中，该绝缘层14为氧化硅层。根据本发明之某些实施例，可通过例如硅晶圆12之热氧化等之习知方法而形成该氧化硅层14。如图2所示，将氢离子15注入硅晶圆12至预定深度16以形成上部分17。该值入的氢离子产生微腔(microcavities)、微丘(microblisters)或微泡(microbubbles)在该注入的晶圆内。当微腔密度和尺寸降低该腔距离于某阈值下，腔间(intercavity)破裂会发生且经由渗漏类型(percolation type)过程而传播。此最后导致晶圆12之分裂，如以下所述。
提供包括诸如硅晶圆18之硅衬底18之下部分23以键合于该上部分17。下部分硅晶圆18具有不同于上部分硅晶圆12晶向之晶向。在本发明之某些实施例中，下部分硅晶圆18具有<100>晶向。
如图3所示，上部分17和下部分23经由绝缘层表面13和下部分23之表面层21而键合在一起。在某些实施例中，研磨上部分17和下部分23之键合表面13、21至低表面粗糙度，例如2μm2 RMS。下部分23和上部分17在钝气环境(inert atmosphere)及温度范围从约900℃至约1200℃中压在一起及加热约5分钟至约5小时以熔接下部分23和上部分17。
在本发明之某些实施例中，提供例如H2O2或HNO3之水溶液和H2O2之滴剂之氧化剂于上部分17和下部分23间之接口。该氧化剂通过以下方式而改良键合过程：允许相对较低温度的键合；通过提供掺杂物于键合液体中而提供更好的压力补偿，该键合液体将产生结合层，而该结合层具有与衬底晶圆非常相近的热膨胀系数；以及通过使用将提供为流动污染物扩散的阻障的键合层的键合液体中的掺杂物而限制污染物移动。
结合的上及下部分17、23接着在约1100℃进行退火约2小时。该退火步骤造成在氢掺杂的上部分17中之微腔传播，而造成晶圆12沿缺陷线16分裂。然后去除该上部分衬底12之块状硅部分而留下附着硅层19。因此，得到SOI结构27，如图4所示。在本发明之某些实施例中，因为该分裂硅层19呈现微粗糙度，故在形成SOI结构27后研磨该结构27。
额外的SOI硅层25形成于SOI结构27上以形成包括多堆栈混合定向层之半导体装置。此可通过重复Smart Cut过程而完成，如先前所述。为了额外的SOI硅层25之形成，该SOI结构27变成下部分29，如图4所示。如图5所示，包括绝缘层24(例如氧化硅层24)以及硅衬底20之上部分31系键合至下部分29。如先前所述，通过注入氢离子至硅衬底20而形成缺陷线22。上部分31之硅衬底20包括具有与硅层19相同晶向之硅。然而，上部分31位于下部分29上，以致硅衬底20之硅面定向为基本上垂直于硅层19之硅面。在本发明之某些实施例中，下部分29之硅层19以及上部分31之硅衬底20皆包括具有<110>晶向之单晶硅。在本发明之某些其它实施例中，可使用具有其它晶向的硅。
接着键合上部分31和下部分19，该上晶圆20沿缺陷线22分裂并移除，如上所述，导致SOI结构27，其包括：具有第一晶向之衬底18、位于该衬底18上之第一绝缘层14、包括具有第二晶向和晶面之硅之第一硅层19、第二绝缘层24、以及包括具有该第二晶向和基本上与该第一硅层19之晶面垂直之晶面之第二硅层25，如图6所示。在本发明之某些实施例中，第一和第二硅层19、25形成至厚度为约30奈米(nm)至约100奈米。
如图7所示，形成氧化硅层26于第二硅层25上。可例如通过化学气相沉积(CVD)而沉积氧化硅层26，或可热氧化硅层25之上表面。接着沉积氮化硅膜28(下文中亦称氮化硅层28)于氧化硅层26上。在本发明之某些实施例中，氧化硅层26之厚度范围为从约5奈米至约100奈米。在本发明之某些实施例中，氧化硅层26约20奈米厚。氮化硅层28厚度为约50奈米至约300奈米。在本发明之某些实施例中，氮化硅层28厚度为约100奈米。
接着形成开口30、32于SOI结构27中，如图8所示。在本发明之某些实施例中，以习知光刻和蚀刻技术形成开口30、32以暴露衬底18之上表面34及第一硅层19之上表面36。习知光刻和蚀刻技术包含：形成阻层于SOI结构27上、遮蔽(masking)及图案化该阻层、非等向性蚀刻(anisotropic etch)该SOI结构27以移除部分之氮化硅层28、氧化硅层26、第二硅层25、以及第二绝缘层24，而暴露第一硅层19之上表面36。继续蚀刻以移除部分之第一硅层19及第一绝缘层14以在开口30中暴露衬底18之上表面34。接着剥除(strip)光刻胶以提供如图8所示之SOI结构27。习知非等向性蚀刻技术包含电浆蚀刻(plasmaetching)及反应性离子蚀刻(reactive ion etching)。非等向性蚀刻可利用连续的利用理想地蚀刻各种不同层之已知电浆蚀刻步骤而替代实行。因为形成不同深度的二开口30、32，可使用分别的光刻及蚀刻步骤以形成各开口30、32。替代性地，二开口皆可利用梯度(gradient)光刻技术而同时形成。
第二氮化硅层38接着沉积于SOI结构27上，如图9所示。在本发明之某些实施例中，通过例如CVD等之习知沉积技术而沉积氮化硅层38至厚度为从约10奈米至约100奈米。接着在开口30、32中非等向性蚀刻氮化硅层38以形成自我对准侧壁间隔件(self-aligned sidewallspacer)38，如图10所示。在本发明之某些实施例中，自我对准间隔件38可包括其它绝缘材料。例如，自我对准氧化物间隔件38可通过非等向性蚀刻沉积的氧化硅层而形成。
成长选择性外延(epitaxial)硅层40、42于硅衬底18和第一硅层19上，以使外延硅层40、42延伸到各别的开口30、32的顶部上，如图11所示。外延硅层40、42具有如其各别的下方底部硅层18、19相同的晶向。因此，外延硅层40具有与硅衬底18相同的晶向，而外延硅层42具有与第一硅层19相同的晶向。
成长选择性外延硅之后，利用习知的化学机械研磨(chemical-mechanical polishing，简称CMP)技术以研磨外延硅层40、42以使其基本上与第二氮化硅层28之上表面43共平面，如图12所示。
三个绝缘区域，第一区域52、第二区域54、以及第三区域56，形成于SOI结构27中并通过习知的浅沟隔离(shallow trench isolation，简称STI)技术而彼此隔离。如图13所示，于SOI结构27中形成沟(trenches)44以暴露第一绝缘层14之表面46。通过习知光刻和蚀刻技术而形成沟44，其包括在SOI结构27上沉积光刻胶、选择性曝光及图案化光刻胶、非等向性蚀刻、以及移除剩下的光刻胶以形成沟44，如图13所示。沟44位于氮化物侧壁38周围，以使当进行非等向性蚀刻时，从结构27移除氮化物侧壁38。
如图14所示，沟44接着通过习知CVD制程以适合的绝缘材料48填充。适合的绝缘材料48包括氮化硅及氧化硅。在本发明之某些实施例中，沟区域44以氧化硅48填充以绝缘第一区域52、第二区域54、以及第三区域56。一些习知以氧化硅填充沟区域44之方法包含：
(a)四乙氧基硅(tetraethylorthosilicate)低压化学气相沉积(TEOSLPCVD)，
(b)非表面敏感TEOS臭氧大气压(non-surface sensitive TEOSozone atmosphere)或次大气压(sub-atmospheric pressure)化学气相沉积(APCVD或SACVD)，以及
(c)硅烷氧化高密度电浆CVD。
以氧化硅48填充沟44前，热氧化物衬料(liners)(图中未显示)系照惯例沿沟44之壁49成长，例如通过在温度约950℃至约1100℃暴露结构27于氧气环境。接着通过CMP平坦化结构27以移除延伸在沟44上之氧化硅48。平坦化之后，接着移除氮化硅层28及氧化硅层26，如图15所示，以暴露第二硅层25之上表面50。典型通过湿式蚀刻移除氮化硅层28及氧化硅层26。习知利用热磷酸蚀刻氮化硅以及利用氢氟酸或氢氟酸和氟化铵的混合物(缓冲氧化物蚀刻)移除氧化硅。于所得之结构27中，第二区域54之第一硅层42与第三区域56之第二硅层25和第一区域52之第三硅层40绝缘。第一区域52之第三硅层40亦与第三区域56之第二硅层25绝缘。
如图16所示，形成NMOSFET 58于第一区域52中，形成PMOSFET60于第二区域54中，以及形成PMOSFET 62于SOI结构27之第三区域56中。该形成于第三区域56之第二硅层25之PMOSFET 62定向为基本上与形成于第二区域54之第一硅层42之PMOSFET 60垂直。
形成栅极氧化物层64及栅极电极层66于结构27上。在本发明之某些实施例中，栅极电极层66包括多晶硅(polysilicon)且形成至厚度约100奈米至约300奈米。栅极氧化物层64典型形成至厚度约10埃()至约100埃。通过习知的光刻和蚀刻技术图案化栅极氧化物层64及栅极电极层66。
通过习知的离子注入技术形成源极和漏极延伸区70。注入至源极和漏极延伸区70之掺杂物种类视该装置为NMOSFET或PMOSFET而定。例如，若晶体管为NMOSFET，则将N型掺杂物注入至源极和漏极延伸区70。在本发明之某些实施例中，例如砷之N型掺杂物以注入量约1×1014离子/平方公分(ions/cm2)至约2×1015离子/平方公分以及注入能量约1千电子伏特(keV)至约5千电子伏特注入至源极和漏极延伸区70。若晶体管为PMOSFET，则将P型掺杂物注入至源极和漏极延伸区70。在本发明之某些实施例中，例如二氟化硼(BF2)之P型掺杂物以注入量约1×1014离子/平方公分至约2×1015离子/平方公分以及注入能量约0.5千电子伏特至约5千电子伏特注入至源极和漏极延伸区70。
视需要形成环形注入物(halo implants)72于沟道区域74中，接近MOSFET 58、60、62之漏极和源极区域68。以与漏极和源极区域68之导电型式(conductivity type)相反之掺杂物形成环形注入物72。在本发明之某些实施例中，可以角度注入(angled implant)形成环形注入物72。在本发明之某些实施例中，环形注入物72可以注入量约8×1012离子/平方公分至约2×1014离子/公分平方以及注入能量约7千电子伏特至约50千电子伏特注入。环形注入物72避免在沟道区域74中源极和汲汲区域之合并。此外，可通过调整环形剂量(halo dose)而修改MOSFET 58、60、62的阈值电压。
接着形成源极和漏极区域68之重浓度掺杂(heavily doped)部分78(下文中亦称重浓度掺杂区域78)。如图17所示，通过习知方法在栅极电极66周围形成侧壁间隔件76，例如沉积绝缘材料层例如氮化硅或氧化硅，接着通过非等向性蚀刻以形成侧壁间隔件76。在本发明之某实施例中，若晶体管为NMOSFET，则以注入量约1×1015离子/平方公分至约4×1015离子/平方公分以及注入能量约20千电子伏特至约50千电子伏特注入砷至重浓度掺杂区域78。在本发明之某些实施例中，若晶体管为PMOSFET，则以注入量约1×1015离子/平方公分至约4×1015离子/平方公分以及注入能量约2千电子伏特至约10千电子伏特注入硼至重浓度掺杂区域78。
由于在具有<110>晶向之硅上制造PMOSFET可大幅提升PMOSFET之效能，包括<110>晶向硅之硅层以P型掺杂物掺杂于漏极和源极区域68。包括<100>晶向硅之硅层以N型掺杂物掺杂于漏极和源极区域68以形成NMOSFET。
接着沉积金属层于SOI结构27上。加热SOI结构27使金属层与下面的源极和漏极区域68及栅极电极66中之硅反应而形成在源极和漏极区域68中及栅极电极66上之金属硅化物结80，如图18所示。
在本发明之某些实施例中，SOI结构91形成有绝缘BOX层84，以使第一区域86中之第三硅层40、第二区域88中之第一硅层42、以及第三区域90中之第二硅层25各为SOI硅层，如图19所示。通过SIMOX制程而形成BOX层84。在SIMOX制程中，注入氧离子82至SOI结构91。在本发明之某些实施例中，以能量范围为从约70千电子伏特至约200千电子伏特以及剂量范围为从约1.0×1017离子/平方公分至约1.0×1018离子/平方公分注入氧离子82至SOI结构91。离子注入后，在温度范围从约1250℃至约1400℃中退火SOI结构91约4至约6小时。如图20所示，接着形成多个MOSFET 92、94、96于第一区域86、第二区域88、以及第三区域90，如上所述。
在本发明之替代实施例中，BOX层84未延伸至第三区域90下。在第一区域86和第二区域88注入氧离子82期间，可利用习知的沉积、光刻、以及蚀刻技术形成硬质氧化物掩膜(hard oxide mask)于第二区域90上以保护第三区域90不受损害。
本发明之实施例提供结合SOI技术之效能改良以及最佳硅晶向之改良的半导体装置。根据本发明之实施例制造之半导体装置以增加空穴迁移率且保持高电子迁移率为特色。此外，配置根据本发明之实施例之半导体装置以在该装置之共享面上之基本上相互垂直定向之多个PMOSFETs中保持高空穴迁移率。
以实例揭露所叙述之实施例只用以作为说明之目的。而非解释为限制申请专利范围。如熟习此技艺者所知，实例揭露涵盖范围广泛不特定于本文所述之实施例。

Claims (10)

1.一种半导体装置，包括：
具有第一晶向的衬底(18)；
位于该衬底(18)上的第一绝缘层(14)；以及
位于该第一绝缘层(14)上的多个硅层，其中，第一硅层(42)包含具有第二晶向和一晶面的硅，以及第二硅层(25)包含具有该第二晶向及基本上与该第一硅层(42)的晶面垂直的晶面的硅。
2.如权利要求1所述的半导体装置，其中，该第一硅层(42)和第二硅层(25)由绝缘区域(48)所隔开。
3.如权利要求1所述的半导体装置，还包括位于该衬底(18)上的第三硅层(40)。
4.如权利要求3所述的半导体装置，其中，该第三硅层(40)通过绝缘区域(48)而与该第一硅层(42)和第二硅层(25)隔开。
5.如权利要求4所述的半导体装置，其中，MOSFET(60，62，58)形成在该第一硅层(42)、第二硅层(25)及第三硅层(40)的各层。
6.一种形成半导体装置的方法，包括下列步骤：
提供绝缘体上硅结构，该绝缘体上硅结构包括第一绝缘层(14)形成于其上的、具有第一晶向的第一硅衬底(18)，以及具有第二晶向和位于该第一绝缘层(14)上的晶面的第一硅层(19)；
提供具有该第二晶向和一晶面的第二硅衬底(20)以及形成在该第二衬底上的第二绝缘层(24)，其中，该第二硅衬底(20)包括通过注入氢离子至该第二硅衬底(20)中所产生的缺陷线(22)；
经由该第二绝缘层(24)和该第一硅层(19)而键合该第二硅衬底(20)至该绝缘体上硅结构，以使该第二硅衬底(20)的晶面定向为基本上与该第一硅层(19)的晶面垂直；以及
沿该缺陷线(22)分裂及移除该第二硅衬底(20)而在该绝缘体上硅结构上留下该第二绝缘层(24)及第二硅层(25)。
7.如权利要求6所述的形成半导体装置的方法，还包括移除部分的该第二硅层(25)、第二绝缘层(24)、第一硅层(19)及第一绝缘层(14)以在该绝缘体上硅结构的第一区域中形成第一开口(30)，暴露该第一硅衬底(18)的一部分(34)；以及
移除部分的该第二硅层(25)和第二绝缘层(24)以在该绝缘体上硅结构的第二区域中形成第二开口(32)，暴露该第一硅层(19)的一部分(36)。
8.如权利要求7所述的形成半导体装置的方法，还包括在该第一开口(30)和该第二开口(32)的侧壁上形成侧壁间隔件(38)；以及
在该第一开口(30)和第二开口(32)中生长外延硅以提供绝缘体上硅结构，其具有在该绝缘体上硅结构的该第一区域(52)中具有该第一晶向的第三硅层(40)、在该绝缘体上硅结构的该第二区域(54)中具有该第二晶向与一晶面的第一硅层(19，42)、以及在该绝缘体上硅结构的第三区域(56)中具有该第二晶向以及基本上与该第一硅层(19，42)的晶面垂直的晶面的第二硅层(25)。
9.如权利要求8所述的形成半导体装置的方法，还包括在该绝缘体上硅结构中形成多个绝缘区域(48)以使该第一区域(52)与该第二区域(54)和第三区域(56)绝缘，以及使该第二区域(54)与该第三区域(56)绝缘。
10.如权利要求20所述的形成半导体装置的方法，还包括在该绝缘体上硅结构的该第一区域(52)、第二区域(54)及第三区域(56)中形成MOSFET(58，60，62)。
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