TWI380442B - Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers - Google Patents

Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers Download PDF

Info

Publication number
TWI380442B
TWI380442B TW094141672A TW94141672A TWI380442B TW I380442 B TWI380442 B TW I380442B TW 094141672 A TW094141672 A TW 094141672A TW 94141672 A TW94141672 A TW 94141672A TW I380442 B TWI380442 B TW I380442B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor device
insulating layer
germanium
forming
Prior art date
Application number
TW094141672A
Other languages
English (en)
Other versions
TW200625635A (en
Inventor
Andrew Michael Waite
Jon D Cheek
Original Assignee
Globalfoundries Us Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Us Inc filed Critical Globalfoundries Us Inc
Publication of TW200625635A publication Critical patent/TW200625635A/zh
Application granted granted Critical
Publication of TWI380442B publication Critical patent/TWI380442B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Description

1380442 九、發明說明： “ 【發明所屬之技術領域】 本發明係關於半導體裝置以及製造半導體裝置之方 法，更詳而言之’係關於包括絕緣層上覆矽（silicon_〇n_ insulator ’簡稱SOI)技術之改良半導體裝置。 【先前技術】 在半導體產業中持續研發之重要目標為在增加半導體 效能的同時減少半導體裝置之功率消耗。諸如金屬氧化物 •半導體場效電晶體（MOSFETs)之平面型電晶體（planar transistor)特別適合用於高密度積體電路。當M〇SFETs -以及其他裝置之尺寸減小時，該裝置之源極/汲極區域、通 .道（channel)區域、以及閘極電極之大小亦減小。 具有短通道長度之持續更小的平面型電晶體之設計需 要&供非常淺的源極/沒極接點（junct i〇ns)。淺接點需要 避免植入的摻雜物侧向擴散至通道内，因為此種擴散不利 _地造成漏電流（leakage current)以及不佳的擊穿 (breakdown)效能❶通常在短通道裝置中可接受的效能需要 深度為1 000埃（A )等級或更小之淺源極/汲極。 絕緣層上覆矽（SOI)技術允許形成高速、淺接點裝置。 此外，SOI裝置藉由減少寄生接點電容（parasitic junction capacitance)而改進效能。 在SOI基材中，由氧化矽製成之埋設氧化物（buried 〇xide)(B0X)膜係形成於單晶矽上，而單晶矽薄膜係形成於 其上各種製造此種SOI基材之方法為已知的。其甲一種 93305 6 1380442 4^M^^^^(Separati〇n_byimpianted 〇，：en)(s刪)之方法，其中 其 形成埋設氧化物（臟）膜。 m w基心 另一種形成S〇I基材之方法為晶圓接合（㈤打 同0將具有氧切表面層之兩個半導體基材共 二間 乳化石夕表面以形成B〇X層於該等兩個半導體基 另-種SOI技術為SmartCut®，其亦有關經由氧化物 曰而接合半導體基材。在Smartcut@方法中，在接合前以 ㈣子植人其t-財導縣材。錢料植人接著使經 氫離子植入之基材自接合的基材中分離，而留下石夕薄層在 表面上。 θ 可藉由選擇具有某晶面定向（crystal plane orientations)之矽層而進一步提升半導體裝置效能，該晶 面疋向有利於電洞或電子流動。例如，若將p型m〇sfeTs 籲（PMOSFETs)製造於（11 〇 )矽表面上，且將閘極定向使電洞於 (ιιο)/<ιιο>的方向流動，則可改良PM0SFETs的效能。在 (ιιο)/<ιιο>方向流動的電洞的遷移率（mobility)比在習 知（100)/<11〇>方向流動的電洞的遷移率的兩倍還高。不幸 地，在（no)表面上以對（110)/<110>方向之成直角（right angles)移動之電洞在（11〇)/<100>方向流動。在（11〇)/ <100〉方向的電洞的遷移率只有在（110)/<110>方向流動的 電洞的遷移率的2/3。此外，在（11 〇)面的電子遷移率比在 習知（100)面的電子遷移率低很多。 93305 7 1380442 —此處所應用之術語「半導體裝置」不限於特定揭露之 實施例在匕處所應用之半導體裝置包含種類廣泛的電子褒 置’其包含覆晶⑴ip chips)、覆晶/封裝組合（package assemblies)电日日體、電容器、微處理器、隨機存取記憶 體等通吊’半導體襄置係指任何包括半導體之電子裳置。 【發明内容】 在半導體裝置技藝中存在結合SOI技術之效能改良以 及理想石夕晶向（crystal orientation)之需求。在此技藝中 進一步存在包括MOSFETs之半導體裝置之需求，其中 PMOSFETs和_SFETs分別製造於對於電洞（hQle)和電子 -遷移率而言為理想的石夕表面上。在此技藝中亦存在形成包 括SOI技術及理想石夕晶向之半導體裝置之方法之需求。此 外，在此技藝中存在形成包括M〇SFETs之半導體裝置之方 法之需求’其中P贿ETs和腦SFETs製造於對於電洞和 電子遷移率而言為理想的矽表面上。 ❿ 本發明之實施例符合這些及其他需求，其係提供包括 具有第一晶向之基材之半導體裝置。第一絕緣層應在該基 材上，且複數個矽層位在該第一絕緣層上。第一矽層包括 具有第二晶向和晶面之石夕。第二石夕層包括具有該第二晶向 及大體與第一矽層之晶面垂直之晶面之矽。 …本發明之實施例復符合這些及其他需求，其提供形成 半導體褒置之方法，包括：設置絕緣層上覆石夕結構，該絕 緣層上覆矽結構包括有第一絕緣層形成於其上之具有第一 晶向之第一矽基材，以及位於第一絕緣層上之具有第二晶 93305 8 1380442 向和晶面之第一矽層。提供第二矽基材，其具有該第二晶 向及晶面以及形成於該第二基材上之第二絕緣層。第二矽 基材包括藉由植入氫離子至該第二矽基材所產生之缺陷線 (a line of defects)。經由該第二絕緣層及該第一矽層而 接合該第二矽基材至該絕緣層上覆矽結構，以使該第二矽 基材之晶面定向為大體垂直於該第一矽層之晶面。該第二 矽基材沿缺陷線分裂和移除，而留下該第二絕緣層及第二 矽層於該絕緣層上覆矽結構上。 本發明滿足具有改良電子特性之改良高速半導體裝置 之需求。 本發明之上述及其他特點、方面、以及優點將在以下 本發明之詳細說明配合所附圖式而更為清楚。 【實施方式】 本發明能夠製造具有s〇i技術之優點以及形成於一般 矽基材上具有不同晶向之矽層上之M0SFET之改良的高速 半導體裝置。本發明復以S〇 I技術之減少的寄生接點電容 優點提供藉由形成於具有（110)/<110>晶向之矽層上之 PM0SFET所提供之更高電洞遷移率。 為了使從在（11 〇 )面上製造裝置獲得之完全效能最佳 化’必須定向所有PM0SFET閘極以使電洞可在（11〇)/<11〇> 方向流動。在習知電路佈局中製造M0SFET閘極電極以致許 多閘極與其他閘極成直角。 根據本發明某些實施例，多堆疊混合定向（hybrid oirientation)層提供複數個矽層，該等矽層具有形成於一 9 93305 1380442 曝光及圖案化光阻、非等向性蝕刻、以及移除剩下的光阻 以形成溝44，如第13圖所示。溝44位於氮化物側壁38 周圍’以使當進行非等向性蝕刻時，從結構27移除氮化物 側壁38。 如第14圖所示，溝44接著藉由習知CVD製程以適合 的絕緣材料48填充。適合的絕緣材料48包括氮化矽及氧 化石夕。在本發明之某些實施例中’溝區域44以氧化矽48 填充以隔離第一區域52、第二區域54、以及第三區域56。 一些習知以氧化矽填充溝區域44之方法包含： (a) 四乙氧基石夕（tetraethylorthosi 1 icate)低壓化 學氣相沉積（TEOS LPCVD)， (b) 非表面敏感TE0S臭氧大氣壓（non-surface sensitive TEOS ozone atmosphere)或次大氣壓 (sub-atmospheric pressure)化學氣相沉積 (APCVD 或 SACVD)，以及 (c) 矽烷氧化高密度電漿CVD。 以氧化石夕48填充溝44前，熱氧化物襯料（1丨ners)(圖 中未顯示）係照慣例沿溝44之壁49成長，例如藉由在溫度 約950t至約ll〇〇t：暴露結構27於氧氣環境。接著藉由又 CMP平坦化結構27以移除延伸在溝〇上之氧化矽4/。平 垣化之後，接著移除氮化矽層28及氧化矽層26，如第15 圓所示，以暴露第二矽層25之上表面5〇。典型藉由渴式 _移除氮化㈣28及氧切層26。習知利用㈣酸二 刻虱化矽以及利用氫氟酸或氫氟酸和氟化銨的混合物（緩 93305 15 1380442 « 衝氧化物蝕刻)移除氧化矽。於所得之結構 層42與第三區域56之第二他二 = 石夕層4°隔離。第—區域52之第三石夕層40 亦/、第二區域56之第二矽層25隔離。 如第16圖所示，形成NM〇SFET58於第—區域μ ::〇ΓΓ:ΕΤ60於第二區域54中，以及形成PM0SFET62 構27之第三區域56中。該形成於第三區域56 =二石夕層25之PM贿62定向為大體與形成於第二區 域54之第一矽層42之PMOSFET 60垂直。 形成閘極氡化物層64及閘極電極層66於結構π上。 在本發明之某些實施例中，閘極電極層 山咖）且形成至厚度約⑽奈米至約_奈米。間 ，氧化物層64典型形成至厚度約1()埃⑷至約彻埃。 错由習知的微影和飯刻技術圖案化閘極氧化物層64及閉 極電極層6 6。 藉由習知的離子植入技術形成源極和沒極延伸區 7〇。植入至源極和汲極延伸區7G之摻雜物 NM0SFET或PM〇SFET而定。例如，若電曰，Λ裝置為 J 右逼日日體為簡0SFET，則 將N型摻雜物植入至源極和沒極延伸區7〇。在本發明之某 些實施例中，例如砷之Μ摻雜物以植入量約心〇)4離； 二方::分U㈣㈤至約 千電子伏㈣eV)W5千電子伏特植入至源極和 沒極延伸區70。若電晶體為PM0SFET，則將p型摻雜物植 入至源極和沒極延伸區70。在本發明之某些實施例中，例 93305 16 丄細442 如二氟化蝴（BF2)之p型摻雜物以植入量約1χ 1〇14離子/平 ♦刀至約2x 1〇離子/平方公分以及植入能量約〇 5千 a子伏特至約5千電子伏特植人至源極和汲極延伸區。 而要幵v成環形植入物（halo implants)72於通道區 一、4中接近M〇SFET 58 ' 6〇、之汲極和源極區域μ。 :與沒極和源極區域68之導電型式(conductivity type) 令。捧雜物形成環开)植入⑯72。在本發明之某些實施例 • 可以角度植入（angled implant)形成環形植入物72。 本發月之某些實施例中，環形植入物72可以植入量約8 X 1—〇12離子/平方公分至約2χ 10“離子/公分平方以及植入 能量約7千電子伏特至約5()千電子伏特植人。環形植入物 α +避免在通道區域74中源極和汲汲區域之合併。此外， 可藉由调整壤形劑量（hal〇 dose)而修改M0SFET 58、60、 62之臨界電壓。 接著形成源極和汲極區域68之重濃度摻雜（heaviiy d〇Ped_)部，78(下文中亦稱重濃度摻雜區域78)。如第i 7 圖所不’藉由習知方法在閘極電極66周圍形成侧壁間隔件 ^例如沉積絕緣材料層例如氮化發或氧化⑪，接著藉由 性蝕刻以形成側壁間隔件7 6。在本發明之某實“ ，右電晶體為NM0SFET，則以植入量約1χ 1〇丨5離子/平 方公分至約4Χ 1015離子/平方公分以及植人能量約20千電 子伏特至約50千電子伏特植人~至重濃度摻㈣域 在，發明之某些實施例中，若電晶體為pm〇sfet，則以植 入罝約1X 1〇15離子/平方公分至約4x 1〇15離子/平方公分 93305 17 1380442 以及植入能量約2千電子伏特至約1G千電子伏特植入蝴至 '重濃度摻雜區域78。 由於在具有<110〉晶向之矽上製造PM0SFET可大幅提 昇PM0SFET之效能，包括<11〇〉晶向石夕之石夕層以卩型摻雜物 摻雜於汲極和源極區域68。包括<1〇〇>晶向矽之矽層以N 型摻雜物摻雜於汲極和源極區域68以形成nm〇sfet。 接著沉積金屬層於SOI結構27上。加熱S0I結構27 使金屬層與下面的源極和汲極區域68及閘極電極中之 矽反應而形成在源極和汲極區域68中及閘極電極上之 金屬矽化物接點80，如第18圖所示。 在本發明之某些實施例中，S0I結構91形成有絕緣β〇χ 層84,以使第一區域86中之第三矽層4〇、第二區域88 中之第一矽層42、以及第三區域90中之第二矽層25各為 SOI矽層，如第19圖所示。藉由SIM〇x製程而形成Β〇χ層 84。在SIM0X製程中’植入氧離子82至S0I結構91。在 φ本發明之某些實施例中，以能量範圍為從約7〇千電子伏特 至約200千電子伏特以及劑量範圍為從約1〇χ 1〇π離子/ 平方公分至約1. 〇χ 1〇18離子/平方公分植入氧離子82至 SOI結構91。離子植入後，在溫度範圍從約125{rc至約 C中退火SOI結構91約4至約6小時。如第20圖所示， 接著形成複數個M0SFET 92、94、96於第一區域86、第二 區域88、以及第三區域90，如上所述。 在本發明之替代實施例中，BOX層84未延伸至第三區 域90下。在第一區域86和第二區域88植入氧離子82期 93305 18

Claims (1)

  1. 第料141672號專利申請案 101年6月4日修正替換頁 十、申請專利範圍： 丨.一種半導體裝置，包括： 具有第一晶向之基材； 在該基材上之第一絕緣層· ，以及 、卜在第絕緣層上且包含第一石夕層和第二石夕層 ，複數個矽層’其中’該第-矽層包括具有第二晶向和 之矽而該第二矽層包括具有該第二晶向及大體與 h第一矽層之晶面垂直之晶面之矽， ’、 9 1 +八中該第一和第二矽層由絕緣區域所隔開。 .專利範圍第1項之半導體裝置，其中，該第一絕 緣層包括氧化矽。 3.=請專利範圍第Μ之半導體裝置，復包括位於該基 材上之第二發層。 A.=料利範圍第3項之半導體裝置，其中，該第三石夕 θ Μ由絕緣區域而與該第—和第二碎層隔開。 •二申範圍第4項之半導體裝置，復包括插置於該 第—夕層與該基材之間之第二絕緣層。 δ.::::利範圍第5項之半導體裝置，其中，該第二絕 7 復插置於該第二♦層與該第-絕緣層之間。 .緩：：：利範圍第6項之半導體裝置，其中，該第二絕 緣層包括氧化矽。 s 8. 如申請專利範圍第&項之丰遙 形成於該第-、第二及第三石夕層之:二’SFET 9. 如申請專利範圍第4項之半導體裝置，曰其中，該基材和 93305(修正版） 21 1380442 第94141672號專利申請案 兮帑一_ r π L 101年6月4日修正替換頁 孩弟二妙層包括具有<1〇〇>晶向之石夕- 10·:申請專利範圍第9項之半導體裝置，其中，該第一和 第一石夕層包括具有<110〉晶向之矽。 U·:申請專利範圍第6項之半導體裝置，復包括形成於該 第一和第二石夕層之酬SFET以及形成 NMOSFET。 矛一 /層乏 請專利範圍第^之半導體裝置，其中，形成於 ^二石夕層之該·圓^向為大體垂直於形成於該 弟一石夕層之該PMOSFET。 13·—種形成半導體裝置之方法，包括下列步驟： 材，以及位在該第一絕緣層上之具有第 第一矽層 提供絕緣層上覆縣構，該絕緣層上覆㈣構包括 有第一絕緣層形成於其上之具有第—晶向之第一石夕其 晶向和晶面之 提供第二梦基材，該第二石夕基材具有該第二晶向和 晶面以及形成於該第二矽基材上之第二絕緣層，Α中， 該第二石夕基材包括藉由植人氫離子至該第二♦基 產生之缺陷線； 二石夕 晶面 經由該第二絕緣層和該第一矽層而接合該第 基材至該絕緣層上覆矽結構，以使該第二矽基材之 疋向為大體與該第一碎層之晶面垂直； 沿該缺陷線分裂及移除該第二矽基材而留下該第 二絕緣層及第二矽層於該絕緣層上覆矽結構上；χ 移除部分之該第二矽層、第二絕緣層、第一梦層及 93305(修正版) 22 1380442 壤 * . I---- 第94141672號專利申請案 101年6月4日修正替換頁 第一絕緣層以形成第一開口於該絕緣層上覆矽結構之 • 第一區域中而暴露部分之該第一矽基材；以及 於該絕緣層上覆矽結構之第二區域中移除部分之 该第二矽層和第二絕緣層以形成第二開口而暴露部分 之該第一梦層。 14. 如申請專利範圍第13項之形成半導體裝置之方法，復 包括形成側壁間隔件於該第一和第二開口之侧壁上。 15. 如申請專利範圍第U項之形成半導體裝置之方法，復 包括成長磊晶矽在該第一和第二開口中以提供絕緣層 上覆矽結構’其具有在該絕緣層上覆矽結構之該第一區 域中具有該第一晶向之第三矽層、在該絕緣層上覆矽結 構之該第二區域中具有該第二晶向與晶面之第一矽 層、以及在該絕緣層上覆矽結構之第三區域中具有該第 一晶向以及大體與該第一矽層之晶面垂直之晶面之該 第二矽層。 16·如申請專利範圍第15項之形成半導體裝置之方法，復 包括·形成複數個絕緣區域在該絕緣層上覆矽結構中以 使該第-區域與該第二和第三區域絕緣，以及使該第二 區域與該第三區域絕緣。 Π.如申請專㈣16項之形成半導體裝置之方法，其 中該开成該複數個絕緣區域之步驟包括移除該側壁間 隔件。 18.如申請專利範圍第16項之形成半導體裝置之方法，復 包括.形成埋設氧化物層於該絕緣層上覆矽結構之該第 93305(修正版) 23 1380442 秦
    lq」 使該第三@層與該基材絕緣。 tr專圍第18項之形成半導體裝置之方法，復 ^括^成該埋設氧化物層於該絕緣層上詩結構之該 弟—Εΐ域中β 2〇·如申請專利範圍第18項之形成半導體裝置之方法，復 包括形成MOSFET於該絕緣層上覆石夕結構之該第一、第 一及第三區域中。 21·如申請專利範圍第16項之形成半導體裝置之方法，其 中該第一石夕層具有<1〇〇>晶向而該第一和第二石夕層具 有〈110>晶向。 22.如申請專利範圍第21項之形成半導體裝置之方法，復 包括形成NMOSFET於該第三矽層以及形成PM〇SFET於該 第一和第二石夕層。 23·如申請專利範圍第丨5項之形成半導體裝置之方法，其 中’該沉積的矽層係藉由選擇性磊晶沉積而沉積。 93305(修正版) 24 14 14 1380442 ^ 鵪 外年//月2?日修正替換I
    12
    第2圖
    17<
    第3圖 (Amended) 齊
TW094141672A 2004-12-08 2005-11-28 Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers TWI380442B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/006,747 US7422956B2 (en) 2004-12-08 2004-12-08 Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers

Publications (2)

Publication Number Publication Date
TW200625635A TW200625635A (en) 2006-07-16
TWI380442B true TWI380442B (en) 2012-12-21

Family

ID=36573248

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094141672A TWI380442B (en) 2004-12-08 2005-11-28 Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers

Country Status (8)

Country Link
US (1) US7422956B2 (zh)
JP (1) JP2008523620A (zh)
KR (1) KR101175342B1 (zh)
CN (1) CN100578751C (zh)
DE (1) DE112005003123B4 (zh)
GB (1) GB2434034B (zh)
TW (1) TWI380442B (zh)
WO (1) WO2006062796A2 (zh)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100843717B1 (ko) * 2007-06-28 2008-07-04 삼성전자주식회사 플로팅 바디 소자 및 벌크 바디 소자를 갖는 반도체소자 및그 제조방법
KR100555569B1 (ko) 2004-08-06 2006-03-03 삼성전자주식회사 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법
US6972478B1 (en) * 2005-03-07 2005-12-06 Advanced Micro Devices, Inc. Integrated circuit and method for its manufacture
US7556989B2 (en) * 2005-03-22 2009-07-07 Samsung Electronics Co., Ltd. Semiconductor device having fuse pattern and methods of fabricating the same
US7473985B2 (en) * 2005-06-16 2009-01-06 International Business Machines Corporation Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
US7696574B2 (en) * 2005-10-26 2010-04-13 International Business Machines Corporation Semiconductor substrate with multiple crystallographic orientations
US7361968B2 (en) * 2006-03-23 2008-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for integrally forming an electrical fuse device and a MOS transistor
US20080124847A1 (en) * 2006-08-04 2008-05-29 Toshiba America Electronic Components, Inc. Reducing Crystal Defects from Hybrid Orientation Technology During Semiconductor Manufacture
US7808082B2 (en) * 2006-11-14 2010-10-05 International Business Machines Corporation Structure and method for dual surface orientations for CMOS transistors
US20080169535A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Sub-lithographic faceting for mosfet performance enhancement
US7728364B2 (en) * 2007-01-19 2010-06-01 International Business Machines Corporation Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation
JP2008235477A (ja) * 2007-03-19 2008-10-02 Oki Electric Ind Co Ltd フォトダイオードおよびそれを用いたフォトｉｃ
JP5286701B2 (ja) * 2007-06-27 2013-09-11 ソニー株式会社 半導体装置および半導体装置の製造方法
FR2929444B1 (fr) * 2008-03-31 2010-08-20 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique du type a semi-conducteur sur isolant et a motifs differencies, et structure ainsi obtenue.
JP2010067930A (ja) * 2008-09-12 2010-03-25 Toshiba Corp 半導体装置およびその製造方法
FR2938117B1 (fr) * 2008-10-31 2011-04-15 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree
FR2942073B1 (fr) * 2009-02-10 2011-04-29 Soitec Silicon On Insulator Procede de realisation d'une couche de cavites
CN102034706B (zh) * 2009-09-29 2012-03-21 上海华虹Nec电子有限公司 控制硅锗合金刻面生长效果的方法
CN101707187B (zh) * 2009-11-27 2012-02-01 上海新傲科技股份有限公司 一种带有绝缘埋层的晶圆的表面处理方法
US8946046B1 (en) 2012-05-02 2015-02-03 Crossbar, Inc. Guided path for forming a conductive filament in RRAM
US8884261B2 (en) 2010-08-23 2014-11-11 Crossbar, Inc. Device switching using layered device structure
US8569172B1 (en) 2012-08-14 2013-10-29 Crossbar, Inc. Noble metal/non-noble metal electrode for RRAM applications
US8946669B1 (en) 2012-04-05 2015-02-03 Crossbar, Inc. Resistive memory device and fabrication methods
US9627443B2 (en) 2011-06-30 2017-04-18 Crossbar, Inc. Three-dimensional oblique two-terminal memory with enhanced electric field
FR2984598A1 (fr) * 2011-12-19 2013-06-21 Soitec Silicon On Insulator Structure substrat sur isolant comprenant une structure electriquement isolante et procede associe
US9559160B2 (en) * 2011-12-23 2017-01-31 Intel Corporation Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition
US20130175618A1 (en) 2012-01-05 2013-07-11 International Business Machines Corporation Finfet device
US9685608B2 (en) 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US9741765B1 (en) 2012-08-14 2017-08-22 Crossbar, Inc. Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
US9396931B2 (en) * 2013-08-01 2016-07-19 Qualcomm Incorporated Method of forming fins from different materials on a substrate
KR102210325B1 (ko) 2013-09-06 2021-02-01 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조 방법
CN105745737B (zh) * 2013-12-18 2020-07-07 英特尔公司 平面异质器件
US10290801B2 (en) 2014-02-07 2019-05-14 Crossbar, Inc. Scalable silicon based resistive memory device
CN106653676B (zh) * 2015-11-03 2019-12-24 中芯国际集成电路制造(上海)有限公司 衬底结构、半导体器件以及制造方法
CN107170750B (zh) * 2017-05-08 2019-08-02 合肥市华达半导体有限公司 一种半导体元器件结构及其制作方法
FI128442B (en) * 2017-06-21 2020-05-15 Turun Yliopisto Silicon structure with crystalline silica
US10192779B1 (en) 2018-03-26 2019-01-29 Globalfoundries Inc. Bulk substrates with a self-aligned buried polycrystalline layer
US11500157B1 (en) * 2019-03-22 2022-11-15 Ciena Corporation Silicon Selective Epitaxial Growth (SEG) applied to a Silicon on Insulator (SOI) wafer to provide a region of customized thickness
US12074024B2 (en) 2021-12-29 2024-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
EP0419767B1 (de) 1989-09-29 1993-11-24 Siemens Aktiengesellschaft Verfahren zur Herstellung eines Körpers aus Silizium
JPH03285351A (ja) * 1990-04-02 1991-12-16 Oki Electric Ind Co Ltd Ｃｍｉｓ型半導体装置およびその製造方法
JPH04372166A (ja) * 1991-06-21 1992-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH0590117A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
EP1179842A3 (en) 1992-01-31 2002-09-04 Canon Kabushiki Kaisha Semiconductor substrate and method for preparing same
US5894152A (en) * 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20040175901A1 (en) * 1999-02-10 2004-09-09 Commissariat A L'energie Atomique Method for forming an optical silicon layer on a support and use of said method in the production of optical components
US6633066B1 (en) * 2000-01-07 2003-10-14 Samsung Electronics Co., Ltd. CMOS integrated circuit devices and substrates having unstrained silicon active layers
JP2002134374A (ja) * 2000-10-25 2002-05-10 Mitsubishi Electric Corp 半導体ウェハ、その製造方法およびその製造装置
FR2819099B1 (fr) 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
JP4304879B2 (ja) * 2001-04-06 2009-07-29 信越半導体株式会社 水素イオンまたは希ガスイオンの注入量の決定方法
US7153757B2 (en) * 2002-08-29 2006-12-26 Analog Devices, Inc. Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure
JP4294935B2 (ja) * 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
JP4117261B2 (ja) * 2003-05-28 2008-07-16 三菱電機株式会社 デマンド監視方式及び装置
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US6815278B1 (en) * 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
JP4419147B2 (ja) * 2003-09-08 2010-02-24 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
JP5113999B2 (ja) * 2004-09-28 2013-01-09 シャープ株式会社 水素イオン注入剥離方法
US7102166B1 (en) * 2005-04-21 2006-09-05 International Business Machines Corporation Hybrid orientation field effect transistors (FETs)

Also Published As

Publication number Publication date
KR101175342B1 (ko) 2012-08-21
US20060118918A1 (en) 2006-06-08
CN101065840A (zh) 2007-10-31
WO2006062796A2 (en) 2006-06-15
GB2434034B (en) 2010-02-17
CN100578751C (zh) 2010-01-06
DE112005003123B4 (de) 2011-11-10
TW200625635A (en) 2006-07-16
KR20070086303A (ko) 2007-08-27
DE112005003123T5 (de) 2008-04-17
GB2434034A (en) 2007-07-11
WO2006062796A3 (en) 2006-08-03
GB0707665D0 (en) 2007-05-30
JP2008523620A (ja) 2008-07-03
US7422956B2 (en) 2008-09-09

Similar Documents

Publication Publication Date Title
TWI380442B (en) Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
KR101124657B1 (ko) 서로 다른 결정 방향을 갖는 실리콘층을 구비한실리콘-온-절연막 반도체 소자 및 실리콘-온-절연막 반도체소자를 형성하는 방법
US9450097B2 (en) Methods for doping Fin field-effect transistors and Fin field-effect transistor
KR100781580B1 (ko) 이중 구조 핀 전계 효과 트랜지스터 및 그 제조 방법
US6372559B1 (en) Method for self-aligned vertical double-gate MOSFET
US6432754B1 (en) Double SOI device with recess etch and epitaxy
TWI390666B (zh) 絕緣體上半導體裝置之製造方法
US8084305B2 (en) Isolation spacer for thin SOI devices
US10411112B2 (en) Semiconductor device with silicon layer containing carbon
US20050260818A1 (en) Semiconductor device and method for fabricating the same
TW201011910A (en) Poly-emitter type bipolar junction transistor, bipolar CMOS DMOS device, and manufacturing methods of poly-emitter type bipolar junction transistor and bipolar COMS DMOS device
US7648880B2 (en) Nitride-encapsulated FET (NNCFET)
TW469648B (en) Semiconductor device and its manufacture method
US6737315B2 (en) Method of manufacturing semiconductor device including steps of forming both insulating film and epitaxial semiconductor on substrate
JP2008288364A (ja) 半導体装置および半導体装置の製造方法
US6657261B2 (en) Ground-plane device with back oxide topography
JP2009267027A (ja) 半導体装置及びその製造方法
JPH0738095A (ja) 半導体装置及びその製造方法
JP2000357792A (ja) 半導体装置の製造方法
TW587283B (en) Method for forming source and drain of transistor
JP2001257346A (ja) 半導体集積回路装置
JP2004063746A (ja) 半導体装置及びその製造方法
TW200306621A (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees