JP2008523620A - 複数のスタックしたハイブリッド方位層を含む半導体装置および半導体装置の形成方法 - Google Patents
複数のスタックしたハイブリッド方位層を含む半導体装置および半導体装置の形成方法 Download PDFInfo
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- JP2008523620A JP2008523620A JP2007545518A JP2007545518A JP2008523620A JP 2008523620 A JP2008523620 A JP 2008523620A JP 2007545518 A JP2007545518 A JP 2007545518A JP 2007545518 A JP2007545518 A JP 2007545518A JP 2008523620 A JP2008523620 A JP 2008523620A
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- Element Separation (AREA)
Abstract
さらに、半導体装置の形成法が提供される。第1結晶方位を有し、第1絶縁層14が上に形成された第1シリコン基板18と、第1絶縁層14上に重なる、第2結晶方位および結晶面を有する第1シリコン層19とを含むシリコン・オン・インシュレータ構造は、第2シリコン基板20に結合される。第2シリコン基板20は第2結晶方位および結晶面を有し、第2絶縁層24がその上に形成される。第2シリコン基板20は、水素イオンを第2シリコン基板20に注入することで生成される線欠陥22を含む。第2シリコン基板20の結晶面は、第1シリコン層19の結晶面に対して実質的に直角に方向付けられる。第2シリコン基板20は線欠陥22に沿って分離されるとともに除去され、第2絶縁層24および第2シリコン層25がシリコン・オン・インシュレータ構造上に残る。次に、シリコン・オン・インシュレータ構造を異なる結晶方位からなるシリコン層にまで選択的にエッチングし、エッチングした領域に選択的エピタキシャルシリコン層を成長させ、その後、シリコン・オン・インシュレータ構造を化学機械研磨によって平坦化することによって、異なる結晶方位を有する複数のデバイスを単一のプレーナシリコン・オン・インシュレータ構造上に形成することができる。
Description
トレンチ領域44を酸化シリコンで充填する従来の方法の一部として、
(a)テトラエチルオルソシリケート(tetraethylorthosilicate)低圧化学蒸着(TEOS LPCVD)
(b)非表面感受性TEOSオゾン大気圧化学蒸着法あるいは準大気圧化学蒸着法(APCVDあるいはSACVD)、および
(c)シラン酸化高密度プラズマCVD
が挙げられる。
Claims (10)
- 第1結晶方位を有する基板(18)と、
前記基板(18)上に位置する第1絶縁層(14)と、
前記第1絶縁層(14)上に位置する複数のシリコン層とを含み、
第1シリコン層(42)は、第2結晶方位および結晶面を有するシリコンを含み、第2シリコン層(25)は第2結晶方位および前記第1シリコン層(42)の結晶面に対して実質的に直角な結晶面を含む、半導体装置。 - 前記第1シリコン層(42)および第2シリコン層(25)は絶縁領域(48)により分離される、請求項1記載の半導体装置。
- 前記基板(18)上に位置する第3シリコン層(40)を更に含む、請求項1記載の半導体装置。
- 前記第3シリコン層(40)は、絶縁領域(48)によって前記第1シリコン層(42)および第2シリコン層(25)から分離される、請求項3記載の半導体装置。
- MOSFET(60、62、58)は、前記第1シリコン層(42)、第2シリコン層(25)、および第3シリコン層(40)の各々に形成される、請求項4記載の半導体装置。
- 第1結晶方位を有し、第1絶縁層(14)が上に形成された第1シリコン基板(18)と、前記第1絶縁層(14)上に位置する、第2結晶方位および結晶面を有する第1シリコン層(19)とを含むシリコン・オン・インシュレータ構造を提供するステップと、
前記第2結晶方位と結晶面とを有する第2シリコン基板(20)と、前記第2基板上に形成された第2絶縁層24とを提供するステップであって、前記第2シリコン基板(20)は水素イオンを前記第2シリコン基板(20)に注入することにより生成された線欠陥(22)を含むところのステップと、
前記第2シリコン基板(20)の前記結晶面が前記第1シリコン層(19)の前記結晶面に対して実質的に直角に方向付けられるように、前記第2絶縁層(24)および前記第1シリコン層(19)を介して、前記第2シリコン基板(20)を前記シリコン・オン・インシュレータ構造に結合するステップと、
前記線欠陥(22)に沿って前記第2シリコン基板(20)を分離するとともに除去し、前記第2絶縁層(24)と第2シリコン層(25)とを前記シリコン・オン・インシュレータ構造上に残すステップとを含む、半導体装置の形成方法。 - 前記第2シリコン層(25)、第2絶縁層(24)、第1シリコン層(19)および第1絶縁層(14)の一部を除去し、シリコン・オン・インシュレータ構造の第1領域に第1開口部(30)を形成し、前記第1シリコン基板(18)の一部(34)を露出させるステップと、
前記第2シリコン層(25)および第2絶縁層(24)の一部を除去し、前記シリコン・オン・インシュレータ構造の第2領域に第2開口部(32)を形成し、前記第1シリコン層(19)の一部(36)を露出させるステップとをさらに含む、請求項6記載の半導体装置の形成方法。 - 前記第1開口部(30)および第2開口部(32)のサイドウォール上にサイドウォールスペーサ(38)を形成するステップと、
前記シリコン・オン・インシュレータ構造の前記第1領域(52)において前記第1結晶方位を有する第3シリコン層(40)、前記シリコン・オン・インシュレータ構造の前記第2領域(54)において前記第2結晶方位および結晶面を有する第1シリコン層(19、42)、および、前記シリコン・オン・インシュレータ構造の第3領域(56)において、第2結晶方位および前記第1シリコン層(19、42)の前記結晶面に対して実質的に垂直な結晶面を持つ前記第2シリコン層(25)を有する第3シリコン層(40)を備えた、シリコン・オン・インシュレータ構造を提供するために、前記第1開口部(30)と第2開口部(32)にエピタキシャルシリコンを成長させるステップとを含む、請求項7記載の半導体装置の形成方法。 - 前記第1領域(52)を前記第2領域(54)および第3領域(56)から分離するとともに、前記第2領域(54)を前記第3領域(56)から分離するために、前記シリコン・オン・インシュレータ構造に複数の絶縁領域(48)を形成するステップを更に含む、請求項8記載の半導体装置の形成方法。
- 前記シリコン・オン・インシュレータ構造の前記第1領域(52)、第2領域(54)および第3領域(56)に、MOSFET(58、60、62)を形成するステップを更に含む、請求項20記載の半導体装置の形成方法。
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US11/006,747 US7422956B2 (en) | 2004-12-08 | 2004-12-08 | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
PCT/US2005/043398 WO2006062796A2 (en) | 2004-12-08 | 2005-11-29 | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
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CN100578751C (zh) | 2010-01-06 |
KR20070086303A (ko) | 2007-08-27 |
WO2006062796A2 (en) | 2006-06-15 |
TW200625635A (en) | 2006-07-16 |
TWI380442B (en) | 2012-12-21 |
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GB2434034B (en) | 2010-02-17 |
US7422956B2 (en) | 2008-09-09 |
WO2006062796A3 (en) | 2006-08-03 |
DE112005003123T5 (de) | 2008-04-17 |
GB2434034A (en) | 2007-07-11 |
DE112005003123B4 (de) | 2011-11-10 |
US20060118918A1 (en) | 2006-06-08 |
KR101175342B1 (ko) | 2012-08-21 |
CN101065840A (zh) | 2007-10-31 |
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