CN101013686A - 互连衬底、半导体器件及其制造方法 - Google Patents

互连衬底、半导体器件及其制造方法 Download PDF

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Publication number
CN101013686A
CN101013686A CNA2007100047900A CN200710004790A CN101013686A CN 101013686 A CN101013686 A CN 101013686A CN A2007100047900 A CNA2007100047900 A CN A2007100047900A CN 200710004790 A CN200710004790 A CN 200710004790A CN 101013686 A CN101013686 A CN 101013686A
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Prior art keywords
electrode pad
opening
interconnect substrate
semiconductor chip
ground floor
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CN101013686B (zh
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本多广一
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NEC Electronics Corp
NEC Corp
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NEC Corp
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Abstract

本发明涉及一种互连衬底，包括互连、绝缘层、非光敏树脂层、光敏树脂层、第一电极焊盘以及第二电极焊盘。非光敏树脂层由非光敏绝缘材料构成。另外，非光敏树脂层具有第一开口。光敏树脂层由光敏绝缘材料构成。另外，光敏树脂层具有第二开口。第二开口的开口面积大于第一开口的开口面积。第一电极焊盘被设置在绝缘层的第一表面侧。第一电极焊盘暴露于第一开口。第二电极焊盘被设置在绝缘层的第二表面侧。第二电极焊盘暴露于第二开口。

Description

互连衬底、半导体器件及其制造方法
本申请基于日本专利申请第2006-022809号，在此通过引用将其内容并入本文。
技术领域
本发明涉及互连衬底和利用该半导体衬底的半导体器件，以及它们的制造方法。
背景技术
例如，在日本特开专利公开第2004-111536号中公开了一种常规的互连衬底。如下制造本文公开的互连衬底。首先，在基底金属板的一个表面上形成第一绝缘层。接下来，在该第一绝缘层上形成将要与例如LSI的半导体芯片连接的第一电极焊盘。因此，在第一电极焊盘上形成了由多层互连和覆盖所述互连的绝缘体构成的互连层。
此后，在互连层上形成将要与例如母板的印刷互连衬底连接的第二电极焊盘。进一步地，在该第二电极焊盘上形成第二绝缘层之后，在该第二绝缘层中形成开口(第二开口)，从而暴露第二电极焊盘。接下来，通过蚀刻去除基底金属板。因此，在第一绝缘层中形成开口(第一开口)，从而暴露第一电极焊盘。上述工艺完成无芯型多层互连衬底。
这里，将要连接至印刷互连衬底的第二电极焊盘比将要与半导体芯片相连的第一电极焊盘具有更大的面积。与其相应的，第二开口具有比第一开口更大的面积。
除了日本特开专利公开No.2004-111536之外，涉及本发明的现有技术文献还有：例如日本特开专利公开No.2005-302922、2005-302943、2005-302968以及2005-302969。
发明内容
发明人发现了如下问题。即，为了形成具有相对较大的开口面积的第二开口，优选使用光刻方法。这是因为通过激光处理难以形成具有较大开口面积的开口。那么，为了使用光刻方法，必须利用光敏材料构造在其中要形成第二开口的第二绝缘层。
然而，通常，与利用非光敏材料构成的绝缘层相比，利用光敏材料构成的绝缘层在机械强度方面较差。绝缘层机械强度的降低导致了互连衬底以及由此提供的半导体器件的可靠性的降低。
根据本发明，提供一种互连衬底，包括：互连；覆盖该互连的绝缘层；在该绝缘层的第一表面上配置的并由非光敏绝缘材料构成的第一层，该第一层具有第一开口；在与第一表面相对的绝缘层的第二表面上配置的、并由光敏绝缘材料构成的第二层，该第二层具有第二开口，该第二开口具有比第一开口更大的开口面积；在绝缘层的第一表面侧上配置第一电极焊盘，并将其暴露于第一开口；以及在绝缘层的第二表面侧上配置第二电极焊盘，并将其暴露于第二开口。
在该互连衬底中，第二层由光敏绝缘材料构成。这允许使用光刻方法来形成具有较大开口面积的第二开口。因此，可以容易地形成该第二开口。另一方面，在其中形成有开口面积较小的第一开口的第一层由非光敏绝缘材料构成。因此，可以获得具有优异机械强度的第一层。从而实现了便于制造并具有高可靠性的互连衬底。
根据本发明，提供一种半导体器件，包括：上述互连衬底；以及连接至第一电极焊盘的半导体芯片。此半导体器件具备上述的互连衬底。从而实现了便于制造且具有高可靠性的半导体器件。
根据本发明，还提供了一种制造互连衬底的方法，包括：在支撑衬底上形成由非光敏绝缘材料构造的第一层；在该第一层上形成第一电极焊盘；在该第一电极焊盘上形成互连和覆盖该互连的绝缘层；在该绝缘层上形成第二电极焊盘；利用光敏绝缘材料构造第二层，以覆盖第二电极焊盘；在该第二层中形成第二开口，从而暴露第二电极焊盘；在形成第二开口之后去除支撑衬底；以及在去除该支撑衬底之后在第一层中形成第一开口，从而暴露第一电极焊盘，该第一开口具有小于第二开口的开口面积。
根据本发明，还提供一种制造半导体器件的方法，包括：在支撑衬底上形成由非光敏绝缘材料构造的第一层；在该第一层上形成第一电极焊盘；在该第一电极焊盘上形成互连和覆盖该互连的绝缘层；在该绝缘层上形成第二电极焊盘；形成由光敏绝缘材料构造的第二层，以覆盖第二电极焊盘；在该第二层中形成第二开口，从而暴露第二电极焊盘；在形成第二开口之后去除支撑衬底；在去除该支撑衬底之后在第一层中形成第一开口，从而暴露第一电极焊盘，该第一开口具有小于第二开口的开口面积；以及将半导体芯片连接至暴露于第一开口的第一电极焊盘。
在这些制造方法中，形成了由光敏绝缘材料构成的第二层。这允许使用光刻方法来形成具有较大开口面积的第二开口。因此，可以容易地形成该第二开口。另一方面，作为在其中将要形成开口面积较小的第一开口的层，形成了由非光敏绝缘材料构成的第一层。因此，可以获得具有优异机械强度的第一层。从而可以容易地制造具有高可靠性的互连衬底和半导体器件。
根据本发明，实现了便于制造且具有高可靠性的互连衬底和半导体器件以及它们的制造方法。
附图说明
通过下面的说明并结合附图，本发明的上面和其它目的、优点和特征将更加显而易见，在附图中：
图1示出了根据本发明的互连衬底和半导体器件的第一实施例的剖视图；
图2A和2B示出了图1的半导体器件一部分的剖视图；
图3A至3C示出了图1的半导体器件制造方法的一个示例的工艺图；
图4A至4C示出了图1的半导体器件制造方法的一个示例的工艺图；
图5A至5C示出了图1的半导体器件制造方法的一个示例的工艺图；
图6A至6C示出了图1的半导体器件制造方法的一个示例的工艺图；
图7A至7C示出了图1的半导体器件制造方法的一个示例的工艺图；
图8A至8C示出了图1的半导体器件制造方法的一个示例的工艺图；
图9A至9C示出了图1的半导体器件制造方法的一个示例的工艺图；
图10示出了实施例修改示例的剖视图；
图11示出了实施例修改示例的剖视图；
图12A和12B示出了实施例修改示例的剖视图；
图13示出了实施例修改示例的剖视图；
图14A和14B示出了常规倒装芯片型半导体器件的一个示例的剖视图；
图15A至15C示出了常规积层衬底制造方法的工艺图。
图16A至16C示出了常规积层衬底制造方法的工艺图。
具体实施方式
下面参考解释性实施例说明本发明。本领域技术人员明白，利用本发明的启示可以实现多种替换实施例，并且本发明并不局限于用于解释目的的实施例。
下面，参考附图，将详细说明根据本发明的互连衬底和半导体器件及其制造方法的优选实施例。在此处对于附图的说明中，相同的元件以相同的引用标记表示，并且不再对其重复说明。
图1示出了根据本发明的互连衬底和半导体器件的第一实施例的剖视图。半导体器件1包括互连衬底10和半导体芯片60。互连衬底10包括互连12、绝缘层14、非光敏树脂层20(第一层)、光敏树脂层30(第二层)，电极焊盘40(第一电极焊盘)以及电极焊盘50(第二电极焊盘)。该互连衬底10是不具有芯衬底的无芯多层互连衬底。
互连12被绝缘层14覆盖。另外，互连12被设置在绝缘层14的多个层中。也就是，互连12具有多层互连结构。非光敏树脂层20被设置在绝缘层14的表面S1(第一表面)上。利用非光敏绝缘材料构造该非光敏树脂层20。非光敏树脂层20可具有多层结构，在所述多层结构中层叠了由不同的非光敏绝缘材料构造的多个层。另外，非光敏树脂层20具有开口22(第一开口)。
光敏树脂层30设置在绝缘层14的表面S2(第二表面)上。表面S2是与表面S1相对的表面。利用光敏绝缘材料构造光敏树脂层30。另外光敏树脂层30具有开口32(第二开口)。开口32的开口面积大于开口22的开口面积。
电极焊盘40被设置在绝缘层14的表面S1侧上。具体地，电极衬底40被设置在绝缘层14的表面S1侧上的表面层中。电极焊盘40暴露于开口22。也就是，上述开口22位于电极焊盘40上方。此电极焊盘40是将与半导体芯片60连接的电极焊盘。另外，构成电极焊盘40的材料可以是，例如单一元素Cu。
电极焊盘50被设置在绝缘层14的表面S2侧上。具体地，电极焊盘50被设置在绝缘层14的表面S2。电极焊盘50暴露于开口32。也就是，上述开口32位于电极焊盘50之上。此电极焊盘50是将要与印刷互连衬底(未示出)连接的电极焊盘，其中所述印刷互连衬底例如是母板。
这里，电极焊盘50的面积大于电极焊盘40的面积。电极焊盘50的布局间距也大于电极焊盘40的布局间距。另外，开口22的开口面积小于电极焊盘40的开口面积。类似地，开口32的开口面积小于电极焊盘50的开口面积。
参考图2A和2B，将更详细地说明电极焊盘40和电极焊盘50。这些图示出了半导体器件1的一部分的剖视图。如图2A所示，多层膜42被设置在暴露于开口22的电极焊盘40的一部分上。此多层膜42由设置在电极焊盘40上的Ni膜42a和设置在Ni膜42a上的Au膜42b的叠层制成。类似地，如图2B所示，多层膜52被设置在暴露于开口32的电极焊盘50的一部分上。此多层膜52由设置在电极焊盘50上的Ni膜52a和设置在Ni膜52a上的Au膜52b的叠层制成。
回到图1，半导体芯片60连接至互连衬底10的电极焊盘40。具体地，半导体芯片60具有凸电极62，并且此凸电极62经由焊料72连接到电极焊盘40。也就是，半导体芯片60以倒装芯片的方式连接至互连衬底10。半导体芯片60可以是，例如LSI。
使用底部填充树脂74填充互连衬底10和半导体芯片60之间的间隙。进一步地，半导体芯片60被密封树脂76覆盖。另外，对于上述的电极焊盘50，连接了作为半导体器件1外部电极端子的焊料球78。然而，可以使用引脚形状或者具有圆柱形式的直列形状的端子作为外部电极端子，用以取代焊料球78。
参考图3A至9C，示出了一种制造半导体器件1的方法作为制造根据本发明的互连衬底和半导体器件的方法的一个实施例。总得来说，该制造方法包括以下步骤(a)至(i)：
(a)在基底衬底90(支撑衬底)上形成非光敏树脂层20；
(b)在该非光敏树脂层20上形成电极焊盘40；
(c)在该电极焊盘40上形成互连12和覆盖该互连12的绝缘层14；
(d)在绝缘层14上形成电极焊盘50；
(e)形成光敏树脂层30以覆盖电极焊盘50；
(f)在该光敏树脂层30中形成开口32，从而暴露电极焊盘50；
(g)在形成开口32之后去除基底衬底90；
(h)在去除基底衬底90之后在非光敏树脂层20中形成开口22，从而暴露电极焊盘40；以及
(i)将半导体芯片60连接至暴露于开口22的电极焊盘40。
更具体地，首先，制备基底衬底90(图3A)。这里，优选地制备具有高平坦度和高机械强度的基底衬底90。例如，利用金属材料或者金属合金材料，例如SUS或者Cu作为主要成分构造基底衬底90。
接下来，在基底衬底90的一个表面上形成非光敏树脂层20(图3B)。非光敏树脂层20的断裂强度和断裂伸长率优选地分别为50Mpa或更高和10％或更高。可以利用处于半固态的由环氧树脂基树脂、氰酸脂基(cyanate-based)树脂或者聚烯烃基树脂制成的绝缘树脂膜，通过真空叠层方法或者真空压力方法可以容易地形成该非光敏树脂层20。另外，可以通过涂覆液体形式的材料，例如PI(聚酰亚胺)，从而形成非光敏树脂层20。
接下来，在非光敏树脂层20的预定位置处形成电极焊盘40(图3C)。例如，可以利用通用的非电解Cu镀籽晶，通过半加成处理方法形成由Cu材料制成的电极焊盘40。这里，假设要安装具有如LSI(半导体芯片60)的区域阵列布局的FC(倒装芯片)器件，该区域阵列布局的FC端子间距可以是，例如约150至250μm。另外，电极焊盘40的直径可以是，例如约60至100μm。
接下来，在电极焊盘40上形成绝缘层14a(图4A)。可以通过上述真空叠层法或者真空压力法容易地形成绝缘层14a。另外，作为一种形成绝缘层14a的不同技术，可以提出一种通过应用等离子表面处理技术，利用旋涂法以及CVD(化学气相淀积)法和PVD(物理气相淀积)法形成液体形式的绝缘材料等的方法。
接下来，执行部分地去除绝缘层14a的工艺，从而形成开口16a(图4B)。这里，当利用光敏材料构成绝缘层14a时，可以通过执行曝光和显影工艺从而形成开口16a。另一方面，当利用非光敏材料构成绝缘层14a时，通过激光处理形成开口16a。在后一情况下，在光刻胶的图案形成之后，通过应用等离子表面处理技术，可利用干法蚀刻技术形成开口16a。
这里，考虑到绝缘层14a的抗破裂特性，优选地应用通常具有优异的断裂强度和断裂伸长比的非光敏材料。另外，通过考虑产品的可靠性，可以利用相同的非光敏材料形成非光敏树脂层20和绝缘层14a。
接下来，在绝缘层14a上形成互连12(图4C)。在形成互连12时，可以使用半加成处理方法。在此处理方法中，首先通过非电解Cu镀或者Ti/Cu的溅射法等在绝缘层14a的整个表面上形成用于电镀的供电层(籽晶金属)。接下来，在涂覆光刻胶和执行曝光与显影工艺从而使预定的互连图案被剥离暴露之后，通过使用电镀方法形成Cu等的互连图案。随后，在剥离掉光刻胶之后，利用互连图案作为掩模通过蚀刻去除下面的供电层。这完成了互连12。
此后，将上述从形成绝缘层14a到形成互连12的步骤重复预定次数，以获得多层互连结构。也就是，在此示例中，在绝缘层14a上形成绝缘层14b之后，在绝缘层14b中形成开口16b(图5A)。在绝缘层14b上形成互连12(图5B)。进一步地，在绝缘层14b上形成绝缘层14c之后，在绝缘层14c中形成开口16c(图5C)。上面的工艺完成了绝缘层14。
接下来，在多层互连的最上层，也就是绝缘层14c的预定位置处通过上述半加成处理法等形成电极焊盘50(图6A)。假设要将电极焊盘50连接至母板，电极焊盘50的布局间距是，例如约0.4至1.0mm。另外，电极焊盘50的直径是，例如约0.18至0.6mm。
接下来，在绝缘层14上形成光敏树脂层30，以覆盖电极焊盘50。进一步地，在光敏树脂层30中形成开口32，从而暴露电极焊盘50(图6B)。优选地通过光刻法形成开口32。
接下来，通过化学蚀刻等去除基底衬底90(图6C)。此时，非光敏树脂层20起到蚀刻阻挡层的作用。这里，当基底衬底90的材料是基于Cu的金属时，可以利用氯化铜的水溶液或者基于氨的碱性蚀刻剂通过蚀刻选择性地去除该基于Cu的金属。另外，当基底衬底90的材料是基于SUS的金属时，可以利用氯化铁的水溶液通过蚀刻去除该基于SUS的金属。
接下来，在非光敏树脂层20中形成开口22，从而暴露电极焊盘40(图7A)。优选地通过激光处理形成开口22。这里，当通过激光处理在开口22的底部生成碳化树脂层(污染层)等时，在激光处理之后通过高锰酸盐处理来执行去除处理。
接下来，在暴露于开口22的电极焊盘40的一部分上形成多层膜42，并且在暴露于开口32的电极焊盘50的一部分上形成多层膜52(图7B)。可通过非电镀法形成多层膜42和多层膜52。以上完成了互连衬底10。这里，通过将在其上分别形成多层膜42和多层膜52的电极焊盘40和电极焊盘50用作电极，利用电测试探头执行互连衬底10的电测试(开路/短路测试)。
此后，在非光敏树脂层20上形成了印刷掩模M1之后，利用焊膏72a和印刷胶刮92执行普通的印刷工艺(图7C)。在通过此工艺将焊膏72a放置在开口22中之后，执行诸如IR回流焊的焊接工艺来形成焊料72(预备焊料部件)(图8A)。
接下来，在互连衬底10的电极焊盘40上以倒装芯片的方式安装半导体芯片60(图8B)。此时，当半导体芯片60的凸电极62是包含诸如Sn或Pb的金属材料作为主要成分的焊料时，可以通过利用助焊剂的加热回流焊工艺以倒装芯片的方式安装半导体芯片60。另外，当凸电极62是包含诸如Au或In的金属材料作为主要成分的焊料时，可以通过热压接合法以倒装芯片的方式安装半导体芯片60。
此后，半导体芯片60和互连衬底10之间的间隙以绝缘底部填充树脂74填充(图8C)。在此示例中，半导体芯片60的侧表面也被底部填充树脂74所覆盖。可以通过利用液体形式的底部填充材料的密封技术或者通过传压密封技术(transfer sealing)等来形成底部填充树脂74。通过提供底部填充树脂74，可以有效地保护半导体芯片60和互连10及其连接部件。
此后，在互连衬底10上形成密封树脂76，以覆盖半导体芯片60(图9A)。可以通过传压密封技术、注入密封技术等形成密封树脂76。通过提供密封树脂76，对于半导体器件1的半导体封装来说，可以实现在机械强度和防潮方面的提高。
此后，将包括诸如Sn的金属材料作为主要成分的焊球78连接至电极焊盘50(图9B)。可以通过，例如将助焊剂选择性地施加至电极衬底50上并随后安装焊球78且利用IR回流焊工艺进行热处理，从而连接焊球78。
此后，利用切割刀等的切割与分离技术用于将晶片分离为多个片(图9C)。上述工艺完成了半导体器件1。
下面说明本实施例的效果。在互连10中，利用光敏绝缘材料构造光敏树脂层30。这允许使用光刻技术形成具有较大开口面积的开口32。因此，可以容易地形成开口32。
另一方面，可以考虑通过激光处理形成开口32。然而，对于激光处理，每次照射的处理直径上限约为100μm，因而不适合用于形成具有约180至600μm直径的电极焊盘50。另外，可以考虑通过干法蚀刻技术形成开口32。然而，采用真空技术的干法蚀刻装置通常极为昂贵。此外，还需要涂覆光刻胶和执行曝光与显影的工艺。这带来了生产成本增加的问题。由于这些原因，优选地使用光刻方法形成开口32。
另一方面，利用非光敏绝缘材料构成非光敏树脂层20，在所述非光敏树脂层20中形成有开口面积较小的开口22。通常，与光敏材料相比，非光敏材料具有优异的机械强度和断裂伸长比。因此，通过采用非光敏树脂层20，在互连衬底10中避免了产生诸如绝缘树脂裂缝的缺陷，因而提高了互连衬底10的可靠性。因此，实现了便于制造并具有高可靠性的互连衬底10。另外，半导体器件1具备此互连衬底10。从而实现了便于制造并具有高可靠性的半导体器件1。
开口22的开口面积小于电极焊盘40的面积。因此，将电极焊盘40表面(暴露于开口22的表面)的一部分构造为覆盖有非光敏树脂层20。这防止了电极焊盘40从绝缘层14剥落。类似地，开口32的开口面积小于电极焊盘50的面积。因此，将电极焊盘50表面(暴露于开口32的表面)的一部分构造为覆盖有光敏树脂层30。这防止了电极焊盘50从绝缘层14剥落。
多层膜42(见图2A)被设置在暴露于开口22的电极焊盘40的一部分上。这在形成焊料72时提高了焊接的稳定性。另外，在执行上述电子测试的情况下，可以使电极焊盘40与测试探头之间的接触电阻稳定。类似地，多层膜52(见图2B)被设置在暴露于开口32的电极焊盘50的一部分上。这在形成焊球78时提高了焊接的稳定性。另外，在执行上述电子测试的情况下，可以使电极焊盘50与测试探头之间的接触电阻稳定。
在开口22中提供焊料72作为预备焊料部件。这在以倒装芯片方式连接半导体芯片60时提高了焊接工艺的稳定性。具体地，当半导体芯片60的大小是15平方毫米或者更大时，电极焊盘40的平行度由于互连衬底10的扭曲往往趋于变差。因此，当考虑生产工艺时，这对于形成焊料72很重要。另一方面，当半导体芯片60的大小小于15平方毫米时，看不到上述趋势，因此对于形成焊料72来说并不重要。
另外，在本实施例的制造方法中，在基底衬底90上形成多层互连层。这将多层互连层机械地限制在基底衬底90，因此可以保持高度的平坦性。进一步地，该多层互连层在热分布方面具有优异的稳定性。因此实现了一种具有优异生产成品率和适于形成具有精密间距的互连的制造方法。
另一方面，在普通积层衬底的情况下，由于FR-4、5或者基于BT的芯衬底的扭曲或者细微不规则，图案间距在行和空间上具有10μm/10μm的限制。此外，由于芯衬底的扭曲较大，在图案曝光期间易于发生焦点深度的变化，这导致制造工艺的稳定性的降低。因此，在形成精密图案的方面以及鉴于生产成本的显著提高，常规制造方法具有技术的限制。
另外，在本发明的制造方法中，非光敏树脂层20在去除基底衬底90时起到蚀刻阻挡层的作用。这可以保护电极焊盘40。因此，将提高制造互连衬底10的工艺稳定性，从而提高生产率。
参考图14A和14B，下面说明常规倒装芯片型半导体器件的一个示例。此半导体器件包括图14A中所示的半导体芯片100。在半导体芯片100的表面上，形成了由导电材料(例如焊料、Au或者基于Sn-Ag的合金)构成的凸起块102。凸块102形成在外部端子上，这些外部端子以预定布局形成在芯片的外围或形成在有源区上，也就是，这些凸块形成在以区域阵列布局形成的外部端子上。
如图14B所示，该半导体芯片100安装在多层互连衬底110上。在此多层互连衬底110上，形成了以与凸块102布局图案的相同图案布置的电极焊盘(未示出)。在多层互连衬底110上安装半导体芯片100时，当焊料被用作凸块102的材料时，通常利用助焊剂执行IR回流工艺。
然而，在多层互连衬底上安装半导体芯片之后，由于它们之间线性膨胀系数不匹配，造成这样的问题，即温度周期特性变差，具体地是在安装可靠性方面。为了解决该问题，通常采取以下措施。
首先，为了使多层互连衬底的线性膨胀系数接近硅的线性膨胀系数，通过使用基于陶瓷的材料尝试使线性膨胀系数的不匹配最小化，从而提高安装可靠性，所述基于陶瓷的材料例如是ALN、莫来石(Mullite)或者玻璃陶瓷，这些都是昂贵的材料。这些尝试在提高安装可靠性方面有效。然而，由于使用昂贵的基于陶瓷的材料作为多层互连衬底材料，因此互连衬底的用途一般局限于高端超级计算机或者大型计算机的应用。
另一方面，近些年来，作为一种利用多层互连衬底在倒装芯片安装中提高安装可靠性的技术日益普及，其中所述多层互连衬底利用了具有较低的价格和较大线性膨胀系数的有机材料，将底部填充树脂放置在半导体芯片和采用有机材料的多层互连衬底之间。该技术是这样的技术，即通过将底部填充树脂放置在半导体芯片和采用有机材料的多层互连衬底之间，作用于凸块连接部件的剪应力被分散了，从而提高了安装可靠性，其中所述凸块连接部件位于半导体芯片和采用有机材料的多层互连衬底之间。
根据该技术，通过允许底部填充树脂介于半导体芯片和采用有机材料的多层互连衬底之间，可以使用具有低价格并采用有机材料的多层互连衬底。然而，与此同时当在底部填充树脂中出现孔隙时，或者当底部填充树脂和半导体芯片之间的界面处或底部填充树脂与采用多层互连衬底之间的界面处的粘和性差时，会出现以下问题。也就是，在产品的吸湿回流焊工艺中导致了界面剥落现象，从而在产品中产生了缺陷。因此，上述技术通常不能促进倒装芯片型半导体器件的成本降低。
另外，通常在倒装芯片型半导体器件中，考虑到凸块布局图案的最小间距和引脚的数量，通常将被称为积层衬底的多层互连衬底用作采用有机材料的多层互连衬底。
下面参考图15A至16C说明生产常规积层衬底的方法。首先，制备芯衬底120，在所述芯衬底中，具有10至40μm厚的Cu箔接合绝缘玻璃环氧树脂基底材料的两个表面上(图15A)，其中所述绝缘玻璃环氧树脂基底材料例如是由FR4、FR5或者BT衬底所代表的。该Cu箔经过图案化工艺变成互连122。进一步地，为了在上和下互连之间建立电连接，形成通孔部件124。可以通过钻孔工艺等并且随后执行通孔镀工艺来打孔形成通孔部件124。此时，考虑到后续步骤的工艺稳定性以及衬底的产品质量稳定性，通孔部件124的内部通常填充有绝缘树脂126，用于填充该通孔。
接下来，在互连120上形成绝缘树脂128，其中所述互连存在于芯衬底120的上方和下方。此后，通过采用光刻胶技术的化学蚀刻法或者激光处理技术等在绝缘树脂128的预定位置处形成开口129(图15B)。接下来，为了确保电解Cu镀工艺的供电层与芯衬底120上的互连122之间的电连接，通过利用诸如Ti/Cu的金属的溅射方法、非电解Cu镀方法等形成金属薄膜层130(图15C)。
此后，为了通过电解Cu镀工艺形成互连图案，在金属薄膜层130上形成约20至40μm厚的干膜或诸如光刻胶的M2掩模，并且执行曝光和显影工艺(图16A)。此后，利用金属薄膜层130作为供电层，通过电解Cu镀工艺形成互连图案部件132。接下来，在剥离掩模M2之后，利用互连图案部件132作为掩模，通过湿法蚀刻工艺去除金属薄膜层130，以使互连图案部件132电气独立(图16C)。重复上述从形成绝缘树脂128至形成互连图案部件132的步骤，以获得多层互连衬底。
然而，根据此制造方法，考虑到对由于与芯衬底120的热膨胀系数不匹配所导致的应力进行缓解以及考虑到诸如连接孔部件可靠性的多层互连衬底的可靠性，为了确保互连图案部件132的厚度，必须采用约20至40μm厚的干膜或者光刻胶。因此，在曝光与显影工艺中形成图案时，约30μm成为最小间距的极限。结果出现问题，使得不能促进多层互连衬底的高度致密和衬底形状的尺度降低。
另外，通常在积层衬底的生产中，采用了这样一种技术，使产品统一地在具有约500mm×600mm尺寸的大面板上制造，并且在最终步骤中通过执行切割工艺，从而获得各个单个多层互连衬底。因此，如果可以降低单个多层互连衬底的外部尺寸，则在每一面板上可获得的衬底数量可以增加。然而，在制造积层衬底的当前方法中，如上所述，只能将互连图案间距制造为最小约30μm。因此，不能降低单个多层互连衬底的外部尺度，从而难以很大程度地降低多层互连衬底的成本。
这种制造多层互连衬底的方法进一步具有扭曲的问题。芯衬底本身具有扭曲，并且在用于形成积层互连图案的曝光与显影工艺中，由于存在的扭曲而引入了抗蚀剂图案的不匹配。抗蚀剂图案的不匹配将造成生产成品率的降低。
另外，为了限制芯衬底的扭曲，必须在芯衬底的两侧上形成积层，因而有必要形成开始并不需要的积层互连层。结果，它将是基于有机的多层互连衬底，该衬底是超过所需的、被迫增加的层。这造成生产成品率降低，并且极难降低其生产成本。
比较而言，根据上述实施例的互连衬底10和半导体器件1及其制造方法，可以解决图14A至16C中所述的与常规技术关联的所有问题。
根据本发明的互连衬底和半导体器件及其制造方法并不局限于上述实施例，因此可以进行各种修改。例如，参考图10，半导体芯片66(第二半导体芯片)可设置在半导体芯片60(第一半导体芯片)上。半导体芯片66经由粘合剂67堆叠在半导体芯片60的背面上。另外，半导体芯片66经由接合线68连接至电极焊盘40。通过这样的构造，可以获得多种芯片类型的半导体器件。另外，当与半导体芯片60功能不同的半导体芯片被用作半导体芯片66时，可以获得该半导体器件的功能衍生。这里，在本示例中，半导体器件被堆叠为两级；然而可将半导体芯片堆叠为三级或更多级。
另外参考图11，热沉80可以设置在半导体芯片60上。热沉80经由粘合剂82连接至半导体芯片60的背面。对于粘合剂82，优选使用具有高导热率的粘合剂。另外，热沉80设置在从半导体芯片60至非光敏树脂层20的区域上，并且设置在半导体芯片60上的部分相对于设置在非光敏树脂层20上的部分突出。利用这样的构造，可以获得具有优异热扩散性的半导体器件。通常，倒装型半导体器件常常为多引脚或者高速逻辑器件，因此重要的是使半导体芯片产生的热能够高效地扩散。
另外，参考图12A，在形成第一层的步骤中，可经由绝缘粘合剂88在基底衬底90上接合非光敏绝缘膜86作为第一层。对于绝缘膜86，优选地使用具有高强度和高伸长性质的绝缘膜。在图12A中，在绝缘膜86上形成Cu箔40a。也就是，在基底衬底90上设置具有粘合剂的RCC(树脂涂覆的铜)，该RCC由Cu箔40a/绝缘膜86/绝缘粘合剂88的多层结构制成。通过在该Cu箔40a上执行图案化工艺，可以形成电极焊盘40(图12B)。可以通过采用减成(subtractive)技术来执行图案化Cu箔40a的工艺，通过该技术，在形成光刻胶以及执行曝光与显影工艺之后，通过蚀刻去除Cu箔40a的预定部分。此后，执行图4A至9C中说明的步骤，以获得图13所示的半导体器件。
根据这样的构造，绝缘粘合剂88起到粘和至基底衬底90的粘合剂的作用，因此如下所述的非光敏绝缘膜可以被用作第一层，其中所述非光敏绝缘膜与图1所示的非光敏树脂层20相比具有更大的厚度(例如，约10至30μm)，但不具有例如高强度PI膜或者液晶聚合物的粘合功能。非光敏PI膜通常具有断裂强度为100MPa或更高以及具有断裂伸长率为100％或更高的机械性质，从而在现有的绝缘材料中具有最高等级的抗破裂性质。因此可以获得具有更加优异的树脂抗破裂性质的无芯型多层互连衬底。
这里，在上述RCC中，在Cu箔40a和绝缘膜86之间存在绝缘粘合剂。也就是，该RCC可以由Cu箔40a/绝缘粘合剂/绝缘膜86/绝缘粘合剂88的多层结构制成。
显然，本发明并不局限于上面的实施例，并且可以在不脱离本发明的精神与保护范围的情况下进行修改与变化。

Claims (16)

1.一种互连衬底，包括：
互连；
覆盖所述互连的绝缘层；
在所述绝缘层的第一表面上配置的且由非光敏绝缘材料构成的第一层，所述第一层具有第一开口；
在与所述第一表面相对的所述绝缘层的第二表面上配置的第二层，且所述的第二层由光敏绝缘材料构成，所述第二层具有第二开口，该第二开口具有比所述第一开口的开口面积大的开口面积。
在所述绝缘层的所述第一表面侧上配置的且暴露于所述第一开口的第一电极焊盘；以及
在所述绝缘层的所述第二表面侧上配置的且暴露于所述第二开口的第二电极焊盘。
2.权利要求1所述的互连衬底，
其中所述互连具有多层互连结构。
3.权利要求1所述的互连衬底，
其中所述第二电极焊盘的面积大于所述第一电极焊盘的面积。
4.权利要求1所述的互连衬底，
其中所述第一开口与所述第二开口的开口面积分别小于所述第一电极焊盘与所述第二电极焊盘的面积。
5.权利要求1所述的互连衬底，
其中构成所述第一电极焊盘的材料是单一元素Cu。
6.权利要求1所述的互连衬底，
其中在暴露于所述第一开口的所述第一电极焊盘的一部分上，以及在暴露于所述第二开口的所述第二电极焊盘的一部分上配置有Ni和Au的多层膜。
7.权利要求1所述的互连衬底，
其中所述第一电极焊盘是与半导体芯片连接的电极焊盘，以及
所述第二电极焊盘是与印刷互连衬底连接的电极焊盘。
8.权利要求1所述的互连衬底，
其中所述第一层是非光敏绝缘膜。
9.一种半导体器件，包括：
权利要求1的所述互连衬底；以及
连接至所述第一电极焊盘的半导体芯片。
10.权利要求9所述的半导体器件，进一步包括在所述半导体芯片上配置的第二半导体芯片，
其中所述第二半导体芯片经由接合线路连接至所述第一电极焊盘。
11.权利要求9所述的半导体器件，进一步包括在所述半导体芯片上配置的热沉。
12.权利要求11所述的半导体器件，
其中在从所述半导体芯片上至所述第一层的区域上配置所述热沉，并且配置在所述半导体芯片上的部分所述热沉相对于配置在所述第一层上的部分所述热沉突出。
13.一种制造互连衬底的方法，包括：
在支撑衬底上形成由非光敏绝缘材料构成的第一层；
在所述第一层上形成第一电极焊盘；
在所述第一电极焊盘上形成互连以及覆盖所述互连的绝缘层；
在所述绝缘层上形成第二电极焊盘；
形成由光敏绝缘材料构成的第二层，以覆盖所述第二电极焊盘；
在所述第二层中形成第二开口，从而暴露所述第二电极焊盘；
在形成所述第二开口之后去除所述支撑衬底；以及
在去除所述支撑衬底之后，在所述第一层中形成第一开口，从而暴露所述第一电极焊盘，所述第一开口具有小于所述第二开口的开口面积的开口面积。
14.权利要求13所述的制造互连衬底的方法，
其中在形成所述第二开口时，通过光刻方法形成所述第二开口，以及
在形成所述第一开口时，通过激光处理形成所述第一开口。
15.权利要求13所述的制造互连衬底的方法，
其中，在形成所述第一层时，通过绝缘粘合剂的中间物，在所述支撑衬底上接合非光敏绝缘膜作为所述第一层。
16.一种制造半导体器件的方法，包括：
在支撑衬底上形成由非光敏绝缘材料构成的第一层；
在所述第一层上形成第一电极焊盘；
在所述第一电极焊盘上形成互连以及覆盖所述互连的绝缘层；
在所述绝缘层上形成第二电极焊盘；
形成由光敏绝缘材料构成的第二层，以覆盖所述第二电极焊盘；
在所述第二层中形成第二开口，从而暴露所述第二电极焊盘；
在形成所述第二开口之后去除所述支撑衬底；以及
在去除所述支撑衬底之后，在所述第一层中形成第一开口，从而暴露所述第一电极焊盘，所述第一开口具有小于所述第二开口的开口面积的开口面积；以及
将半导体芯片连接至暴露于所述第一开口的所述第一电极焊盘。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402017B (zh) * 2008-07-23 2013-07-11 Nec Corp 半導體裝置及其製造方法
CN103311132A (zh) * 2013-05-20 2013-09-18 江苏长电科技股份有限公司 金属框多层线路基板先镀后蚀工艺方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090178839A1 (en) * 2007-03-14 2009-07-16 Toshiaki Takenaka Recognition mark and method for manufacturing circuit board
JP2009302427A (ja) * 2008-06-17 2009-12-24 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
US20100073894A1 (en) * 2008-09-22 2010-03-25 Russell Mortensen Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same
JPWO2011089936A1 (ja) * 2010-01-22 2013-05-23 日本電気株式会社 機能素子内蔵基板及び配線基板
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
JP5565000B2 (ja) * 2010-03-04 2014-08-06 カシオ計算機株式会社 半導体装置の製造方法
US8866301B2 (en) * 2010-05-18 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers with interconnection structures
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
KR101719636B1 (ko) 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
TWI474444B (zh) * 2011-12-28 2015-02-21 Princo Corp 超薄多層基板之封裝方法
TWI433621B (zh) * 2011-12-28 2014-04-01 Princo Corp 超薄多層基板之封裝方法
TWI440412B (zh) * 2011-12-28 2014-06-01 Princo Corp 超薄多層基板之封裝方法
JP2017050464A (ja) * 2015-09-03 2017-03-09 凸版印刷株式会社 配線基板積層体、その製造方法及び半導体装置の製造方法
TWI582921B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
TWI582903B (zh) * 2015-12-02 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
TWI582864B (zh) * 2015-12-09 2017-05-11 南茂科技股份有限公司 半導體封裝結構及其製作方法
CN115547846A (zh) * 2019-02-21 2022-12-30 奥特斯科技(重庆)有限公司 部件承载件及其制造方法和电气装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886362A (en) * 1993-12-03 1999-03-23 Motorola, Inc. Method of reflowing solder bumps after probe test
KR950027550U (ko) * 1994-03-07 1995-10-18 정의훈 클로즈 가이드(Cloth guide)의 경사안내로울러 좌. 우 이송장치
US5587882A (en) * 1995-08-30 1996-12-24 Hewlett-Packard Company Thermal interface for a heat sink and a plurality of integrated circuits mounted on a substrate
US6609652B2 (en) * 1997-05-27 2003-08-26 Spheretek, Llc Ball bumping substrates, particuarly wafers
US5893726A (en) * 1997-12-15 1999-04-13 Micron Technology, Inc. Semiconductor package with pre-fabricated cover and method of fabrication
US6235544B1 (en) * 1999-04-20 2001-05-22 International Business Machines Corporation Seed metal delete process for thin film repair solutions using direct UV laser
JP3908157B2 (ja) * 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402017B (zh) * 2008-07-23 2013-07-11 Nec Corp 半導體裝置及其製造方法
CN103311132A (zh) * 2013-05-20 2013-09-18 江苏长电科技股份有限公司 金属框多层线路基板先镀后蚀工艺方法
CN103311132B (zh) * 2013-05-20 2015-08-26 江苏长电科技股份有限公司 金属框多层线路基板先镀后蚀工艺方法

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