CN100527373C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN100527373C
CN100527373C CNB2006101000273A CN200610100027A CN100527373C CN 100527373 C CN100527373 C CN 100527373C CN B2006101000273 A CNB2006101000273 A CN B2006101000273A CN 200610100027 A CN200610100027 A CN 200610100027A CN 100527373 C CN100527373 C CN 100527373C
Authority
CN
China
Prior art keywords
semiconductor device
electrode pad
outside terminal
mask layer
salient point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2006101000273A
Other languages
English (en)
Other versions
CN101026109A (zh
Inventor
藤森城次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of CN101026109A publication Critical patent/CN101026109A/zh
Application granted granted Critical
Publication of CN100527373C publication Critical patent/CN100527373C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11515—Curing and solidification, e.g. of a photosensitive bump material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13309—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13318—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1332—Antimony [Sb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13364—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13369—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742—Apparatus for manufacturing bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Abstract

本发明提供一种成本低、易使用及效率高的制造半导体器件的方法及具有以窄间距排列的微凸点的高性能半导体器件，该制造半导体器件的方法使得在形成凸点时不需要形成或去除阻挡金属。该方法包括如下步骤：在半导体衬底(10)的一个表面上形成多个电极焊盘(12)；形成覆盖在各个电极焊盘(12)的周边的绝缘层，例如无机绝缘层(14)和有机绝缘层(16)；在所述绝缘层(14，16)上有选择地形成掩模层(20)；清洗电极焊盘(12)的没有被所述绝缘层(14，16)覆盖的表面；在由所述绝缘层(14，16)和该掩模层(20)界定的区域中形成外部端子(46)，使其与所述电极焊盘(12)接触；以及去除该掩模层(20)。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请基于2006年2月17日申请的在先日本专利申请No.2006-040866并要求其优先权，在此通过参考援引其全部内容。
技术领域
本发明涉及一种成本低、易使用及效率高的制造半导体器件的方法及具有以窄间距排列的微凸点的高性能半导体器件，该制造半导体器件的方法使得在形成凸点时不需要形成或去除阻挡金属。
背景技术
近年来，随着电子器件变薄、变小的趋势，人们力图减小半导体器件的尺寸和获得更大的封装密度。在这样的背景之下，半导体器件中电极间距变小的趋势产生了新的获得微间距凸点的需要——例如，柱形电极(凸点)现今已得到适当地使用。在此，传统半导体器件的实例在图9中示出。
在图9所示的半导体器件中，等间距设置的电极焊盘510形成在半导体衬底500的一个表面上，覆盖膜520形成在半导体衬底500上，覆盖各个电极焊盘510之间的间隙。保护膜530延伸在半导体衬底500上，覆盖覆盖膜520的整个表面和各个电极焊盘510的一部分。焊料凸点550形成在电极焊盘510上，且阻挡金属540位于焊料凸点550与电极焊盘510之间。阻挡金属540具有提高电极焊盘510与焊料凸点550之间的粘附性的功能。
在这种外部端子结构中，需要在减小凸点间距的同时将阻挡金属540小型化。然而，这种小型化难以实现并导致不期望的成本增加。此外，当使用这样的焊料凸点时，它们在回流处理中变为接近球形，从而难以获得更微小的凸点间距。注意：在这种传统的半导体器件中，能够以大约170μm至220μm的间距形成凸点。
已提出了如下几种用于形成凸点的方法：一种方法是在形成于被覆盖的电路板上的电极周围设置开口，并利用刮板(squeegee)在上述开口中嵌入已在减压环境下涂在电路板上的焊料(参见日本特开(JP-A)No.2004-128354)；另一种方法是在减压环境下将焊膏印刷在具有焊盘(solderpad)的印刷布线板上(参见日本特开(JP-A)No.2002-111192)。然而，通过这些方法形成的凸点存在一个问题：由于它们由焊料形成，在回流处理中会变为球形，因此凸点间距不够窄。
此外，有一种已知的方法利用电镀形成凸点。通过这种方法，阻挡金属一般形成在凸点与互连(或焊盘)之间。这样的阻挡金属具有如下优点：通过电镀在焊盘上形成凸点时，增加了凸点与焊盘之间的粘附性并用作公共电极。凸点间距变小的趋势要求阻挡金属小型化；然而，阻挡金属的小型化难以实现并导致不期望的成本增加，从而与减少单个半导体器件和封装的成本的趋势相背离。
另外，还提出了如下方法作为凸点的形成方法：在焊盘表面上形成用与阻挡金属相同的材料制成的抗反射膜，而省略阻挡金属形成工艺，然后将抗反射膜在形成凸点的电镀期间用作公共电极(参见日本特开(JP-A)No.8-162456)。然而，通过这种方法，在形成凸点之后，多余的互连层露在外面，需要将其去除。为此，需要采用与传统的阻挡层去除工艺类似的工艺，因此这种方法就简化制造工艺而言不符合要求。
因此，已提供一种成本低、易使用及效率高的制造半导体器件的方法及具有以窄间距排列的微凸点的高性能半导体器件，该制造半导体器件的方法使得在形成凸点时不需要形成或去除阻挡金属，并能够以窄间距形成凸点。
本发明的目的是解决上述传统问题并实现以下所述的目的。具体地，本发明的目的是提供一种成本低、易使用及效率高的制造半导体器件的方法及具有以窄间距排列的微凸点的高性能半导体器件，该制造半导体器件的方法使得在形成凸点时不需要形成或去除阻挡金属。
发明内容
以下是解决上述问题的手段。
本发明的制造半导体器件的方法包括如下步骤：在半导体衬底的一个表面上形成多个电极焊盘；形成覆盖在各个电极焊盘的周边的绝缘层；在该绝缘层上有选择地形成掩模层；清洗电极焊盘的没有被绝缘层覆盖的表面；在由该绝缘层和该掩模层界定的区域中形成外部端子，使其与所述电极焊盘接触；以及去除掩模层。
在这种方法中，首先，在半导体衬底的一个表面上形成多个电极焊盘。形成覆盖在各个电极焊盘的周边的绝缘层。在绝缘层上有选择地形成掩模层。清洗电极焊盘的没有被绝缘层覆盖的表面。在由绝缘层和掩模层界定的区域中形成外部端子，使其与电极焊盘接触。最后，去除掩模层。在去除掩模层的步骤中，未暴露电极焊盘。例如，当阻挡金属形成在半导体衬底上且凸点(外部端子)形成在阻挡金属上时，需要去除阻挡金属的暴露部位的一部分。然而，在本发明的方法中，不需要形成这样的阻挡金属，也就不需要将其去除。因此，通过本发明的方法，能够容易、高效且低成本地制造具有以窄间距排列的凸点的半导体器件。
本发明的半导体器件包括：多个电极焊盘，形成在半导体衬底的一个表面上；覆盖在各个电极焊盘的周边的绝缘层；以及外部端子，形成在所述电极焊盘上并与所述电极焊盘接触，所述外部端子具有基本上平行于所述电极焊盘表面的平坦表面。
在本发明的半导体器件中，外部端子与电极焊盘直接接触，通常，在外部端子与电极焊盘之间不形成阻挡金属。
本发明还提供一种半导体器件，包括：多个电极焊盘，形成在半导体衬底的一个表面上；绝缘层，覆盖在各个电极焊盘的周边；以及外部端子，形成在所述电极焊盘上并与所述电极焊盘接触，所述外部端子具有平行于所述电极焊盘表面的平坦表面，形成在所述电极焊盘上的所述外部端子具有在所述绝缘层的表面延伸，并大于所述绝缘层界定的开口尺寸的尺寸，其中相邻的外部端子之间的距离为150μm或更小。本发明的半导体器件具有以窄间距排列的微凸点并具有高性能。
附图说明
图1A为说明本发明的制造半导体器件的方法的第一实例(实例1)的第一剖视图。
图1B为说明本发明的制造半导体器件的方法的第一实例(实例1)的第二剖视图。
图2A为示出在本发明的制造半导体器件的方法的第一实例(实例1)中，由有机绝缘层界定的开口尺寸A与将形成外部端子的开口尺寸B之间关系的实例的示意图。
图2B为示出在本发明的制造半导体器件的方法的第一实例(实例1)中，由有机绝缘层界定的开口尺寸A与光阻层中的开口尺寸C之间关系的实例的示意图。
图3为在本发明的制造半导体器件的方法的第一实例(实例1)中使用的凸点形成装置的实例的示意图。
图4A为说明本发明的制造半导体器件的方法的第一实例(实例1)的第三剖视图，示出在图1B所示的步骤之后进行的步骤。
图4B为说明本发明的制造半导体器件的方法的第一实例(实例1)的第四剖视图。
图4C为说明本发明的制造半导体器件的方法的第一实例(实例1)的第五剖视图。
图5为示出本发明的半导体器件的第一实例(实例1)的垂直剖视图。
图6为示出本发明的半导体器件的第二实例(实例2)的垂直剖视图。
图7为示出本发明的半导体器件的第三实例(实例3)的垂直剖视图。
图8为示出本发明的半导体器件的第四实例(实例4)的垂直剖视图。
图9为示出传统半导体器件的垂直剖视图。
具体实施方式
下面，参照实例描述本发明的半导体器件及本发明的制造半导体器件的方法，然而上述实例不应解释为限制本发明。
(实例1)
参照附图描述本发明的制造半导体器件的方法的第一实例。
根据特定的晶片处理，在由硅(Si)制成的半导体衬底(晶片)10的上表面(一个表面)上形成多个半导体器件。
然后，如图1A所示，在半导体器件上以如下方式有选择地形成无机绝缘层14：无机绝缘层14覆盖构成半导体器件外部端子的各个电极焊盘12的周边，而有选择地暴露外部端子的一部分。此外，在半导体器件上形成覆盖无机绝缘层14的上表面和侧表面的有机绝缘层16。
构成电极焊盘12的材料的实例包括主要由铝(Al)组成的材料(例如Al-Cu、Al-Si以及Al-Cu-Ti)和铜(Cu)，而电极焊盘12的厚度设定为大约0.5μm至2μm。
无机绝缘层14为由下层和上层构成的叠层，下层由二氧化硅(SiO2)制成，上层由氮化硅制成(SiN)，并且无机绝缘层14的厚度设定为大约300μm至800μm。
有机绝缘层16由聚酰亚胺树脂制成，并且有机绝缘层16的厚度设定为大约1μm至20μm。
通过设置这种有机绝缘层16，可以防止水通过无机绝缘层14与电极焊盘12之间留下的间隙侵入，并可以减少下文将描述的外部端子(凸点)上的机械应力。
接下来，在半导体器件上形成覆盖有机绝缘层16和暴露的电极焊盘12的光阻层，然后对光阻层进行选择性曝光和显影，从而形成在相应于电极焊盘12的位置具有开口18的光阻层20，如图1B所示。
光阻层20在以下描述的工艺中用作掩模层。在此工艺中，光阻层20的图案设计为使得有选择地覆盖电极焊盘12的有机绝缘层16的顶部的一部分暴露在开口中。即，光阻层20以使得电极焊盘12和有机绝缘层16均部分地暴露的方式设置在半导体器件上。更具体地，如果假定已经去除光阻层20，如图2A所示，外部端子(凸点)Mb以如下方式形成：为了在有机绝缘层16的表面上延伸，外部端子Mb的尺寸B大于由有机绝缘层16界定的开口尺寸A(即A<B)。此外，光阻层20的开口尺寸C大于开口尺寸A(即A<C)，如图2B所示。
注意：构成光阻层20的光阻材料可由正光阻材料或负光阻材料形成，并且可根据所需的图案精度，例如根据曝光光源(exposure light)的波长(例如g线、i线、或KrF)进行选择。可采用水溶性光阻材料或膜(片)型光阻材料。光阻层20的厚度设定为大约150μm。
使用凸点形成装置700(其示意结构在图3中示出)，在形成有掩模层的半导体衬底(晶片)10上形成外部端子(凸点)，其中该掩模层由光阻层20形成。
凸点形成装置700包括：第一处理腔71，用于去除出现在形成于半导体晶片10上的半导体器件中的各个电极焊盘12的暴露表面上的氧化物膜；第二处理腔72，用于将含有金属材料的、用于凸点的膏体(paste)填入由光阻层20界定的区域中；以及第三处理腔73，用于加热膏体。
晶片转移腔75中的转移臂(图中未示出)将半导体晶片10从一个腔转移到另一个腔或者从晶片设定腔74转移到某一个腔。凸点形成装置700保持在真空或者减压状态下，从而各个腔可适当地保持在真空或者减压状态下。
首先，将给定数目的半导体晶片10放置在凸点形成装置700的晶片设定腔74中，并将各个处理腔抽空以形成真空。
随后，通过转移臂，将置于晶片设定腔74中的一个半导体晶片10转移至第一处理腔(氧化物膜去除腔)71。在第一处理腔71中，去除出现在形成于半导体晶片10上的各个半导体器件的电极焊盘12的暴露表面上的氧化物膜。更具体地，如图4A所示，去除出现在由有机绝缘层16界定的开口18中的各个电极焊盘12的暴露表面上的氧化物膜42，从而使各个电极焊盘12的金属层表面暴露在开口18中。
氧化物膜42可通过清洗处理去除，在清洗处理中使用CHF3和O2的混合气体、CHF4和O2的混合气体、O2气体、或N2气体。此清洗处理优选在20℃至200℃的温度下且在0.5kW至2.0kW的输出功率下进行。
可选择地，氧化物膜42可通过使用氩(Ar)气或氮(N2)气的RF溅射方法、或者通过使用甲酸气体的还原处理来去除。
当采用RF溅射方法时，该方法优选在50℃至200℃的温度下且在0.5kW至2.0kW的输出功率下进行。同时，当采用还原处理时，该处理优选在20℃至200℃的温度下进行。
然后，在第一处理腔71中已去除开口18暴露出的电极焊盘12上的氧化物膜42的情况下，通过转移臂将半导体晶片10从第一处理腔71转移至第二处理腔(膏体填充腔)72。此时，凸点形成装置700保持在真空或减压状态下，并且各个腔适当地保持在真空或减压状态下，从而防止形成于半导体晶片10上的半导体器件的电极焊盘12表面氧化。
然后，在第二处理腔72中，将含金属材料的膏体填入由光阻层20界定的区域中，即将含金属材料的膏体放置在形成于半导体晶片10上的各个半导体器件的电极焊盘12的暴露表面上。更具体地，在真空或减压状态下，将由含金属粒子(粉末)的树脂制成的导电膏体44填入由光阻层20界定的区域中并与光阻层20的顶部高度平齐。这种状态在图4B中示出。
注意：由于第二处理腔72在填充导电膏体44时保持在真空或减压状态下，因此没有空气进入设置于电极焊盘12上且由有机绝缘层16界定的开口18中。因此，可以在不包含气泡(气孔)的情况下填充导电膏体。
用于金属粒子(粉末)的材料没有具体限制，并可根据特定目的而适当地选择。实例包括铜(Cu)、金(Au)、镍(Ni)、钯(Pd)、铂(Pt)、铟(In)、锗(Ge)、锑(Sb)及锌(Zn)。这些金属可单独使用或者组合使用，两种或更多种金属的混合物、这些金属的合金以及合金的混合物都可以使用。
同时，热固树脂(thermosetting resin)可用作上述树脂。然而，这些热固树脂需要在低于所用金属的熔点的温度下进行固化。为此，当使用铜(Cu，熔点：1083℃)时，采用环氧树脂。
除了热固树脂之外，也可以采用光固化树脂(photocurable resin)。
金属粒子(粉末)的含量没有具体限制，并可根据特定目的而适当地选定。例如，金属-树脂的质量比优选为95：5至70：30。
然后，在第二处理腔72中已将导电膏体44放置在开口18暴露出的电极焊盘12上的情况下，通过转移臂将半导体晶片10从第二处理腔72转移至第三处理腔(膏体固化腔)73。此时，凸点形成装置700保持在真空或减压状态下，并且各个腔适当地保持在真空或减压状态下。
在第三处理腔73中，在真空或减压状态下加热半导体晶片10以固化导电膏体44，从而形成外部端子(凸点)46。这种状态在图4C中示出。
在上述热处理期间，第三处理腔73保持在真空或减压状态下。为此，即使当气体已经从导电膏体44放出时，上述气体也不可能结合到外部端子(凸点)46中。
上述处理中的加热温度根据构成导电膏体44的树脂材料和该树脂材料所含的金属材料来确定。如果导电膏体44由上述的环氧树脂制成，则将其加热至大约200℃。
在本实例中，在形成于半导体晶片上的各个半导体器件的电极焊盘上形成外部端子时，如上所述，与去除出现在电极焊盘上的氧化物膜和在电极焊盘上形成外部端子(凸点)的工艺相关的清洗工艺均在真空或减压状态下进行。通过这种方式，为了形成外部端子(凸点)而设计的树脂膏体被放置在外部端子上，并覆盖外部端子。此时，在电极焊盘与树脂膏体之间既不会产生绝缘物质(例如氧化物膜)，也不会产生气孔，从而可在电极焊盘与外部端子(凸点)之间提供高粘附性并可确保电极焊盘与外部端子(凸点)之间的低阻电连接和高机械接合强度。
然后，在第三处理腔73中已经过热处理而在电极焊盘12上形成外部端子(凸点)46的半导体晶片10，通过转移臂从第三处理腔73转移至晶片设定腔74。
使晶片设定腔74的压强恢复到大气压之后，将半导体晶片10从晶片设定腔74中取出，并且通过用蚀刻剂如碱性溶剂溶解光阻层20或者通过将光阻层20从半导体晶片10上剥离，从而去除半导体晶片10上的光阻层20。通过这种方式，在半导体晶片10上形成多个独立且清晰的外部端子(凸点)46，各个外部端子46具有接近平坦的上表面。这种状态在图5中示出。
在具有排列在电极焊盘12上的外部端子(凸点)46的半导体器件100中，没有所谓的阻挡层形成在电极焊盘12与外部端子(凸点)46之间的界面处，如图5所示。这表明不需要制备用于这种阻挡层的材料及其形成工艺。此外，在电极焊盘12与外部端子(凸点)46之间可提供高粘附性，并可确保电极焊盘12与外部端子(凸点)46之间的低阻电连接和高机械接合强度。
如上文所述，要求半导体器件更小、更密集及性能更高的同时，半导体器件中外部端子(凸点)的数目趋于增加。因此，沿着半导体器件的横截面，各个外部端子(凸点)的水平尺寸B(参见图5)需要设定为100μm或更小，而且近来设定为10μm至30μm。此外，相邻外部端子(凸点)之间的距离，或者端子间距D(参见图5)需要设定为150μm或更小，而且近来设定为130μm或更小。
为此，本发明的半导体器件设计为使得外部端子(凸点)46具有基本上平行于电极焊盘12表面的平坦表面。因此，本发明的半导体器件的凸点46的高度(厚度)小于传统球形凸点的高度；从而可以减小半导体器件的尺寸并使半导体器件变薄。
注意：尽管本实例的半导体器件的外部端子(凸点)46如上所述，与光阻层20一样高(厚)，但外部端子(凸点)46的高度(厚度)不必一定与光阻层20的高度(厚度)相同；只需要外部端子(凸点)46的高度(厚度)至少为光阻层20的高度(厚度)的三分之二。
注意：可以对本发明的半导体器件进行多种修改，如下文描述的实例中所表明的。
(实例2)
本发明的半导体器件的第二实例在图6中示出。
在图6所示的半导体器件200中，有机绝缘层16以如下方式形成在无机绝缘层14上：有机绝缘层16没有覆盖无机绝缘层14的侧表面。更具体地，有机绝缘层16和无机绝缘层14具有相同的图案。
通过这种结构，界定开口(由此暴露电极焊盘12)的两个绝缘层(即有机绝缘层16和无机绝缘层14)的处理变得易于进行，并且也可以减小开口的尺寸。
外部端子(凸点)46接触电极焊盘12，而没有所谓的阻挡层位于外部端子(凸点)46与电极焊盘12之间，并且外部端子(凸点)46部分地延伸在无机绝缘层14的表面上。
此外，通过这种结构，可省略阻挡金属形成工艺，从而能够以低成本形成以凸点间距排列的精细的外部端子(凸点)。
(实例3)
本发明的半导体器件的第三实例在图7中示出。
在图7所示的半导体器件300中，有机绝缘层16以如下方式形成在无机绝缘层14上：有机绝缘层16没有覆盖无机绝缘层14的侧表面，并且有机绝缘层16的端部与各个外部端子(凸点)的侧表面接触。
通过这种结构，能够降低对处理有机绝缘层16的精度要求，同时能够以高精度处理无机绝缘层14，从而能够进一步减小开口的尺寸。
外部端子(凸点)46接触电极焊盘12，而没有所谓的阻挡层位于外部端子(凸点)46与电极焊盘12之间，并且外部端子(凸点)46部分地延伸在无机绝缘层14的表面上。
此外，通过这种结构，可省略阻挡金属形成工艺，从而能够以低成本形成以窄间距排列的精细的外部端子(凸点)。
(实例4)
本发明的半导体器件的第四实例在图8中示出。
在图8所示的半导体器件400中，保护层16A以如下方式有选择地形成在无机绝缘层14上：保护层16A没有覆盖无机绝缘层14的侧表面，并且保护层16A与外部端子(凸点)46分离。
由于保护层16A与外部端子(凸点)46分离，因此保护层16A的绝缘性可较低。
由于在制造过程中碳不适宜地进入无机绝缘层14的表面，因此无机绝缘层14的绝缘性降低，从而需要进行去除含碳部分的工艺。然而，如本实例中所表明的，通过在无机绝缘层14上以与外部端子(凸点)46分离的方式有选择地形成保护层16A，可省略这样的工艺。通过这种结构，也能够以高精度处理无机绝缘层14，从而易于减少开口的尺寸。
外部端子(凸点)46接触电极焊盘12，而没有所谓的阻挡层位于外部端子(凸点)46与电极焊盘12之间，并且外部端子(凸点)46部分地延伸在无机绝缘层14的表面上。
此外，通过这种结构，可省略阻挡金属形成工艺，从而能够以低成本形成以窄间距排列的精细的外部端子(凸点)。
此外，由于本实例的外部端子(凸点)46形成在无机绝缘层14上，它们的高度比实例1中外部端子(凸点)46的高度小对应于有机绝缘层16厚度的量。因此，可以制造更小的半导体器件。
根据本发明，可以解决上述传统问题，并可以提供一种成本低、易使用及效率高的制造半导体器件的方法及具有以窄间距排列的微凸点的高性能半导体器件，该制造半导体器件的方法使得在形成凸点时不需要形成或去除阻挡金属。
本发明的半导体器件具有以窄间距排列的微凸点并具有高性能。
本发明的制造半导体器件的方法使得不需要形成或去除阻挡金属，并能够廉价而高效地制造半导体器件。本发明的方法尤其适用于制造本发明的半导体器件。

Claims (12)

1.一种制造半导体器件的方法，包括如下步骤：
在半导体衬底的一个表面上形成多个电极焊盘；
形成覆盖在各个电极焊盘(12)的周边的绝缘层；
在该绝缘层上有选择地形成掩模层；
清洗所述电极焊盘的没有被绝缘层覆盖的表面；
在由该绝缘层和该掩模层界定的区域中形成外部端子，使其与所述电极焊盘接触；以及
去除掩模层。
2.如权利要求1所述的制造半导体器件的方法，其中清洗所述电极焊盘表面的步骤和形成所述外部端子的步骤是在真空或减压状态下进行的。
3.如权利要求2所述的制造半导体器件的方法，其中清洗所述电极焊盘表面的步骤和形成所述外部端子的步骤是在同一装置的不同腔中进行的。
4.如权利要求1所述的制造半导体器件的方法，其中在清洗所述电极焊盘表面的步骤中，通过选自灰化、RF溅射以及使用甲酸的回流的至少一种工艺，来去除形成于各个电极焊盘上的氧化物膜。
5.如权利要求1所述的制造半导体器件的方法，其中该掩模层由光阻层形成。
6.如权利要求5所述的制造半导体器件的方法，其中该掩模层是通过对光阻层进行选择性曝光和显影而形成。
7.如权利要求1所述的制造半导体器件的方法，其中形成外部端子的步骤是通过将金属和可固化树脂的混合物填入所述电极焊盘上方的由该绝缘层和该掩模层界定的区域而进行的，并且该可固化树脂为热固树脂和光固化树脂的至少其中之一。
8.如权利要求1所述的制造半导体器件的方法，其中所述外部端子形成为与该掩模层一样高。
9.如权利要求1所述的制造半导体器件的方法，其中所述外部端子的直径为100μm或更小。
10.如权利要求1所述的制造半导体器件的方法，其中相邻的外部端子之间的距离为150μm或更小。
11.一种半导体器件，包括：
多个电极焊盘，形成在半导体衬底的一个表面上；
绝缘层，覆盖在各个电极焊盘的周边；以及
外部端子，形成在所述电极焊盘上并与所述电极焊盘接触，所述外部端子具有平行于所述电极焊盘表面的平坦表面，形成在所述电极焊盘上的所述外部端子具有在所述绝缘层的表面延伸，并大于所述绝缘层界定的开口尺寸的尺寸，
其中相邻的外部端子之间的距离为150μm或更小。
12.如权利要求11所述的半导体器件，其中所述外部端子是由金属和可固化树脂的混合物形成，并且该可固化树脂为热固树脂和光固化树脂的至少其中之一。
CNB2006101000273A 2006-02-17 2006-06-28 半导体器件及其制造方法 Active CN100527373C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006040866A JP2007220959A (ja) 2006-02-17 2006-02-17 半導体装置及びその製造方法
JP2006040866 2006-02-17

Publications (2)

Publication Number Publication Date
CN101026109A CN101026109A (zh) 2007-08-29
CN100527373C true CN100527373C (zh) 2009-08-12

Family

ID=38428773

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101000273A Active CN100527373C (zh) 2006-02-17 2006-06-28 半导体器件及其制造方法

Country Status (5)

Country Link
US (1) US7871917B2 (zh)
JP (1) JP2007220959A (zh)
KR (1) KR100752106B1 (zh)
CN (1) CN100527373C (zh)
TW (1) TWI338343B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101675322B1 (ko) 2009-06-23 2016-11-14 삼성전자주식회사 다공성 산화막 속에 형성된 나노와이어 네트워크 단원계 상변화층을 갖는 상변화 메모리 및 형성 방법
TWI490992B (zh) * 2011-12-09 2015-07-01 Chipmos Technologies Inc 半導體結構
US10269747B2 (en) * 2012-10-25 2019-04-23 Taiwan Semiconductor Manufacturing Company Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
CN107204294A (zh) * 2016-03-18 2017-09-26 联芯科技有限公司 一种倒装焊芯片的制作方法及裸芯片组件
JP2020047775A (ja) * 2018-09-19 2020-03-26 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置
US11423526B2 (en) * 2020-11-13 2022-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Optical inspection of a wafer

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214141A (ja) * 1988-02-23 1989-08-28 Nec Corp フリップチップ型半導体装置
JPH02267941A (ja) * 1989-04-07 1990-11-01 Citizen Watch Co Ltd 突起電極の形成方法
JPH08162456A (ja) 1994-12-07 1996-06-21 Kawasaki Steel Corp バンプの製造方法
JPH08330308A (ja) * 1995-05-31 1996-12-13 Matsushita Electric Ind Co Ltd バンプの形成方法
JPH11260863A (ja) * 1998-03-09 1999-09-24 Sumitomo Electric Ind Ltd 半導体装置用接続端子とその製造方法
US6108210A (en) * 1998-04-24 2000-08-22 Amerasia International Technology, Inc. Flip chip devices with flexible conductive adhesive
JP3449535B2 (ja) 1999-04-22 2003-09-22 ソニー株式会社 半導体素子の製造方法
US6277249B1 (en) * 2000-01-21 2001-08-21 Applied Materials Inc. Integrated process for copper via filling using a magnetron and target producing highly energetic ions
JP2002111192A (ja) 2000-10-04 2002-04-12 Ibiden Co Ltd 半田バンプ形成方法および半田バンプ形成装置
JP4638614B2 (ja) 2001-02-05 2011-02-23 大日本印刷株式会社 半導体装置の作製方法
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
JP3615206B2 (ja) * 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
JP4025322B2 (ja) * 2001-11-15 2007-12-19 富士通株式会社 半導体装置の製造方法
US6593220B1 (en) * 2002-01-03 2003-07-15 Taiwan Semiconductor Manufacturing Company Elastomer plating mask sealed wafer level package method
JP4270792B2 (ja) * 2002-01-23 2009-06-03 富士通株式会社 導電性材料及びビアホールの充填方法
JP2004103928A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 基板及びハンダボールの形成方法及びその実装構造
JP2004128354A (ja) 2002-10-04 2004-04-22 Fujitsu Ltd はんだバンプの形成方法
US7485962B2 (en) * 2002-12-10 2009-02-03 Fujitsu Limited Semiconductor device, wiring substrate forming method, and substrate processing apparatus
JP2004214345A (ja) 2002-12-27 2004-07-29 Renesas Technology Corp 半導体装置およびその製造方法
US6784089B2 (en) * 2003-01-13 2004-08-31 Aptos Corporation Flat-top bumping structure and preparation method
CN1291069C (zh) * 2003-05-31 2006-12-20 香港科技大学 微细间距倒装焊凸点电镀制备方法
KR100581279B1 (ko) * 2003-06-02 2006-05-17 삼성전자주식회사 포토레지스트 제거용 조성물 및 이를 이용한 반도체소자의 범프 형성방법
JP4130668B2 (ja) * 2004-08-05 2008-08-06 富士通株式会社 基体の加工方法
JP2006222232A (ja) * 2005-02-09 2006-08-24 Fujitsu Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
TWI338343B (en) 2011-03-01
TW200733269A (en) 2007-09-01
US7871917B2 (en) 2011-01-18
US20070197016A1 (en) 2007-08-23
CN101026109A (zh) 2007-08-29
KR100752106B1 (ko) 2007-08-29
KR20070082834A (ko) 2007-08-22
JP2007220959A (ja) 2007-08-30

Similar Documents

Publication Publication Date Title
US7800233B2 (en) Semiconductor device and method of manufacturing the same
JP4850392B2 (ja) 半導体装置の製造方法
US6221751B1 (en) Wafer fabrication of die-bottom contacts for electronic devices
JP4307284B2 (ja) 半導体装置の製造方法
KR100646722B1 (ko) 반도체 장치 및 그 제조 방법
US8039962B2 (en) Semiconductor chip, method of fabricating the same and stack package having the same
JP3684978B2 (ja) 半導体装置およびその製造方法ならびに電子機器
CN100527373C (zh) 半导体器件及其制造方法
US20030230805A1 (en) Semiconductor device and manufacturing method thereof
CN102652358B (zh) 基于面板的引线框封装方法和装置
JP2006128172A (ja) 半導体装置及びその製造方法
US8174044B2 (en) Light emitting diode package and method for forming the same
JP2006032699A (ja) 半導体装置の製造方法
KR20060132490A (ko) 관통 전극을 갖는 반도체 장치 및 그 제조 방법
CN1574324A (zh) 半导体装置及其制造方法
US7492045B2 (en) Semiconductor module, method for manufacturing semiconductor modules and mobile device
JP3524441B2 (ja) 配線形成方法
US20060145340A1 (en) Substrate and method for fabricating the same
JP4215571B2 (ja) 半導体装置の製造方法
KR101626536B1 (ko) 반도체 패키지 및 그 제조 방법
KR100923501B1 (ko) 패키지 기판 제조방법
JP4544902B2 (ja) 半導体装置及びその製造方法
JP2006066803A (ja) 半導体装置及びその製造方法
US7378345B2 (en) Metal electroplating process of an electrically connecting pad structure of circuit board and structure thereof
JP2002270711A (ja) 半導体装置用配線基板およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: FUJITSU MICROELECTRONICS CO., LTD.

Free format text: FORMER OWNER: FUJITSU LIMITED

Effective date: 20081107

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20081107

Address after: Tokyo, Japan

Applicant after: FUJITSU MICROELECTRONICS Ltd.

Address before: Kawasaki, Kanagawa, Japan

Applicant before: Fujitsu Ltd.

C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: FUJITSU SEMICONDUCTOR CO., LTD.

Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD.

CP01 Change in the name or title of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Japan's Kanagawa Prefecture Yokohama

Patentee before: Fujitsu Microelectronics Ltd.

CP02 Change in the address of a patent holder

Address after: Japan's Kanagawa Prefecture Yokohama

Patentee after: FUJITSU MICROELECTRONICS Ltd.

Address before: Tokyo, Japan

Patentee before: Fujitsu Microelectronics Ltd.

ASS Succession or assignment of patent right

Owner name: SUOSI FUTURE CO., LTD.

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD.

Effective date: 20150526

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150526

Address after: Kanagawa

Patentee after: SOCIONEXT Inc.

Address before: Japan's Kanagawa Prefecture Yokohama

Patentee before: FUJITSU MICROELECTRONICS Ltd.