CN100470745C - 晶片贴板封装及其制造方法 - Google Patents

晶片贴板封装及其制造方法 Download PDF

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CN100470745C
CN100470745C CNB2007100873116A CN200710087311A CN100470745C CN 100470745 C CN100470745 C CN 100470745C CN B2007100873116 A CNB2007100873116 A CN B2007100873116A CN 200710087311 A CN200710087311 A CN 200710087311A CN 100470745 C CN100470745 C CN 100470745C
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film
ball pad
solder ball
circuitry lines
semiconductor chip
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CN101034674A (zh
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姜明杉
柳彰燮
朴正现
郑会枸
金智恩
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明一个方面的特征在于晶片贴板封装的制造方法。该方法可包括：(a)将干膜层压在载体膜上，所述载体膜的一侧层压有薄金属膜；(b)通过曝光和显影处理根据电路线使干膜形成图案，并形成焊球盘和电路线；(c)去除干膜；(d)在除形成有焊球盘的部分以外的部分层压上部光致成像阻焊剂；(e)蚀刻形成在未层压上部光致成像阻焊剂的部分上的薄金属膜；(f)通过倒装焊接将半导体芯片安装在焊球盘上；(g)用钝化材料模制半导体芯片；(h)去除载体膜和薄金属膜；以及(i)将下部光致成像阻焊剂层压在焊球盘的下面。由于使用晶种层形成电路图案，因此根据本发明的晶片贴板封装及其制造方法可设计高密度电路。

Description

晶片贴板封装及其制造方法
相关申请交叉参考
本申请要求于2006年3月10日向韩国知识产权局提交的韩国专利申请第10-2006-0022844号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及半导体芯片封装及其制造方法，更具体地，涉及晶片贴板(board on chip)封装及其制造方法。
背景技术
由于电子设备变得越来越小，因此需要高性能的小型半导体芯片封装。因此，广泛使用的是具有分层堆叠或水平地排列在平面上的多个半导体芯片的多芯片封装，或将半导体芯片直接组合于基板上并密封它们的晶片贴板封装。
与借助于引线框架将半导体芯片安装于基板上的传统半导体芯片封装不同，晶片贴板(BoC)将其自身的承受模直接安装在基板上，减少由于DRAM的高速导致的热损失和电子损失。因此，晶片贴板作为适于高速DRAM(例如DDR2)的下一代高速半导体基板而受到关注。DRAM的容量从128MB迅速增加至256MB、512MB、1GB、2GB等，因此，为了减少电子损失并确保可靠性，基板应更薄。
传统晶片贴板封装在基板的中心具有孔以便于与半导体芯片相连接，并且该结构被设计成通过缩短信号行进的距离来使存储器加速。
图1是根据现有技术的晶片贴板封装的截面图。参考图1，具体表现为球栅阵列封装的传统晶片贴板封装包括电路基板110和半导体芯片120。电路基板110和半导体芯片120通过焊接线130电连接，该焊接线的一端与形成在半导体芯片120一侧上的焊盘140相结合，其另一端与形成在电路基板110上的焊点150相结合。这里，焊接线130涂覆有模制树脂160，并且多个焊球170形成在电路基板110的一侧上以使得晶片贴板封装可与外部装置(未示出)电连接。简单地说，在未在基板中形成通孔的情况下，传统晶片贴板通过焊接线传输电信号。由于具有最小化的长度，因此这样一种焊接线阻碍基板变得更薄。因此传统的晶片贴板结构不适于具有大容量的存储器(例如DRAM)。
发明内容
本发明的特征在于，一种晶片贴板封装及其制造方法，所述晶片贴板封装及其制造方法可应付迅速增加的存储器的速度和容量。
本发明提供了一种晶片贴板封装及其制造方法，所述晶片贴板封装及其制造方法不需要用于形成封装的内插器(interposer)以及不需要用于形成用于安装半导体芯片的空腔的独立程序，从而降低了制造成本。
另外，本发明提供了一种晶片贴板封装及其制造方法，由于半导体芯片通过倒装法安装在基板上，因此所述晶片贴板封装及其制造方法不需要导线。
而且，本发明提供了一种晶片贴板封装及其制造方法，由于使用晶种层形成电路图案，因此所述晶片贴板封装及其制造方法可设计高密度电路。
本发明一个方面的特征在于，一种晶片贴板封装的制造方法。该方法可包括：(a)将干膜层压在载体膜上，所述载体膜的一侧层压有薄金属膜；(b)通过曝光和显影处理根据电路线对干膜形成图案，并形成焊球盘和电路线；(c)去除干膜；(d)在除形成有焊球盘的部分以外的部分层压上部光致成像阻焊剂(photo solder resist)；(e)蚀刻形成在未层压上部光致成像阻焊剂的部分上的薄金属膜；(f)通过倒装焊接将半导体芯片安装在焊球盘上；(g)用钝化材料模制半导体芯片；(h)去除载体膜和薄金属膜；以及(i)将下部光致成像阻焊剂层压在焊球盘的下面。
载体膜可为绝缘层，薄金属膜可用铜制成。
载体膜可用铜(Cu)制成，而薄金属膜可用镍(Ni)制成，其中载体膜的厚度可在30μm与40μm之间。
所述方法可进一步包括通过涂覆锡(Sn)而对焊球盘进行表面处理以及在电路线上层压有机化合物。
或者，所述方法可包括：(a)将第一干膜层压在载体膜上，所述载体膜的一侧层压有薄金属膜；(b)通过曝光和显影处理根据电路线对第一干膜形成图案，并形成焊球盘和电路线；(c)去除第一干膜；(d)在除形成有焊球盘的部分以外的部分层压第二干膜；(e)蚀刻形成在未层压第二干膜的部分上的薄金属膜；(f)通过涂覆锡(Sn)而对焊球盘进行表面处理；(g)去除第二干膜；(h)通过倒装焊接将半导体芯片安装在焊球盘上；(i)用钝化材料模制半导体芯片；(j)去除载体膜和薄金属膜；以及(k)将光致成像阻焊剂层压在焊球盘的下面。
载体膜可为绝缘层，薄金属膜可用铜制成。
载体膜可用铜(Cu)制成，而薄金属膜可用镍(Ni)制成，其中载体膜的厚度可在30μm与40μm之间。
所述方法可进一步包括在电路线上层压有机化合物。
本发明的另一个方面的特征在于一种晶片贴板封装。该封装可包括：在一侧上具有空腔和图案的光致成像阻焊剂，所述图案与电路线相对应；容纳在空腔中的焊球盘；电路线，该电路线与焊球盘电连接，并形成在光致成像阻焊剂的另一侧上；通过倒装焊接安装在焊球盘上的半导体芯片；以及用于模制半导体芯片的钝化材料。
或者，该封装可包括：具有区域和图案的光致成像阻焊剂，半导体芯片安装在该区域上，所述图案根据电路线而形成；形成在光致成像阻焊剂一侧中并具有图案的电路线；形成在光致成像阻焊剂一侧上并与电路线电连接的焊球盘；通过倒装焊接安装在焊球盘上的半导体芯片；以及用于模制半导体芯片的钝化材料。
在以下描述中将部分地阐述本发明总发明构思的其它方面和优点，本发明总发明构思的其它方面和优点可从所述描述中部分地显而易见，或者可通过本发明总发明构思的实践而获知。
附图说明
结合以下描述、所附权利要求、以及附图将更好地理解本发明的这些和其它特征、方面、和优点，在附图中：
图1是根据现有技术的晶片贴板封装的截面图；
图2是根据本发明一个实施例的晶片贴板封装的截面图；
图3和图4示出了根据本发明第一实施例的晶片贴板封装的制造方法；
图5和图6示出了根据本发明第二实施例的晶片贴板封装的制造方法；以及
图7和图8示出了根据本发明第三实施例的晶片贴板封装的制造方法。
具体实施方式
在下文中，将参照附图详细描述本发明的实施例。在参照附图的描述中，不管图序号为多少，那些相同或相应的部件用相同的参考标号表示，并且省略了重复的解释。
另外，在描述本发明的实施例之前，首先将描述用于制造普通基板的方法。尽管下面描述了用于制造多层基板的方法，但是本发明决不局限于用于制造多层基板的以下方法。
首先，内部电路图案被形成在芯层的外侧上。切割满足产品规格的内层基材，并且使用干膜和加工膜(working film)形成预定的内部电路图案。这里，内层可被擦洗，内层干膜可被层压，并且内层可被曝光和显影。
之后，在将其上形成有电路图案的内层结合于外层之前，进行棕色(黑色)氧化处理以加固附着力。也就是说，铜箔的表面被化学氧化以增强表面粗糙度，从而使得层压产生更好的附着力。接着，通过层压内层基板和预浸料，进行预层压和层压处理。
之后，对层压的内层基板和预浸料进行真空压制。取代真空压制，还可对层压的内层基板和预浸料进行热压或冷压。
从面板的角落中裁出树脂和铜箔，并在钻孔处理的准备中进行X射线目标钻孔处理，在该处理中，在内层电路上的目标标记处形成孔。
之后，进行钻孔处理以实现基板的层之间的导电。这里，计算机数控(CNC)方法可用于钻孔处理。
接着，外层被覆以干膜和加工膜以形成电路图案，并将其暴露于预定强度的光线下预定持续时间，且在蚀刻处理中显影未受照射的部分。在检查了外层并测量了刻度之后，设计并制造出阻焊剂曝光膜(exposure film)。之后，进行诸如刷光(brush polishing)的预处理，在该预处理中，铜箔的表面被制造成粗糙的以使阻焊剂油墨更好地附着于基板。之后涂覆阻焊剂；使用在前述处理中适当设计的阻焊剂曝光膜曝光阻焊剂；在显影处理中去除阻焊剂；以及进行包括电/最终测试的各种后处理。
图2是根据本发明实施例的晶片贴板(芯片贴板)封装的截面图。参考图2，根据本发明的晶片贴板封装包括光致成像阻焊剂210、半导体芯片220、隆起(bump)230(1)和230(2)、焊料块(solderlump)233(1)和233(2)、焊球盘240(1)和240(2)、钝化材料250、以及焊球260。半导体芯片220是能够进行高速信号处理的集成芯片，并通过倒装法安装在光致成像阻焊剂210中所形成的空腔中。接着，隆起230(1)和230(2)直接电连接于焊球盘240(1)和240(2)，其中焊球盘240(1)和240(2)容纳在光致成像阻焊剂210中形成的空腔中。这里，在光致成像阻焊剂210的一侧上形成有空腔和与电路线相对应的图案。焊球盘240(1)和240(2)与电路线电连接，允许半导体芯片220与电路线交换(communicate)信号。另外，半导体芯片220通过倒装法直接安装在光致成像阻焊剂210上，因此封装的总厚度足够薄，不需要内插器以在光致成像阻焊剂210与半导体芯片220顶部上形成的基板(未示出)之间形成空间。
钝化材料250是模制树脂(诸如环氧树脂)，被形成在半导体芯片220的四侧上，以保护半导体芯片220免受电的和化学的外部因素的侵害。隆起230(1)和230(2)可为金(Au)隆起、焊料隆起等，焊球盘240(1)和240(2)可由诸如金(Au)或铜(Cu)的导电金属制成。下面描述的隆起和焊盘是由如上所述相同材料制成的。
焊料块(solder lump)233(1)和233(2)将隆起230(1)和230(2)与焊球盘240(1)和240(2)结合在一起。为了结合晶片贴板封装与外部装置，焊球260电结合于晶片贴板封装中形成的电路线。这里，焊球盘240(1)和240(2)的表面由诸如锡的材料处理以防止氧化。另外，可以以各种方式对与焊球260相结合的电路线进行表面处理以防止氧化。防氧化的表面处理可为热空气焊锡均涂(HASL)、化学镀金、有机可焊性保护剂(OSP)镀、化学镀锡、化学抗原镀(electroless antigen plating)、镀钯等。OSP镀通过在印刷电路板上涂覆有机化合物保护铜表面免受空气侵蚀，以防止氧化。由于有机化合物近似于焊剂，因此OSP镀也被称作预焊剂处理。如果有机化合物未被平均地涂覆于印刷电路板焊盘的表面上的话，铜膜可被氧化，在执行双面回流焊接时会出现问题。因此，在打开真空包装时要求迅速的处理。
以上描述集中在晶片贴板封装上。在下文中，将参照附图描述根据本发明的晶片贴板封装的制造方法。该制造方法介绍了三个实施例，下面将逐一描述。
图3和图4示出了根据本发明第一实施例的晶片贴板封装的制造方法。
参考步骤(a)，将干膜315(1)和315(2)层压在载体膜305上，在所述载体膜的一侧上层压有薄金属膜310。薄金属膜310可通过化学镀层压在载体膜305上。薄金属膜310可由铜构成，且薄金属膜310的厚度可为3μm或更小。
为了形成电路线，在将干膜315(1)和315(2)层压在载体膜305上之后，通过曝光和显影处理形成图案，并通过半加成法或改进的半加成法来电镀所述图案。
在通过化学镀形成铜(Cu)晶种层之后，半加成法使用不具有晶种层的材料形成电路图案。也就是说，抗电镀层用在铜箔(该铜箔位于敷铜箔层压板的外层上)的表面上，并且将形成电路的部分中的抗电镀层通过曝光和显影处理被剥离。因此，外层铜箔的表面露出，并且只有未形成电路的部分的抗电镀层保留在铜箔的外层上。通过在表面上镀铜，抗电镀层被剥离以便于在露出的外层铜箔的表面上形成镀铜电路层，从而形成电路图案。在完成电镀之后，剩余的抗电镀层被剥离，并使用齐平蚀刻(flush etching)溶解所形成电路中的布线之间的铜箔，从而完成印刷电路板。当通过齐平蚀刻去除铜箔层时，镀铜电路层的上部边缘也变为有蚀痕的，这破坏了最后的印刷电路板的形状以及电路的横截面的纵横比。为了避免这种情况，也可进行以下处理：在半加成法中，镀铜电路层和外层铜箔层必须具有1.0或更高的Rv值(其为Vsc/Vsp)，Vsp是构成镀铜电路层的析出的铜的溶解速度，而Vsc是构成外层铜箔层的铜的溶解速度。改进的半加成法使用从一开始其上就层压有铜的材料(即，具有晶种层的材料)形成电路图案。该方法的其余部分与上述半加成法相同。以下描述的是通过改进的半加成法制造晶片贴板封装的方法。
参考步骤(b)，通过执行曝光和显影处理，从待形成电路线的区域中去除干膜315(1)和315(2)，因此形成与电路线一致的图案。
参考步骤(c)，通过图案电镀处理形成电路线320(3)。该处理形成微电路线和焊球盘320(1)和320(2)，半导体芯片将安装于其上。
参考步骤(d)，在图案电镀处理之后，从未形成有电路的区域中去除干膜315(1)和315(2)。
参考步骤(e)，在去除干膜315(1)和315(2)之后，光致成像阻焊剂325被层压以保护电路的表面。在上述步骤中层压的光致成像阻焊剂325被称作上部光致成像阻焊剂，而在随后的步骤中层压的光致成像阻焊剂325被称作下部光致成像阻焊剂。这里，上部光致成像阻焊剂325未层压在将形成焊球盘320(1)和320(2)的区域上，以便使得半导体芯片可安装于其上。
参考步骤(f)和(g)，在层压上部光致成像阻焊剂325之后，从形成有焊球盘320(1)和320(2)的区域中蚀刻掉用作晶种层的薄金属膜310，并对焊球盘320(1)和320(2)的表面进行处理以防止氧化。之后，为了安装半导体芯片，基板被切割成条状，并在焊球盘320(1)和320(2)的表面上形成焊料块333(1)和333(2)。
参考步骤(h)，通过倒装法安装半导体芯片335，并且模制钝化材料345(例如，环氧树脂)以保护半导体芯片335。这里，形成在半导体芯片335上的隆起340(1)和340(2)分别与焊球盘320(1)和320(2)相连。
参考步骤(i)，在安装半导体芯片335并去除载体膜305之后，从形成有电路的区域中去除用作晶种层的薄金属膜310。之后，为了将根据本发明的晶片贴板封装安装在外部装置中，用OSP(有机可焊保护剂)法对电路线320(3)的表面进行表面处理，并以与电路线320(3)图案相对应的方式层压下部光致成像阻焊剂350使得电路线320(3)不会被覆盖。
载体膜305可为绝缘层，并且载体膜305与干膜315(1)和315(2)可通过碱性化合物(Na2CO3、K2CO3、NaOH、或KOH)被显影或被去除。
图5和图6示出了根据本发明第二实施例的晶片贴板封装的制造方法。下面的描述着重于与第一实施例的差异上。
图5和图6示出了载体膜505、薄金属膜510、干膜515(1)和515(2)、焊球盘520(1)和520(2)、上部光致成像阻焊剂325、锡530(1)和530(2)、焊料块533(1)和533(2)、半导体芯片535、形成在半导体芯片535上的隆起540(1)和540(2)、钝化材料545、以及下部光致成像阻焊剂550。
参考步骤(a)，载体膜505可由厚铜制成以便容易处理。这里，铜的厚度可在30μm至40μm之间，优选为35μm。这里，除铜以外的材料可用作晶种层以便于选择性地蚀刻载体膜505。所述材料的实例包括镍(Ni)和铝(Al)。
图7和图8示出了根据本发明第三实施例的晶片贴板封装的制造方法。下面的描述着重于与第二实施例的差异上。图7和图8示出了载体膜605、薄金属膜610、第一干膜615(1)和615(2)、焊球盘620(1)和620(2)、电路线620(3)、第二干膜625、锡630(1)和630(2)、焊料块633(1)和633(2)、半导体芯片635、形成在半导体芯片635上的隆起640(1)和640(2)、钝化材料、以及下部光致成像阻焊剂650。
参考步骤(f)，取代上部光致成像阻焊剂，干膜被层压。在步骤(f)层压的干膜被称作第二干膜625，在步骤(b)层压的干膜被称作第一干膜615(1)和615(2)。这里，由于干膜比光致成像阻焊剂更便宜，因此层压第二干膜625可降低成本。
在步骤(j)，当半导体芯片635被安装时去除第二干膜625，并且在步骤(k)，下部光致成像阻焊剂650被层压以保护电路线620(3)。形成在根据本发明第三实施例的晶片贴板封装中的下部成像阻焊剂650具有这样一个区域，在该区域中半导体芯片635通过倒装法被安装，并根据电路线620(3)被形成图案。也就是说，下部光致成像阻焊剂650形成在除电路线620(3)通过焊球与外部装置相结合的部分以外的晶片贴板封装的一侧上，以便于保护晶片贴板封装免受电的和化学的外部因素的侵害。
这里，焊球盘620(1)和620(2)形成在安装有半导体芯片635的部分中。并且，电路线620(3)在下部光致成像阻焊剂650的一侧上被形成图案。因而，焊球盘620(1)和620(2)与电路线620(3)形成在下部光致成像阻焊剂650的同一侧上。
虽然已结合所公开的实施例描述了本发明，但是应该理解的是，在不脱离下面权利要求中所述的本发明范围和精神或其等同物的前提下，本领域中普通技术人员可改变或修正这些实施例。

Claims (13)

1.一种制造晶片贴板封装的方法，所述方法包括：
(a)将干膜层压在载体膜上，在层压所述干膜之前，所述载体膜的一侧层压有薄金属膜；
(b)通过曝光和显影处理根据电路线使所述干膜形成图案，并形成焊球盘和所述电路线；
(c)去除所述干膜；
(d)在除形成有所述焊球盘的部分以外的部分层压上部光致成像阻焊剂；
(e)蚀刻形成在未层压所述上部光致成像阻焊剂的部分上的薄金属膜；
(f)通过倒装焊接将半导体芯片安装在所述焊球盘上；
(g)用钝化材料模制所述半导体芯片；
(h)去除所述载体膜并且去除除所述电路线区域之外的所述薄金属膜；以及
(i)以与所述电路线区域相对应的方式层压下部光致成像阻焊剂使得所述电路线不会被覆盖。
2.根据权利要求1所述的方法，还包括(j)在所述(f)之前通过涂覆锡而对所述焊球盘进行表面处理。
3.根据权利要求1所述的方法，还包括在所述电路线上层压有机化合物。
4.根据权利要求1所述的方法，其中，所述载体膜为绝缘层，所述薄金属膜用铜制成。
5.根据权利要求1所述的方法，其中，所述载体膜用铜制成，而所述薄金属膜用镍制成。
6.根据权利要求5所述的方法，其中，所述载体膜的厚度在30μm与40μm之间。
7.一种制造晶片贴板封装的方法，所述方法包括：
(a)将第一干膜层压在载体膜上，在层压所述第一干膜之前，所述载体膜的一侧层压有薄金属膜；
(b)通过曝光和显影处理根据电路线使所述第一干膜形成图案，并形成焊球盘和所述电路线；
(c)去除所述第一干膜；
(d)在除形成有所述焊球盘的部分以外的部分层压第二干膜；
(e)蚀刻形成在未层压所述第二干膜的部分上的薄金属膜；
(f)通过涂覆锡而对所述焊球盘进行表面处理；
(g)去除所述第二干膜；
(h)通过倒装焊接将半导体芯片安装在所述焊球盘上；
(i)用钝化材料模制所述半导体芯片；
(j)去除所述载体膜并且去除除所述电路线区域之外的所述薄金属膜；以及
(k)以与所述电路线区域相对应的方式层压下部光致成像阻焊剂使得所述电路线不会被覆盖。
8.根据权利要求7所述的方法，还包括在所述电路线上层压有机化合物。
9.根据权利要求7所述的方法，其中，所述载体膜为绝缘层，所述薄金属膜用铜制成。
10.根据权利要求7所述的方法，其中，所述载体膜用铜制成，而所述薄金属膜用镍制成。
11.根据权利要求10所述的方法，其中，所述载体膜的厚度在30μm与40μm之间。
12.一种晶片贴板封装，包括：
在一侧上具有凹槽并且在另一侧上具有图案的光致成像阻焊剂，所述图案与电路线相对应；
容纳在所述凹槽中的焊球盘；
电路线，与所述焊球盘电连接，并形成在所述光致成像阻焊剂的另一侧上；
通过倒装焊接安装在所述焊球盘上的半导体芯片；以及
用于模制所述半导体芯片的钝化材料。
13.一种晶片贴板封装，包括：
具有区域和图案的光致成像阻焊剂，半导体芯片安装在所述区域上，所述图案根据电路线而形成；
形成在所述光致成像阻焊剂一侧中的电路线；
形成在所述光致成像阻焊剂一侧上并与所述电路线电连接的焊球盘；
通过倒装焊接安装在所述焊球盘上的半导体芯片；以及
用于模制所述半导体芯片的钝化材料。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687860B2 (en) 2005-06-24 2010-03-30 Samsung Electronics Co., Ltd. Semiconductor device including impurity regions having different cross-sectional shapes
TWI367555B (en) * 2007-03-21 2012-07-01 Advanced Semiconductor Eng Conversion substrate for leadframe and the method for making the same
KR100924554B1 (ko) * 2007-11-30 2009-11-02 주식회사 하이닉스반도체 플립 칩 패키지 및 이의 제조 방법
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
KR101479506B1 (ko) 2008-06-30 2015-01-07 삼성전자주식회사 임베디드 배선 기판, 이를 포함하는 반도체 패키지 및 그제조 방법
KR101019161B1 (ko) * 2008-12-11 2011-03-04 삼성전기주식회사 패키지 기판
KR101047139B1 (ko) * 2009-11-11 2011-07-07 삼성전기주식회사 단층 보드온칩 패키지 기판 및 그 제조방법
KR101140978B1 (ko) * 2010-08-20 2012-05-03 삼성전기주식회사 인쇄회로기판의 제조방법
KR101213029B1 (ko) * 2010-12-09 2012-12-18 (주) 윈팩 반도체 패키지
DE102011000866A1 (de) * 2011-02-22 2012-08-23 Friedrich-Alexander-Universität Erlangen-Nürnberg Elektrisches Bauelement mit einer elektrischen Verbindungsanordnung und Verfahren zu dessen Herstellung
US8569808B1 (en) * 2012-04-06 2013-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Temperature stabilitized MEMS
US9721880B2 (en) * 2015-12-15 2017-08-01 Intel Corporation Integrated circuit package structures
US9646943B1 (en) 2015-12-31 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Connector structure and method of forming same
CN114364157B (zh) * 2021-12-23 2023-11-10 广东德赛矽镨技术有限公司 一种带双面焊接焊盘的pcb的贴片及封装方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP4480108B2 (ja) * 2000-06-02 2010-06-16 大日本印刷株式会社 半導体装置の作製方法
JP4683769B2 (ja) * 2001-05-31 2011-05-18 三井金属鉱業株式会社 銅メッキ回路層付銅張積層板及びその銅メッキ回路層付銅張積層板を用いたプリント配線板の製造方法
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
JP4056854B2 (ja) * 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
KR100536315B1 (ko) * 2004-01-02 2005-12-12 삼성전기주식회사 반도체 패키지 기판 및 그 제조 방법
US7009286B1 (en) * 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
KR100617585B1 (ko) * 2004-01-28 2006-09-01 주식회사 뉴프렉스 연성 인쇄회로기판의 제조방법
TWI260060B (en) * 2005-01-21 2006-08-11 Phoenix Prec Technology Corp Chip electrical connection structure and fabrication method thereof
US7339278B2 (en) * 2005-09-29 2008-03-04 United Test And Assembly Center Ltd. Cavity chip package
JP2008016508A (ja) * 2006-07-03 2008-01-24 Nec Electronics Corp 半導体装置およびその製造方法
KR101486420B1 (ko) * 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법

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