CN100481357C - 制造具有凹腔的基板的方法 - Google Patents

制造具有凹腔的基板的方法 Download PDF

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CN100481357C
CN100481357C CNB2007100793501A CN200710079350A CN100481357C CN 100481357 C CN100481357 C CN 100481357C CN B2007100793501 A CNB2007100793501 A CN B2007100793501A CN 200710079350 A CN200710079350 A CN 200710079350A CN 100481357 C CN100481357 C CN 100481357C
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layer
circuit
cavity
seed layer
crystal seed
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CN101026099A (zh
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郑会枸
姜明杉
金智恩
朴正现
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Abstract

本发明一个方面的特征是用于制造具有凹腔的基板的方法。该方法可包括：(a)在上部晶种层上形成上层电路；(b)将干膜层压在上部晶种层的其中将形成有凹腔的部分上；(c)通过在上部晶种层的顶部上以及上层电路的顶部和侧部上形成绝缘层而制造上部外层；(d)将上部外层堆叠在形成有内部电路的芯层的一侧上；(e)去除上部晶种层；以及(f)通过去除干膜而形成凹腔。根据本发明用于制造具有凹腔的基板的方法，可在绝缘层的厚度保持不变的同时，通过在外部电路的侧部上形成绝缘层而减小基板的总厚度。

Description

制造具有凹腔的基板的方法
相关申请交叉参考
本申请要求于2006年2月16日向韩国知识产权局提交的韩国专利申请第10-2006-0014918号的权益，其全部内容结合于此作为参考。
技术领域
本发明涉及一种堆叠型半导体封装组件，更具体地说，涉及一种用于制造其上形成有凹腔的基板的方法。
背景技术
随着电子工业的发展，对于更好地运行和更小型化的电子部件的需求日益增加。为了适应这些需求，半导体封装技术已从在一个基板上封装一个集成电路发展为在一个基板上封装几个集成电路。而且，为了达到实现高性能、高密度封装的需要，以及为了满足这些封装的要求，已引入了“层叠封装(POP)”技术。然而，使得封装的厚度最小化已成为成功地实施POP技术所需征服的挑战。
图1是根据现有技术的层叠封装件的剖视图。图1示出了下部封装110、上部封装120、上部焊球130以及下部焊球140。
传统球栅阵列(BGA)半导体封装件具有基板主体，其中安装有多个图案化的导线。在基板主体的顶部上是多个芯片焊盘，半导体芯片丝焊于其上。另外，基板主体顶部的一些部分由环氧化合物模制而成并形成模制部分，以使得半导体芯片和金属线被包封。多个焊球粘附于基板的底部以使得安装于基板中的导线的另一端可被连接。传统球栅阵列半导体封装件的这种结构太厚以致于无法在有限部分内堆叠成为高集成存储组件。
传统层叠封装件的下部封装件110具有双级结构，并且集成电路安装在该基板的表面上。下部封装件110的基板通过与制造普通印刷电路板相同的方法制造。半导体封装组件中增加的密度使得安装多个集成电路成为必要的。通过传统方法，难以在保持层叠封装件总厚度的同时增加下部封装件110中的安装。减小半导体芯片厚度的晶片减薄方法可用作减小厚度的一种方法，但是这增加了伴随延时操作(prolonged operation)的功能误差(function error)的问题。因此，尝试通过减小基板的厚度而实现层叠封装的安装能力的提高。
另外，电路布线形成在下部封装件110和上部封装120的绝缘层上，使得封装中使用的基板变厚。
发明内容
本发明提供了用于制造具有凹腔的基板的方法，该方法可减小其中安装有集成电路(IC)的封装件的厚度。
另外，本发明提供了用于制造具有凹腔的基板的方法，该方法允许多个半导体芯片成层地安装在层叠封装件的下部封装件中。
而且，本发明提供了用于制造具有凹腔的基板的方法，该方法可减小用于具有三层或更多层的层叠封装件的基板的厚度。
另外，本发明提供了用于制造具有凹腔的基板的方法，该方法可在绝缘层的厚度保持不变的同时通过将绝缘层形成在外部电路的侧部上而减小基板的总厚度。
本发明一个方面的特征是用于制造具有凹腔的基板的方法。该方法可包括：(a)在上部晶种层上形成上层电路；(b)将干膜层压在上部晶种层的其中将形成空腔的部分上；(c)通过在上部晶种层的顶部上以及上层电路的顶部和侧部上形成绝缘层而制造上部外层；(d)将上部外层堆叠在形成有内部电路的芯层的一侧上；(e)移除上部晶种层；以及(f)通过移除干膜而形成凹腔。
该方法还可包括：(g)在下部晶种层上形成下层电路；(h)通过将绝缘层层压在下部晶种层的顶部上以及下层电路的顶部和侧部上而形成下部外层；(i)将下部外层层压在其上形成有内部电路的芯层的另一侧上；以及(j)去除下部晶种层。
步骤(c)还可包括在其中将形成凹腔的部分中形成凹陷部，并且通过将干膜容纳于绝缘层的凹陷部中，而将绝缘层层压在上部晶种层上。
该方法还可包括形成与凹腔中的半导体芯片电连接的焊盘。
本发明另一个方面的特征在于具有凹腔的基板。该基板包括：芯层，其具有形成在绝缘材料两侧上的内部电路；上部外层，其形成在芯层的一侧上并且其中形成有上层电路；以及下部外层，其形成在芯层的另一侧上并且其中形成有下层电路，其中，上部外层还包括延伸到上层电路侧部的绝缘层，在该绝缘层中形成有凹陷部以容纳半导体芯片。
具有凹腔的基板还可包括焊盘，其形成在芯层的上表面上并被容纳于绝缘层的凹陷部中以便于与半导体芯片电连接。
将在以下描述中部分地阐述本总发明概念的其它方面和优点，并且所述方面和优点从以下描述中将部分地变得显而易见，或者可通过本总发明概念的实践而获得。
附图说明
根据以下描述、所附权利要求、以及附图可更好地理解本发明的这些和其它特征、方面和优点，在附图中：
图1是根据现有技术的层叠封装件的剖面图。
图2是构成根据本发明实施例的层叠封装件的半导体封装件的示意性剖面图。
图3是根据本发明实施例的层叠封装件的截面图。
图4是示出了用于制造根据本发明实施例的层叠封装件的方法的流程图。
图5至7是示出了根据本发明实施例的层叠封装件的制造过程的截面图。
具体实施方式
在下文中，将参照附图更详细地描述本发明的实施例。在参照附图的描述中，不管图序号为多少，那些相同或相应的部件用相同的参考标号表示，并且省略了重复的解释。
另外，在描述本发明的实施例之前，将首先描述制造普通基板的方法。尽管下面描述了用于制造多层基板的方法，但是本发明决不局限于以下所述用于制造多层基板的方法。
首先，内部电路图案被形成在芯层的外侧上。切割满足产品规格的内层基材，并且使用干膜和加工膜(working film)形成预定的内部电路图案。这里，内层可被擦洗(scrub)，内层干膜可被层压，并且内层可被曝光和显影。
之后，在将其上形成有电路图案的内层结合于外层之前，进行棕色(黑色)氧化处理以加固附着力。也就是说，铜箔的表面被化学氧化以增强表面粗糙度，从而使得层压产生更好的附着力。接着，通过层压内层基板和预浸料，进行预层压和层压处理。
之后，对层压的内层基板和预浸料进行真空压制。还可对层压的内层基板和预浸料进行热压或冷压，取代真空压制。
从面板的角落中裁出树脂和铜箔，并在钻孔处理的准备中进行X射线目标钻孔处理，在该处理中，在内部电路上的目标标记处形成孔。
之后，进行钻孔处理以实现基板的层之间的导电。这里，计算机数控(CNC)方法可用于钻孔处理。
接着，外层被覆以干膜和加工膜以形成电路图案，并将其暴露于预定强度的光线下预定持续时间，且在蚀刻处理中显影未受照射的部分。在检查了外层并测量了刻度之后，设计并制造出阻焊剂曝光膜(exposure film)。之后，进行诸如刷毛磨光(brush polishing)的预处理，在该预处理中，铜箔的表面被制造成粗糙的以使阻焊剂油墨更好地附着于基板。之后涂覆阻焊剂；使用在前述处理中适当设计的阻焊剂曝光膜曝光阻焊剂；在显影处理中去除阻焊剂；以及进行包括电/最终测试的各种后处理。
图2是构成根据本发明实施例的层叠封装件的半导体封装件的示意性剖面图。参照图2，根据本发明的半导体封装件包括芯层210、导线220、金属焊盘230、集成电路240、金属线250、模制部分260、以及焊球270。
根据本发明，至少一个集成电路240被安装并位于形成在基板上的凹腔中，以减小半导体封装件的厚度。也就是说，使用绝缘层使凹腔形成在层叠封装件的芯层210的上部中，并且集成电路240被插在所形成的凹腔中。接着，使用金属线250使得集成电路240电连接至导线220和金属焊盘230。使用防护材料(诸如环氧树脂)，将模制部分形成在集成电路240周围和顶部上。
图3是根据本发明实施例的其中未安装有芯片的层叠封装件的截面图。参照图3，根据本发明的基板包括芯层310、内部电路320、绝缘层330、空隙过孔(IVH)335、外部电路340、成像(photo)阻焊剂350、以及焊盘360。芯层310可为具有内部电路320的铜箔层压底基板，并且绝缘层330可由诸如预浸料或树脂涂覆铜箔(RCC)等材料制成。绝缘层330形成在芯层的两侧上，并且还形成在相邻内部电路图案之间以及相邻外部电路图案之间，通过这使得绝缘层330的顶表面与外部电路340的顶表面齐平。
由于内部电路320和外部电路340埋在绝缘层330中，因此尽管绝缘层330的厚度未改变，但是根据本发明的基板可更薄。
内部电路320和外部电路340可通过IVH 335和BVH彼此电连接。这里，内部电路320和外部电路340也可通过镀通孔(PTH，未示出)彼此电连接。焊盘370被容纳在凹腔中并连接基板和稍后将安装于其上的半导体芯片。半导体芯片和基板可通过倒装芯片结合焊或引线接合而彼此连接。
图4是示出了用于制造根据本发明实施例的层叠封装件的方法的流程图。根据该方法，为了形成凹腔，制造上部外层和下部外层，之后将它们堆叠在芯层上。
在步骤S410中，将上层电路形成在上部晶种层上。这里，上层电路是指形成在芯层上方的外部电路，而下层电路是指形成在芯层下方的外部电路。任何材料都可用于上部晶种层，只要所述材料是节省成本的、广泛使用的、以及在随后的蚀刻处理中在不会蚀刻掉Cu图案的情况下可被选择性地蚀刻就可以。所述材料的实例包括铝(Al)、镍(Ni)等。为了形成上层电路，将干膜层压在上部晶种层上，并通过曝光和显现显影处理形成图案。这里，可通过半加成法(SAP)或改进的半加成法(MSAP)而应用图案喷镀。
在通过化学镀形成铜(Cu)晶种层之后，半加成法(SAP)使用不具有晶种层的材料形成电路图案。也就是说，电镀抗蚀剂(plating resist)用在铜箔(该铜箔位于覆铜薄层压板的外层上)的表面上，并且使其中将形成电路的部分中的电镀抗蚀剂通过曝光和显影处理而被剥离。因此，外部铜箔的表面变为被暴露出，并且仅使得将不形成电路的部分中的电镀抗蚀剂保留在铜箔的外层上。通过在表面上镀铜，电镀抗蚀剂被剥离以在暴露的外部铜箔的表面上形成镀铜电路层，从而形成电路图案。一旦完成镀层，剩余的电镀抗蚀剂被剥离，并且使用闪速蚀刻(flush etching)溶解所形成的电路中的布线之间的铜箔，从而完成印刷电路板。当通过闪速蚀刻去除铜箔层时，镀铜电路层的上部边缘也变为有蚀痕的，这破坏了最后的印刷电路板的形状以及电路的横截面的纵横比。为了避免这种情况，也可进行以下处理：在半加成法中，镀铜电路层和外层铜箔层必须具有1.0或更高的Rv值(其为Vsc/Vsp)，Vsp是构成镀铜电路层的析出的铜的溶解速度，而Vsc是构成外层铜箔层的铜的溶解速度。改进的半加成法使用从一开始其上就层压有铜的材料(即，具有晶种层的材料)形成电路图案。该方法的其余部分与上述半加成法相同。镍或铝可用于本发明的晶种层。因此，由于用于晶种层的材料与用于电路的材料彼此不同，因此可选择性地蚀刻晶种层。
在步骤S420中，用于图案镀层的干膜被去除，另一个干膜被再次层压在其中将形成有凹腔的部分上。或者，可将除其中将形成有凹腔的部分以外的、用于图案镀层的干膜去除。
在步骤S430中，通过将绝缘层层压成与层压在其中将形成有凹腔的部分上的干膜一样高，而形成上部外层。这里，绝缘层可由诸如预浸料、树脂涂覆铜箔(RCC)、或粘结片(bonding sheet)等绝缘材料形成。
在步骤S440中，上部外层沿允许干膜面向芯层的方向而堆叠在其上形成有内部电路的芯层上。在步骤S450中，上部晶种层被选择性地蚀刻，之后在步骤S460中去除干膜，从而形成凹腔。
图5至7是示出了根据本发明实施例的具有凹腔的层叠封装件的制造过程的截面图。
图5示出了稍后堆叠在芯层上的上部外层的制造过程。
参考步骤(a)，在将干膜530层压在上部晶种层510上之后，形成与上层电路520相对应的电路图案。这里，可通过半加成法(S八P)或改进的半加成法(MSAP)来应用图案镀层。这里，凹腔形成在虚线k与k′之间的部分中，并且该部分在面积和宽度上不同于其中未形成有凹腔的其它部分。
参考步骤(b)，将形成在上部晶种层510上的干膜530去除，之后将另一个干膜530再次层压在虚线k与k′之间的部分上。该部分稍后被去除以形成凹腔。各种不同溶液(例如，NaOH)可用于去除干膜530。这里，为了在其中将形成有凹腔的部分上形成干膜530，可将干膜530整体去除，之后可将另一个干膜530再次层压在其中将形成有凹腔的部分上。或者，在除了其中将形成有凹腔的部分以外的部分上去除图案镀层处理所使用的干膜530。
参考步骤(c)，以与层压在其中将形成有凹腔的部分上的干膜530一样高的方式，将绝缘层540层压在芯层上。
绝缘层540被层压在上层电路520的顶部和侧部以及上部晶种层510的顶部上。
因此，即使绝缘层540的厚度未改变，基板的总厚度也可减小。
绝缘层540可由各种绝缘材料构成，并被预处理以提高镀层图案与绝缘层之间的附着强度。
图6示出了稍后堆叠在芯层上的下部外层的制造过程。
参考步骤(a)，将干膜630层压在下部晶种层610上，并接着形成与下层电路620相对应的电路图案。可通过半加成法(SAP)或改进的半加成法(MSAP)应用图案镀层。
参考步骤(b)，将形成在下部晶种层610上的干膜630去除。各种不同溶液(例如，NaOH)可用于去除干膜630。
参考步骤(c)，通过形成绝缘层640(该绝缘层将被层压在芯层上)而形成下部外层。绝缘层640被层压在下层电路620的顶部和侧部上以及下部晶种层610的顶部上。因此，如上所述，即使绝缘层640的厚度未改变，基板的总厚度也可减小。
图7示出了将上部外层和下部外层堆叠在芯层上的过程。
参考步骤(a)，将上部外层和下部外层堆叠在形成有内部电路720的芯层710上。这里，上部外层被堆叠成使得上部外层的干膜530和绝缘层540面向芯层710，并且下部外层被堆叠成使得下部外层的绝缘层640面向芯层710。
参考步骤(b)，在堆叠上部外层和下部外层之后去除上部晶种层510和下部晶种层610。这里，可使用不蚀刻铜的蚀刻液蚀刻掉铝(Al)或镍(Ni)，其中铜为用于外部电路(上层电路520和下层电路620)的材料。芯层710中形成的空隙过孔(IVH)可被填以绝缘材料(例如，树脂)，该绝缘材料构成层压在上部外层和下部外层上的绝缘层。
参考步骤(c)，在去除上部晶种层510和下部晶种层610之后，形成过孔，之后进行闪镀处理730(该处理为化学镀)，以便于将外部电路(上层电路520和下层电路620)与内部电路720电连接。
参考步骤(d)，在闪镀处理730之后，层压干膜740以使得过孔不被封闭。
参考步骤(e)，过孔的线被电解喷镀并且干膜740被去除。之后，通过蚀刻液蚀刻闪镀层730并且去除用于形成凹腔的干膜740。NaOH溶液可用作蚀刻液。
参考步骤(f)，通过表面处理工艺涂覆成像阻焊剂(PSR)760，并且通过镀金而形成焊盘750。根据用于接合半导体芯片的方法，焊盘750可为引线结合焊盘或倒装芯片焊盘。
虽然已结合所公开的实施例描述了本发明，但是应该理解的是，在不脱离下面权利要求中所述的本发明范围和精神或其等同物的前提下，本领域中普通技术人员可改变或更改这些实施例。

Claims (4)

1.一种用于制造具有凹腔的基板的方法，所述方法包括：
(a)在上部晶种层上形成上层电路；
(b)将干膜层压在所述上部晶种层的一部分上，其中在该部分的上方将形成凹腔；
(c)通过在所述上部晶种层的顶部上以及所述上层电路的顶部和侧部上形成绝缘层而制造上部外层；
(d)将所述上部外层堆叠在形成有内部电路的芯层的一侧上；
(e)去除所述上部晶种层；以及
(f)通过去除所述干膜而形成所述凹腔。
2.根据权利要求1所述的方法，进一步包括：
(g)在下部晶种层上形成下层电路；
(h)通过将绝缘层层压在所述下部晶种层的顶部以及所述下层电路的顶部和侧部上而形成下部外层；
(i)将所述下部外层层压在其上形成有所述内部电路的芯层的另一侧上；以及
(j)去除所述下部晶种层。
3.根据权利要求1所述的方法，其中步骤(c)进一步包括：
在绝缘层中的其中将形成有所述凹腔的部分中形成凹陷部；并且通过将所述干膜容纳于所述绝缘层的所述凹陷部中而将所述绝缘层层压在所述上部晶种层上。
4.根据权利要求1所述的方法，进一步包括：形成与所述凹腔中的半导体集成电路芯片电连接的焊盘。
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