CN100438010C - 引线框带和制造使用引线框带的半导体封装的方法 - Google Patents

引线框带和制造使用引线框带的半导体封装的方法 Download PDF

Info

Publication number
CN100438010C
CN100438010C CNB021570515A CN02157051A CN100438010C CN 100438010 C CN100438010 C CN 100438010C CN B021570515 A CNB021570515 A CN B021570515A CN 02157051 A CN02157051 A CN 02157051A CN 100438010 C CN100438010 C CN 100438010C
Authority
CN
China
Prior art keywords
lead frame
frame strip
wafer holder
lead
dam bar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB021570515A
Other languages
English (en)
Other versions
CN1427473A (zh
Inventor
李相均
李凤熙
李东勳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hanwha Techwin Co Ltd
Original Assignee
Samsung Techwin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Techwin Co Ltd filed Critical Samsung Techwin Co Ltd
Publication of CN1427473A publication Critical patent/CN1427473A/zh
Application granted granted Critical
Publication of CN100438010C publication Critical patent/CN100438010C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

提供了导线架带和制造使用导线架带的半导体封装的方法。导线架带包含至少一个导线架板，其中多个单元导线架以矩阵形式彼此连接，各个单元导线架包含：晶片座，其中半导体芯片将被装配在该晶片座上；系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；多个导线，处于和系筋的另一端相同的水平并且从系垫延伸预定距离；横过导线形成的、与导线整合以支撑导线的坝条，其中沿着导线架板的边缘形成沟槽，沟槽充当缓冲带，并且在沟槽的横向形成连接带以支撑导线架板。

Description

引线框带和制造使用引线框带的半导体封装的方法
本专利申请要求2001年12月21日于韩国知识产权局(KIPO)申请的韩国专利申请2001-82487的优先权，这里完整参考引用了该申请。
技术领域
本发明涉及引线框带和制造使用引线框带的半导体封装的方法，更具体地，本发明涉及能够抑制封装模制期间模制溢料的产生的引线框带，和制造使用该引线框的半导体封装的方法。
背景技术
图1是传统半导体封装10的剖视图，而图2是在制造图1的半导体封装10时使用的单元引线框的示意结构的透视图。
图1示出的半导体封装10是一种所谓的智能金属芯片尺寸封装(SMCSP)。晶片座12构成半导体封装10的上部，并且半导体芯片11附着于半导体封装10中晶片座12的底部。在图2中，晶片座12被系筋(tiebar)15支撑。具体地，系筋15被加工成下设在晶片座12的角部，延伸到晶片座12外部。并且，在系筋15之间形成多个导线20。导线20和晶片座12分别通过接合线21和22被连接到半导体芯片11。接着，涂上密封剂25以包围半导体芯片11、系筋15、导线20和晶片座12的侧面和底部。在图2中，附图标记16和30分别表示孔和坝条(dam bar)，并且后面会对其进行详细描述。
制造使用具有上述晶片座的引线框的半导体封装的一般方法包含：分别模制装配有半导体芯片的引线框的单切边(individualtrimming)方法；和模制并且接着切断装配有多个半导体芯片的矩阵类型引线框带的矩阵封装(MAT)方法。由于在使用单切边方法时单元半导体封装的制造成本高于MAT方法的制造成本，所以单切边方法不经常使用。
图3是传统MAT方法中使用的引线框带的一部分的顶视图。更具体地说，图3示出了引线框矩阵的角部的放大视图。
参照图3，单元引线框是整合晶片座12、系筋15和多个导线20的结构。坝条30充当两个引线框的相邻导线之间的边界。坝条30是支撑导线20的栅格型结构。
为了在半导体封装的树脂模制工艺中使用的模具内形成凹陷，需要箝位上部模具和下部模具。在箝位工艺中，上部模具向在晶片座12的角部下设的引线框的晶片座12施加压力。在箭头A1的方向上，压力通过系筋15被传递到单元引线框的4个角部。在单元引线框的角部形成孔16，孔16对应于系筋15的末端，于是几乎完全吸收箝位压力。在单元引线框被放到引线框矩阵的边缘或角部上的情况下，箝位压力没有被孔16完全吸收，并且在箭头A2的方向上被传递到相邻坝条30。
通常，坝条30被半蚀刻，以使半导体封装模制之后在切割加工期间半导体封装的切断部分出现的毛边或锯条的磨损最小。然而外力很容易使坝条30的半蚀刻部分变形。于是，在箭头A2的方向上传递的压力可能使相邻坝条31变形。坝条31的变形阻碍了在使用树脂模制引线框带的箝位加工中上部模具和下部模具的精确接合。因此，上部和下部模具的不完整接合可能产生模制溢料26，即导致导线20被图1所示的树脂覆盖的现象。
为了防止模制溢料的产生，人们已经建议在向模具中插入引线框时在引线框带的下部粘附薄膜。这种方法降低了模制溢料的出现，但是额外需要在引线框带的下部附着和脱离薄膜，从而增加了制造成本。
发明内容
本发明提供了一种引线框带和制造使用该引线框带的半导体封装的方法，其中该引线框带能够在使用矩阵封装(MAT)方法制造半导体封装时防止半导体封装中模制溢料的出现。
本发明还提供了一种用于半导体封装、降低半导体封装制造成本的引线框带，和制造使用该引线框带的半导体封装的方法。
根据本发明的一个方面，提供一种引线框带，包括：至少一个引线框板，在该引线框板中多个单元引线框以矩阵形式彼此连接，其中各个单元引线框包含：晶片座，其中半导体芯片将被装配在该晶片座上；系筋，其中系筋的一端被连接到晶片座并且被加工成向下设置的形式，其中该系筋在向下设置时将晶片座和多个导线保持在不同高度；多个导线，处于和系筋的另一端相同的高度并且从晶片座延伸预定距离；横过导线形成并且与导线整合以支撑导线的坝条，其中沿着引线框板的边缘形成沟槽，该沟槽充当缓冲带，并且在沟槽上横向形成连接带以支撑引线框板，所述连接带形成在坝条的延伸线上。
最好是，晶片座一侧装配半导体芯片，而另一侧暴露到外部。
最好是，在坝条的延伸线上形成连接带。
最好是，连接带具有弯曲部分。
最好是，坝条包含多个凹槽，所述多个凹槽排列成一条线。
最好是，坝条包含多个凹槽，所述多个凹槽排列成一条线。
根据本发明的另一个方面，提供一种制造半导体封装的方法，该方法包含制备引线框带，该引线框带包含至少一个引线框板，在该引线框板中多个单元引线框以矩阵形式彼此连接，其中各个单元引线框均具有：将装配半导体芯片的晶片座；系筋，其中系筋的一端被连接到晶片座并且被加工成向下设置的形式，其中该系筋在向下设置时将晶片座和多个导线保持在不同高度；多个导线，处于和系筋的另一端相同的高度并且从晶片座延伸预定距离；横过导线而形成并且与导线整合以支撑导线的坝条，其中沿着引线框板的边缘形成沟槽，该沟槽充当缓冲带，并且在沟槽上横向形成连接带以支撑引线框板；向晶片座装配半导体芯片；在半导体芯片和导线之间，及半导体芯片和晶片座之间进行导线接合；用树脂模制引线框带，所述引线框带装配有半导体芯片并且与导线接合以形成封装；和以半导体封装为单位切割模制的引线框带，其中在坝条的延伸线上形成所述连接带。
最好是，晶片座一侧装配半导体芯片，而另一侧暴露到外部。
最好是，该方法还包含在制备引线框带期间半蚀刻引线框带以便在坝条中形成多个凹槽，所述多个凹槽排列成一条线。
当以半导体封装为单元切断模制的引线框带时，可以沿着多个凹槽切断模制的引线框带。
在制备引线框带期间，该方法还包含对引线框带进行蚀刻或打孔以便在坝条中形成多个孔，所述多个孔排列成一条线。
当将模制的引线框带切割成半导体封装单元时，可以沿着多个孔切断引线框带。
附图说明
通过参照附图详细描述优选实施例可以更加明白本发明的上述方面和优点，其中：
图1是传统半导体封装的示意剖视图；
图2是在制造图1的半导体封装时使用的单元引线框的示意结构的透视图；
图3是在制造图1的半导体封装时使用的传统引线框带的一部分的顶视图；
图4是基于本发明实施例的引线框带的顶视图；
图5是图4的引线框带的部分B的顶视图；
图6是沿着晶片座的对角线得到的图5中引线框带的单元引线框的剖视图；
图7是图5的部分C的顶视图；
图8是图解制造基于本发明实施例的半导体封装的方法的流程图；而
图9是基于本发明实施例的引线框带的示意结构的顶视图。
具体实施方式
参照图4，基于本发明实施例的引线框带100包含引线框板110，其中在引线框板110上，多个单元引线框120在相同平面以矩阵形式彼此对齐连接。当使用矩阵封装(MAT)方法制造半导体封装时，可以使用引线框带100。例如，4个引线框板110排列成线以形成一个引线框带100，但是在图4中为了方便只图解了引线框带100的一部分。沿着导轨部分在引线框带100的两端形成对位孔101。
沿着引线框板110的边缘形成长条型沟槽200。横过沟槽200形成连接带210以支撑引线框板110，而连接带210断开沟槽200。在某些坝条的延伸线上形成连接带210。在图4中，连接带210被图解成形成于引线框板110的边缘的中心处，以及坝条的位于引线框板110的角部的延伸线处。然而连接带210的数量和位置不局限于上述描述。
图5是图4的引线框板110的部分B的放大顶视图。参照图4，形成引线框板110的单元引线框包含晶片座130；被加工成在对角方向上从晶片座130向下延伸，即下设的系筋135；从晶片座130径向延伸预定距离的导线140；和横过导线140形成以支撑导线140、并且是相邻单元引线框之间的边界的坝条150。相邻单元引线框共用一个坝条150，并且在整个引线框板110上以网格形式形成坝条150。
图6是沿着晶片座130的对角线得到的图5中引线框带的单元引线框的剖视图。具体地，图6图解了在形成封装的模制加工期间单元引线框中的变化，但是为了清楚，省略了对封装的单元引线框的图解。
为了形成封装，装配有半导体芯片(未示出)的单元引线框首先被箝位在上部模具300和下部模具310之间，并且接着将模制树脂填充到上部和下部模具300和310之间形成的模具凹陷中。如图6所示，在半导体芯片的箝位期间，上部模具300将晶片座130下压。在图6中，点线表示在下压上部模具300之前上部模具300和晶片座130的初始位置。上部模具300的下压降低了晶片座130的位置，并且通过系筋135将箭头A10指示的作用力传递到引线框120的下设角部137。
参照图5，如部分C中的A10所示，作用力被传递并集中在单元引线框的角部137，除了引线框板110的边缘之外。然而孔136吸收了大量的集中作用力。并且，沿着引线框板110的边缘形成的沟槽200的变形会吸收位于引线框板110边缘的单元引线框的角部137上集中的作用力。由于在坝条150的延伸线上形成连接带210，箭头A20指示的作用力通过连接带210传递到引线框板110的外部。
如图5所示，连接带210最好具有弯曲部分，该弯曲部分充当通过沟槽200的变形吸收作用力的缓冲带。在图5中，连接带210的弯曲部分为′Z′形，但是连接带210的形状可以是各种各样的。
如上所述，通过作用力吸收可以抑制箭头A2所示的排斥力的出现，从而防止与引线框板110的边缘相邻的坝条的变形。
图7是图5的部分C的放大顶视图，其中为了方便省略了指示方向上作用力的箭头。
参照图7，坝条150包含沿一条线纵向形成的凹槽155。与传统的半蚀刻坝条相比，在不导致毛边和锯条磨损的出现的情况下可以防止因其结构削弱造成的坝条150的变形。可以使用半蚀刻形成凹槽155。
其间，尽管附图中未示出，然而可以形成孔而不是凹槽155。在与图7所示的凹槽155相同的位置上形成孔，以便在坝条50上打孔。可以使用蚀刻或打孔方法形成孔。在引线框带100的模制之后，沿着凹槽155或孔将引线框带100切割成单元半导体封装。
图8是图解制造基于本发明实施例的半导体封装的方法的流程图。参照图8，该方法包含制备引线框带(S1)，装配半导体芯片(S2)；导线接合加工(S3)；模制加工(S4)；和切割加工(S5)。
在制备引线框带(S1)时，将引线框带制造成具有至少一个引线框板，其中多个单元引线框以矩阵形式排列。各个单元引线框包含晶片座，其中半导体芯片将被装配在该晶片座上；从晶片座延伸并且被加工成下设形式的多个系筋；多个导线，处于和系筋的端部相同的水平并且从晶片座延伸预定距离；横过导线形成以支撑导线的坝条。沿着引线框板的边缘形成沟槽，并且在沟槽上横向形成连接带以支撑引线框板。前面已经详细描述了引线框带，于是这里省略了有关引线框带的描述。可以使用半蚀刻或打孔方法形成引线框带。
当制备引线框(S1)时，在坝条上形成多个凹槽。如上所述，使用半蚀刻方法在坝条中形成多个凹槽，该多个凹槽排列成一条线。可选地，可以使用蚀刻或打孔方法在坝条中形成多个孔。
在向晶片座装配半导体芯片(S2)时，分别从晶片上切下半导体芯片并且将其装配到晶片座的下部。
在进行导线接合加工(S3)时，进行导线接合以便将半导体芯片电连接到导线或晶片座。
在模制加工(S4)中，进行模制加工以便将半导体芯片和导线接合引线框封装在引线框板单元中。如上所述，在这种情况下，防止了坝条的变形，从而在上部和下部模具之间精确形成了凹陷。因此，可以防止模制溢料的出现。
在切割加工(S5)中，以半导体封装为单元切割封装的引线框，从而完成不出现模制溢料的半导体封装。
在切割加工(S5)中，沿着坝条之上或之中形成的多个凹槽或孔将封装的引线框板切割成半导体封装单元，其中该多个凹槽或孔排列成一条线。如果沿着凹槽或孔切割引线框板，可以防止半导体封装的切割部分的毛边的出现。
统计测量表明，使用传统引线框制造半导体封装的方法所制造的半导体封装有35％出现模制溢料，而使用基于本发明的半导体封装制造方法所制造的半导体封装有4％出现模制溢料。也就是说，基于本发明的半导体封装制造方法显著降低了模制溢料的出现。
如上所述，通过基于本发明的引线框和制造使用该引线框的半导体封装的方法，可以使用MAT方法制造出模制溢料的产生得到抑制的半导体封装。
此外，根据本发明，不需要用于清除模制溢料的其它加工和成本，于是降低了半导体封装的制造成本。
虽然前面参照优选实施例示出和描述了本发明，然而本领域的技术人员可以理解，在不偏离所附权利要求书限定的本发明的宗旨和范围的前提下，可以进行各种形式和细节方面的改变。

Claims (13)

1.一种引线框带(100)，包括：
至少一个引线框板(110)，在该引线框板(110)中多个单元引线框(120)以矩阵形式彼此连接，
其中各个单元引线框(120)包含：
晶片座(130)，其中半导体芯片将被装配在该晶片座上；
系筋(135)，其中系筋的一端被连接到晶片座(130)并且被加工成向下设置的形式，其中该系筋在向下设置时将晶片座(130)和多个导线(140)保持在不同高度；
多个导线(140)，处于和系筋的另一端相同的高度并且从晶片座(130)延伸预定距离；
横过导线(140)形成并且与导线(140)整合以支撑导线的坝条(150)，
其中沿着引线框板的边缘形成沟槽(200)，该沟槽(200)充当缓冲带，并且
在沟槽(200)上横向形成连接带(210)以支撑引线框板(110)，所述连接带(210)形成在坝条(150)的延伸线上。
2.如权利要求1所述的引线框带，其中晶片座一侧装配半导体芯片，而另一侧暴露到外部。
3.如权利要求1所述的引线框带，其中连接带具有弯曲部分。
4.如权利要求2所述的引线框带，其中坝条包含多个凹槽，所述多个凹槽排列成一条线。
5.如权利要求1所述的引线框带，其中坝条包含多个凹槽，所述多个凹槽排列成一条线。
6.如权利要求3所述的引线框带，其中坝条包含多个凹槽，所述多个凹槽排列成一条线。
7.一种制造半导体封装的方法，包括：
制备引线框带(100)，该引线框带(100)包含至少一个引线框板(110)，在该引线框板中多个单元引线框(120)以矩阵形式彼此连接，其中各个单元引线框(120)均具有：将装配半导体芯片的晶片座(130)；系筋(135)，其中系筋(135)的一端被连接到晶片座(130)并且被加工成向下设置的形式，其中该系筋(135)在向下设置时将晶片座(135)和多个导线(140)保持在不同高度；多个导线(140)，处于和系筋的另一端相同的高度并且从晶片座(130)延伸预定距离；横过导线(140)而形成并且与导线(140)整合以支撑导线(140)的坝条(150)，其中沿着引线框板(110)的边缘形成沟槽(200)，该沟槽(200)充当缓冲带，并且在沟槽(200)上横向形成连接带(210)以支撑引线框板(110)；
向晶片座(130)装配半导体芯片；
在半导体芯片和导线(140)之间，及半导体芯片和晶片座(130)之间进行导线接合；
用树脂模制引线框带，所述引线框带装配有半导体芯片并且与导线接合以形成封装；和
以半导体封装为单元切割模制的引线框带，
其中在坝条(150)的延伸线上形成所述连接带(210)。
8.如权利要求7所述的方法，其中晶片座一侧装配半导体芯片，而另一侧暴露到外部。
9.如权利要求7所述的方法，还包括在制备引线框带期间半蚀刻引线框带以便在坝条中形成多个凹槽，所述多个凹槽排列成一条线。
10.如权利要求8所述的方法，还包括在制备引线框带期间半蚀刻引线框带以便在坝条中形成多个凹槽，所述多个凹槽排列成一条线。
11.如权利要求9所述的方法，其中当以半导体封装为单元切断模制的引线框带时，沿着所述多个凹槽切断模制的引线框带。
12.如权利要求7所述的方法，其中在制备引线框带期间，该方法还包括对引线框带进行蚀刻或打孔以便在坝条中形成多个孔，所述多个孔排列成一条线。
13.如权利要求12所述的方法，其中当将模制的引线框带切割成半导体封装单元时，沿着所述多个孔切割引线框带。
CNB021570515A 2001-12-21 2002-12-20 引线框带和制造使用引线框带的半导体封装的方法 Expired - Fee Related CN100438010C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR0182487 2001-12-21
KR1020010082487A KR100781149B1 (ko) 2001-12-21 2001-12-21 리드프레임 스트립 및 이를 이용한 반도체 패키지 제조 방법

Publications (2)

Publication Number Publication Date
CN1427473A CN1427473A (zh) 2003-07-02
CN100438010C true CN100438010C (zh) 2008-11-26

Family

ID=19717392

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021570515A Expired - Fee Related CN100438010C (zh) 2001-12-21 2002-12-20 引线框带和制造使用引线框带的半导体封装的方法

Country Status (4)

Country Link
US (1) US6838753B2 (zh)
JP (1) JP4381677B2 (zh)
KR (1) KR100781149B1 (zh)
CN (1) CN100438010C (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132734B2 (en) * 2003-01-06 2006-11-07 Micron Technology, Inc. Microelectronic component assemblies and microelectronic component lead frame structures
US7183485B2 (en) * 2003-03-11 2007-02-27 Micron Technology, Inc. Microelectronic component assemblies having lead frames adapted to reduce package bow
KR20050083322A (ko) * 2004-02-23 2005-08-26 삼성테크윈 주식회사 반도체 패키지용 리이드 프레임과 이의 제조방법
US7635910B2 (en) * 2005-01-20 2009-12-22 Infineon Technologies Ag Semiconductor package and method
US7821116B2 (en) * 2007-02-05 2010-10-26 Fairchild Semiconductor Corporation Semiconductor die package including leadframe with die attach pad with folded edge
US7714418B2 (en) * 2007-07-23 2010-05-11 National Semiconductor Corporation Leadframe panel
US7812430B2 (en) * 2008-03-04 2010-10-12 Powertech Technology Inc. Leadframe and semiconductor package having downset baffle paddles
US8492887B2 (en) * 2010-03-25 2013-07-23 Stats Chippac Ltd. Integrated circuit packaging system with leadframe and method of manufacture thereof
CN101814482B (zh) * 2010-04-30 2012-04-25 江苏长电科技股份有限公司 有基岛引线框结构及其生产方法
TW201417195A (zh) * 2012-10-23 2014-05-01 Wecon Automation Corp 圓形式晶粒置放方法
JP6087153B2 (ja) * 2013-01-10 2017-03-01 株式会社三井ハイテック リードフレーム
US9337130B2 (en) * 2014-07-28 2016-05-10 Texas Instruments Incorporated Leadframe strip and leadframes
US9741643B2 (en) * 2016-01-22 2017-08-22 Texas Instruments Incorporated Leadframe strip with vertically offset die attach pads between adjacent vertical leadframe columns
JP6677616B2 (ja) * 2016-09-29 2020-04-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN107919339B (zh) * 2016-10-11 2022-08-09 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
KR102514564B1 (ko) * 2021-06-28 2023-03-29 해성디에스 주식회사 홈이 형성된 리드를 포함하는 리드 프레임

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242281B1 (en) * 1998-06-10 2001-06-05 Asat, Limited Saw-singulated leadless plastic chip carrier
US20020003918A1 (en) * 2000-03-08 2002-01-10 Ooi Boon Siew Quantum well intermixing
JP2002231872A (ja) * 2001-02-02 2002-08-16 Mitsui High Tec Inc リードフレーム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327008A (en) * 1993-03-22 1994-07-05 Motorola Inc. Semiconductor device having universal low-stress die support and method for making the same
KR0140458B1 (ko) * 1994-12-14 1998-06-01 황인길 반도체 패키지 제조용 리드프레임
KR100369502B1 (ko) * 1999-12-14 2003-01-30 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 리드 프레임의 구조
US6400004B1 (en) * 2000-08-17 2002-06-04 Advanced Semiconductor Engineering, Inc. Leadless semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242281B1 (en) * 1998-06-10 2001-06-05 Asat, Limited Saw-singulated leadless plastic chip carrier
US20020003918A1 (en) * 2000-03-08 2002-01-10 Ooi Boon Siew Quantum well intermixing
JP2002231872A (ja) * 2001-02-02 2002-08-16 Mitsui High Tec Inc リードフレーム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
2002-03918A 2002.03.22

Also Published As

Publication number Publication date
JP2003197844A (ja) 2003-07-11
KR100781149B1 (ko) 2007-11-30
JP4381677B2 (ja) 2009-12-09
US20030116833A1 (en) 2003-06-26
CN1427473A (zh) 2003-07-02
KR20030052502A (ko) 2003-06-27
US6838753B2 (en) 2005-01-04

Similar Documents

Publication Publication Date Title
CN100438010C (zh) 引线框带和制造使用引线框带的半导体封装的方法
US6617197B1 (en) Multi row leadless leadframe package
KR100927319B1 (ko) 스탬핑된 리드프레임 및 그 제조 방법
KR950005269B1 (ko) 반도체 패키지 구조 및 제조방법
US20110263077A1 (en) Method of assembling semiconductor devices including saw singulation
US6882048B2 (en) Lead frame and semiconductor package having a groove formed in the respective terminals for limiting a plating area
US7095096B1 (en) Microarray lead frame
US6703694B2 (en) Frame for semiconductor package including plural lead frames having thin parts or hollows adjacent the terminal roots
US8643156B2 (en) Lead frame for assembling semiconductor device
KR100971938B1 (ko) 리드 프레임 구조체와 그 응용
WO2014016734A1 (en) Matrix leadframe for led packaging
US20050073031A1 (en) Lead frame, semiconductor device, and method for manufacturing semiconductor device
CN218447899U (zh) 可靠性及作业性改善型框架结构
US8080448B1 (en) Semiconductor device with nested rows of contacts
JPS61237458A (ja) 樹脂封止型半導体装置
CN107919339B (zh) 具有高密度引线阵列的半导体装置及引线框架
KR100819794B1 (ko) 리드프레임 및, 그것을 이용한 반도체 패키지 제조 방법
JPH05243464A (ja) リードフレーム及びこれを用いた樹脂封止型半導体装置
JP2661152B2 (ja) Ｉｃカード用モジュールの製造方法
KR970000093Y1 (ko) 버텀 리드 팩키지용 리드 프레임
KR970053631A (ko) 반도체 다핀 패키지 및 그 제조방법
CN110637364B (zh) 改进的引线框系统
CN115706070A (zh) Qfn封装结构及其制作方法
JP2001127232A (ja) リードフレーム及びその製造方法
JPH02159752A (ja) リードフレーム

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081126

Termination date: 20121220