CN1427473A - 导线架带和制造使用导线架带的半导体封装的方法 - Google Patents

导线架带和制造使用导线架带的半导体封装的方法 Download PDF

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CN1427473A
CN1427473A CN02157051A CN02157051A CN1427473A CN 1427473 A CN1427473 A CN 1427473A CN 02157051 A CN02157051 A CN 02157051A CN 02157051 A CN02157051 A CN 02157051A CN 1427473 A CN1427473 A CN 1427473A
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wire frame
frame strip
lead
lead frame
strip
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李相均
李凤熙
李东勳
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Hanwha Techwin Co Ltd
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Abstract

提供了导线架带和制造使用导线架带的半导体封装的方法。导线架带包含至少一个导线架板，其中多个单元导线架以矩阵形式彼此连接，各个单元导线架包含：晶片座，其中半导体芯片将被装配在该晶片座上；系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；多个导线，处于和系筋的另一端相同的水平并且从系垫延伸预定距离；横过导线形成的、与导线整合以支撑导线的坝条，其中沿着导线架板的边缘形成沟槽，沟槽充当缓冲带，并且在沟槽的横向形成连接带以支撑导线架板。

Description

导线架带和制造使用 导线架带的半导体封装的方法
本专利申请要求2001年12月21日于韩国知识产权局(KIPO)申请的韩国专利申请2001-82487的优先权，这里完整参考引用了该申请。
技术领域
本发明涉及导线架带和制造使用导线架带的半导体封装的方法，更具体地，本发明涉及能够抑制封装模塑期间模塑溢料的产生的导线架带，和制造使用该导线架的半导体封装的方法。
背景技术
图1是传统半导体封装10的剖视图，而图2是在制造图1的半导体封装10时使用的单元导线架的示意结构的透视图。
图1示出的半导体封装10是一种所谓的智能金属芯片尺寸封装(SMCSP)。晶片座12构成半导体封装10的上部，并且半导体芯片11附着于半导体封装10中晶片座12的底部。在图2中，晶片座12被系筋(tiebar)15支撑。具体地，系筋15被加工成下设在晶片座12的角部，延伸到晶片座12外部。并且，在系筋15之间形成多个导线20。导线20和晶片座12分别通过接合线21和22被连接到半导体芯片11。接着，涂上密封剂25以包围半导体芯片11、系筋15、导线20和晶片座12的侧面和底部。在图2中，附图标记16和30分别表示孔和坝条(dam bar)，并且后面会对其进行详细描述。
制造使用具有上述晶片座的导线架的半导体封装的一般方法包含：分别塑模装配有半导体芯片的导线架的单切边(individualtrimming)方法；和塑模并且接着切断装配有多个半导体芯片的矩阵类型导线架带的矩阵封装(MAT)方法。由于在使用单切边方法时单元半导体封装的制造成本高于MAT方法的制造成本，所以单切边方法不经常使用。
图3是传统MAT方法中使用的导线架带的一部分的顶视图。更具体地说，图3示出了导线架矩阵的角部的放大视图。
参照图3，单元导线架是整合晶片座12、系筋15和多个导线20的结构。坝条30充当两个导线架的相邻导线之间的边界。坝条30是支撑导线20的栅格型结构。
为了在半导体封装的树脂模塑工艺中使用的模具内形成凹陷，需要箝位上部模具和下部模具。在箝位工艺中，上部模具向在晶片座12的角部下设的导线架的晶片座12施加压力。在箭头A1的方向上，压力通过系筋15被传递到单元导线架的4个角部。在单元导线架的角部形成孔16，孔16对应于系筋15的末端，于是几乎完全吸收箝位压力。在单元导线架被放到导线架矩阵的边缘或角部上的情况下，箝位压力没有被孔16完全吸收，并且在箭头A2的方向上被传递到相邻坝条30。
通常，坝条30被半蚀刻，以使半导体封装模塑之后在切割加工期间半导体封装的切断部分出现的毛边或锯条的磨损最小。然而外力很容易使坝条30的半蚀刻部分变形。于是，在箭头A2的方向上传递的压力可能使相邻坝条31变形。坝条31的变形阻碍了在使用树脂模塑导线架带的箝位加工中上部模具和下部模具的精确接合。因此，上部和下部模具的不完整接合可能产生模塑溢料26，即导致导线20被图1所示的树脂覆盖的现象。
为了防止模塑溢料的产生，人们已经建议在向模具中插入导线架时在导线架带的下部粘附薄膜。这种方法降低了模塑溢料的出现，但是额外需要在导线架带的下部附着和脱离薄膜，从而增加了制造成本。
发明内容
本发明提供了一种导线架带和制造使用该导线架带的半导体封装的方法，其中该导线架带能够在使用矩阵封装(MAT)方法制造半导体封装时防止半导体封装中模塑溢料的出现。
本发明还提供了一种用于半导体封装、降低半导体封装制造成本的导线架带，和制造使用该导线架带的半导体封装的方法。
根据本发明的一个方面，提供一种导线架带，该导线架带包含至少一个导线架板，其中多个单元导线架以矩阵形式彼此连接。各个单元导线架包含晶片座，其中半导体芯片将被装配在该晶片座上；系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；多个导线，处于和系筋的另一端相同的水平并且从系垫(tie pad)延伸预定距离；横过导线形成的、与导线整合以支撑导线的坝条，其中沿着导线架板的边缘形成沟槽，沟槽充当缓冲带，并且在沟槽的横向形成连接带以支撑导线架板。
最好是，晶片座一侧装配半导体芯片，而另一侧暴露到外部。
最好是，在坝条的延伸线上形成连接带。
最好是，连接带具有弯曲部分。
最好是，坝条在线上包含多个凹槽。
最好是，坝条在线上包含多个凹槽。
根据本发明的另一个方面，提供一种制造半导体封装的方法，该方法包含制备导线架带，该导线架带包含至少一个导线架板，在该导线架板中多个单元导线架以矩阵形式彼此连接，其中各个单元导线架均具有将装配半导体芯片的晶片座；系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；多个导线，处于和系筋的另一端相同的水平并且从系垫延伸预定距离；横过导线而形成并且与导线整合以支撑导线的坝条，其中沿着导线架板的边缘形成沟槽，沟槽充当缓冲带，并且在沟槽的横向形成连接带以支撑导线架板；向晶片座装配半导体芯片；在半导体芯片和导线之间，及半导体芯片和晶片座之间进行导线接合；用树脂模塑导线架带，导线架带装配有半导体芯片并且与导线接合以形成封装；及以导线架为单元切断塑模的导线架带。
最好是，晶片座一侧装配半导体芯片，而另一侧暴露到外部。
最好是，该方法还包含在制备导线架带期间半蚀刻导线架带以便在线上的坝条中形成凹槽。
当以半导体封装为单元切断塑模的导线架带时，可以沿着多个凹槽切断塑模的导线架带。
在制备导线架带期间，该方法还包含对导线架带进行蚀刻或打孔以便在线上的坝条中形成多个孔。
当将塑模的导线架带切割成半导体封装单元时，可以沿着多个孔切断导线架带。
附图说明
通过参照附图详细描述优选实施例可以更加明白本发明的上述方面和优点，其中：
图1是传统半导体封装的示意剖视图；
图2是在制造图1的半导体封装时使用的单元导线架的示意结构的透视图；
图3是在制造图1的半导体封装时使用的传统导线架带的一部分的顶视图；
图4是基于本发明实施例的导线架带的顶视图；
图5是图4的导线架带的部分B的顶视图；
图6是沿着晶片座的对角线得到的图5中导线架带的单元导线架的剖视图；
图7是图5的部分C的顶视图；
图8是图解制造基于本发明实施例的半导体封装的方法的流程图。
具体实施方式
参照图4，基于本发明实施例的导线架带100包含导线架板110，其中在导线架板110上，多个单元导线架120在相同平面以矩阵形式彼此对齐连接。当使用矩阵封装(MAT)方法制造半导体封装时，可以使用导线架带100。例如，4个导线架板110排列成线以形成一个导线架带100，但是在图4中为了方便只图解了导线架带100的一部分。沿着导轨部分在导线架带100的两端形成对位孔101。
沿着导线架板110的边缘形成长条型沟槽200。横过沟槽200形成连接带210以支撑导线架板110，而连接带210断开沟槽200。在某些坝条的延伸线上形成连接带210。在图4中，连接带210被图解成形成于导线架板110的边缘的中心处，以及坝条的位于导线架板110的角部的延伸线处。然而连接带210的数量和位置不局限于上述描述。
图5是图4的导线架板110的部分B的放大顶视图。参照图4，形成导线架板110的单元导线架包含晶片座130；被加工成在对角方向上从晶片座130向下延伸，即下设的系筋135；从晶片座130径向延伸预定距离的导线140；和横过导线140形成以支撑导线140、并且是相邻单元导线架之间的边界的坝条150。相邻单元导线架共用一个坝条150，并且在整个导线架板110上以网格形式形成坝条150。
图6是沿着晶片座130的对角线得到的图5中导线架带的单元导线架的剖视图。具体地，图6图解了在形成封装的模塑加工期间单元导线架中的变化，但是为了清楚，省略了对封装的单元导线架的图解。
为了形成封装，装配有半导体芯片(未示出)的单元导线架首先被箝位在上部模具300和下部模具310之间，并且接着将模塑树脂填充到上部和下部模具300和310之间形成的模具凹陷中。如图6所示，在半导体芯片的箝位期间，上部模具300将晶片座130下压。在图6中，点线表示在下压上部模具300之前上部模具300和晶片座130的初始位置。上部模具300的下压降低了晶片座130的位置，并且通过系筋135将箭头A10指示的作用力传递到导线架120的下设角部137。
参照图5，如部分C中的A10所示，作用力被传递并集中在单元导线架的角部137，除了导线架板110的边缘之外。然而孔136吸收了大量的集中作用力。并且，沿着导线架板110的边缘形成的沟槽200的变形会吸收位于导线架板110边缘的单元导线架的角部137上集中的作用力。由于在坝条150的延伸线上形成连接带210，箭头A20指示的作用力通过连接带210传递到导线架板110的外部。
如图5所示，连接带210最好具有弯曲部分，该弯曲部分充当通过沟槽200的变形吸收作用力的缓冲带。在图5中，连接带210的弯曲部分为′Z′形，但是连接带210的形状可以是各种各样的。
如上所述，通过作用力吸收可以抑制箭头A2所示的排斥力的出现，从而防止与导线架板110的边缘相邻的坝条的变形。
图7是图5的部分C的放大顶视图，其中为了方便省略了指示方向上作用力的箭头。
参照图7，坝条150包含在线上纵向形成的凹槽155。与传统的半蚀刻坝条相比，在不导致毛边和锯条磨损的出现的情况下可以防止因其结构削弱造成的坝条150的变形。可以使用半蚀刻形成凹槽155。
其间，尽管附图中未示出，然而可以形成孔而不是凹槽155。在与图7所示的凹槽155相同的位置上形成孔，以便在坝条50上打孔。可以使用蚀刻或打孔方法形成孔。在导线架带100的模塑之后，沿着凹槽155或孔将导线架带100切割成单元半导体封装。
图8是图解制造基于本发明实施例的半导体封装的方法的流程图。参照图8，该方法包含制备导线架带(S1)，装配半导体芯片(S2)；导线接合加工(S3)；模塑加工(S4)；和切割加工(S5)。
在制备导线架带(S1)时，将导线架带制造成具有至少一个导线架板，其中多个单元导线架以矩阵形式排列。各个单元导线架包含晶片座，其中半导体芯片将被装配在该晶片座上；从晶片座延伸并且被加工成下设形式的多个系筋；多个导线，处于和系筋的端部相同的水平并且从晶片座延伸预定距离；横过导线形成以支撑导线的坝条。沿着导线架板的边缘形成沟槽，并且在沟槽上横向形成连接带以支撑导线架板。前面已经详细描述了导线架带，于是这里省略了有关导线架带的描述。可以使用半蚀刻或打孔方法形成导线架带。
当制备导线架(S1)时，在坝条上形成多个凹槽。如上所述，使用半蚀刻方法在线上的坝条中形成多个凹槽。可选地，可以使用蚀刻或打孔方法在坝条中形成多个孔。
在向晶片座装配半导体芯片(S2)时，分别从晶片上切下半导体芯片并且将其装配到晶片座的下部。
在进行导线接合加工(S3)时，进行导线接合以便将半导体芯片电连接到导线或晶片座。
在模塑加工(S4)中，进行模塑加工以便将半导体芯片和导线接合导线架封装在导线架板单元中。如上所述，在这种情况下，防止了坝条的变形，从而在上部和下部模具之间精确形成了凹陷。因此，可以防止模塑溢料的出现。
在切割加工(S5)中，以半导体封装为单元切割封装的导线架，从而完成不出现模塑溢料的半导体封装。
在切割加工(S5)中，沿着在线上的坝条之上或之中形成的多个凹槽或孔将封装的导线架板切割成半导体封装单元。如果沿着凹槽或孔切割导线架板，可以防止半导体封装的切割部分的毛边的出现。
统计测量表明，使用传统导线架制造半导体封装的方法所制造的半导体封装有35％出现模塑溢料，而使用基于本发明的半导体封装制造方法所制造的半导体封装有4％出现模塑溢料。也就是说，基于本发明的半导体封装制造方法显著降低了模塑溢料的出现。
如上所述，通过基于本发明的导线架和制造使用该导线架的半导体封装的方法，可以使用MAT方法制造出模塑溢料的产生得到抑制的半导体封装。
此外，根据本发明，不需要用于清除模塑溢料的其它加工和成本，于是降低了半导体封装的制造成本。
虽然前面参照优选实施例示出和描述了本发明，然而本领域的技术人员可以理解，在不偏离所附权利要求书限定的本发明的宗旨和范围的前提下，可以进行各种形式和细节方面的改变。

Claims (14)

1.一种导线架带，包括：
至少一个导线架板，在该导线架板中多个单元导线架以矩阵形式彼此连接，
其中各个单元导线架包含：
晶片座，其中半导体芯片将被装配在该晶片座上；
系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；
多个导线，处于和系筋的另一端相同的水平并且从系垫延伸预定距离；
横过导线形成并且与导线整合以支撑导线的坝条，
其中沿着导线架板的边缘形成沟槽，该沟槽充当缓冲带，并且
在沟槽上横向形成连接带以支撑导线架板。
2.如权利要求1所述的导线架带，其中晶片座一侧装配半导体芯片，而另一侧暴露到外部。
3.如权利要求1所述的导线架带，其中在坝条的延伸线上形成连接带。
4.如权利要求3所述的导线架带，其中连接带具有弯曲部分。
5.如权利要求2所述的导线架带，其中坝条在线上包含多个凹槽。
6.如权利要求3所述的导线架带，其中坝条在线上包含多个凹槽。
7.如权利要求4所述的导线架带，其中坝条在线上包含多个凹槽。
8.制造半导体封装的方法，包括：
制备导线架带，该导线架带包含至少一个导线架板，在该导线架板中多个单元导线架以矩阵形式彼此连接，其中各个单元导线架均具有将装配半导体芯片的晶片座；系筋，其中系筋的末端被连接到晶片座并且被加工成下设的形式；多个导线，处于和系筋的另一端相同的水平并且从系垫延伸预定距离；横过导线而形成并且与导线整合以支撑导线的坝条，其中沿着导线架板的边缘形成沟槽，沟槽充当缓冲带，并且在沟槽上横向形成连接带以支撑导线架板；
向晶片座装配半导体芯片；
在半导体芯片和导线之间，及半导体芯片和晶片座之间进行导线接合；
用树脂模塑导线架带，导线架带装配有半导体芯片并且与导线接合以形成封装；和
以半导体封装为单元切割塑模的导线架带。
9.如权利要求8所述的方法，其中晶片座一侧装配半导体芯片，而另一侧暴露到外部。
10.如权利要求8所述的方法，还包括在制备导线架带期间半蚀刻导线架带以便在线上的坝条中形成凹槽。
11.如权利要求9所述的方法，还包括在制备导线架带期间半蚀刻导线架带以便在线上的坝条中形成凹槽。
12.如权利要求10所述的方法，其中当以半导体封装为单元切断塑模的导线架带时，沿着多个凹槽切断塑模的导线架带。
13.如权利要求8所述的方法，其中在制备导线架带期间，该方法还包括对导线架带进行蚀刻或打孔以便在线上的坝条中形成多个孔。
14.如权利要求13所述的方法，其中当将塑模的导线架带切割成半导体封装单元时，沿着多个孔切割导线架带。
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