CN100407413C - 电路基板、焊球网格阵列的安装结构和电光装置 - Google Patents

电路基板、焊球网格阵列的安装结构和电光装置 Download PDF

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CN100407413C
CN100407413C CN200310100242XA CN200310100242A CN100407413C CN 100407413 C CN100407413 C CN 100407413C CN 200310100242X A CN200310100242X A CN 200310100242XA CN 200310100242 A CN200310100242 A CN 200310100242A CN 100407413 C CN100407413 C CN 100407413C
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mentioned
semiconductor element
pad
solder flux
mounting structure
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CN1497709A (zh
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芦田刚士
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BOE Technology Group Co Ltd
BOE Technology HK Ltd
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Seiko Epson Corp
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Abstract

本发明提供了一种即使在通过回流处理将焊球网格阵列安装到电路基板上的情况下,也能够增大焊料的印刷余量的电路基板、焊球网格阵列的安装结构和电光装置以及电子设备。在包含用于安装焊球网格阵列的焊盘和布线的电路基板、焊球网格阵列的安装结构和电光装置以及电子设备中,电路基板包含用于安装焊球网格阵列的焊盘、用于连接该焊盘和外部端子的布线和抗焊剂,该抗焊剂具有用于使焊盘和布线一并露出的开口部。

Description

电路基板、焊球网格阵列的安装结构和电光装置
技术领域
本发明涉及电路基板、焊球网格阵列的安装结构和电光装置以及电子设备。特别是涉及即使在利用回流处理将焊球网格阵列安装到电路基板上时,也可以增大焊料的印刷余量的电路基板、焊球网格阵列的安装结构和电光装置以及电子设备。
背景技术
以往,作为与半导体元件的引线端子的细间距化、多针化对应的安装方法,广泛应用在印刷电路板(PCB)上搭载QFP(四边扁平封装,クアツド·フラツト·パツケ一ジ)的方法。这是将在封装的4边具有多个鸥翼(ガルウイング)型的引线端子的作为扁平封装的QFP安装到通常由树脂等构成的PCB上,同时,在实现与PCB的导体部的电气连接的状态下使用的方法。
但是,有人指出QFP存在有随着进一步的细间距化、多针化,由于安装时的焊料桥接引起的短路、焊料不足等,会产生连接可靠性下降的问题。另外,QFP还存在有由于引线端子比封装向外侧突出,致使PCB上的安装面积增大的问题。
因此,为了适应半导体元件的进一步细间距化、多针化,已提案了使用焊球网格阵列(以下称为BGA)、芯片尺寸封装(以下称为CSP)的安装方法、以及安装它们的印刷电路板。
具体而言,如图25所示,有在相同的印刷电路板上分别配置形状不同的半导体封装的焊点(焊接区,ランド)381、382、并用图案布线383将用于使在每个封装中具有相同功能的端子连接的焊点相互连接起来的印刷电路板。按照这样的印刷电路板,即使搭载在印刷电路板上的封装的形状发生变更,也可以不必制造新的另外的印刷电路板而用相同的印刷电路板进行搭载。
另外,还有将BGA等更换维修困难的电子器件加以处理以免发生焊接不良的的安装方法。更具体而言,如图26的流程图所示,安装方法290包括:将焊膏印刷在PCB上的规定地方的工序291、将BGA(包括间距为0.8mm或以下的芯片尺寸封装(CSP))等的带凸块的半导体元件通过管脚(マウンタ一)搭载到印刷有焊膏的PCB上的规定地方的工序292、进行X线检查以分选半导体元件的良品和不良品的工序293、以及仅对X线检查合格的半导体元件中的良品进行回流加热安装的工序294。
另外,如图27(a)~(d)所示,还有使用将焊膏312涂布到在基板310上设置的凹部311的方法的BGA的安装方法。
更具体而言,BGA的安装方法的特征在于:如图27(a)所示,准备表面具有多个凹部311的基板310,如图27(b)所示,对多个凹部311涂布焊膏312,如图27(c)所示,使BGA315的凸块317与多个凹部311的位置对齐,进而,如图27(d)所示,进行回流安装、压紧固定。
另外,如图28(a)~(c)所示,还有借助各向异性导电膜(AnisotropicConductive Film,以下称为ACF)347将带凸块的半导体元件346与基板343的焊盘341进行热压固定的安装方法。
按照这种由ACF347进行的安装方法,即使在如CSP那样凸块(バンプ)347的间距窄到0.1~0.5mm左右的情况下,也能够得到可有效地防止相邻的凸块间的短路发生,并同时可一并地将多个凸块347电气连接的优点。
但是,以往的印刷电路基板存在有以下问题,在安装BGA等带细微的凸块的半导体元件时,必须将作为导电材料的焊料正确地印刷到细微的焊点(焊盘)上,因此,印刷的对位、印刷本身都需要时间,另一方面,印刷后的焊料的位置容易与焊盘发生偏离。特别是在使用CSP的情况下,因为比BGA更细间距化,所以,要将焊料高精度地印刷到FPC等容易变形的印刷电路基板的焊点(焊盘)上进行安装,事实上是很困难的。
另外,按照图26所示的安装方法,在进行回流加热之前,必须进行X线检查,工序数增多,同时存在制造管理复杂化、制造时间延长等问题。另外,必须将焊膏正确地印刷到细微的焊盘上,所以,印刷的对位、印刷本身都需要时间。
另外,按照图27所示的安装方法,不仅形成具有凹部的焊盘比较困难,而且必须对具有细微的凹部的焊盘正确地进行印刷,所以,印刷的对位、印刷本身反而更需要时间。
此外,使用ACF的安装方法,还存在有不仅该ACF的成本高,而且难以与其他元件同时安装的问题。即,进行热挤压固定安装的ACF与通过焊料回流处理安装的其他元件必须考虑不同的安装工序的顺序,单独地加以实施。
发明内容
因此,锐意研究上述问题之后发现,通过设置具有以使与BGA连接的全部或一部分焊盘及布线一并露出的方式进行开口的开口部的抗焊剂,可以增大焊料的涂布余量(印刷余量),从而不易发生因在抗焊剂的阶差处产生毛刺等引起的印刷的塌陷等现象,因此,焊料的涂布精度高,并且变得容易。另外,虽然还要考虑因焊料的印刷偏离引起的连接不良现象,但在这种情况下,抗焊剂本身的偏离、不位阶差所左右而由于印刷偏离而从焊盘溢出的焊料,由于其流动特性,在回流时将流回到焊盘上。
即,本发明的目的旨在提供一种即使在利用焊料通过回流处理安装BGA(包括CSP)时,因焊料的涂布不良引起的BGA的安装位置偏离很少的电路基板、利用该电路基板的BGA的安装结构和电光装置以及电子设备。
按照本发明,提供一种电路基板,该电路基板在包含用于安装BGA的焊盘、用于连接该焊盘和外部端子的布线、以及抗焊剂,其特征在于抗焊剂具有用于使焊盘和布线一并露出的开口部,可以解决上述问题。
即,通过采用这样的结构,焊料的涂布容易,并可以增大焊料的涂布余量。
另外,在构成本发明的电路基板时,优选为在将所安装的BGA的面积设为100%时,将开口部的面积设为50~150%的范围内的值。
通过采用这样的结构,焊料的涂布容易,并可以增大焊料的涂布余量。
另外,在构成本发明的电路基板时,优选为在安装BGA的地方中,在从其外周向内侧区域0.1mm的地方,存在抗焊剂或其端部。
通过采用这样的结构,由于在BGA的端部存在抗焊剂,所以,能够有效地防止边缘短路。
另外,在构成本发明的电路基板时,优选为在混合存在所安装的BGA的凸块的间距小于0.6mm的窄的地方和大于或等于0.6mm的宽的地方时,与对应于该BGA的窄的地方的焊盘相对应地设置抗焊剂的开口部。
通过采用这样的结构,即使凸块的间距宽窄不同,也可以很容易地实施电路基板的设计。
另外,在构成本发明的电路基板时,优选为将抗焊剂的厚度设置为所安装的BGA的凸块高度的1~50%。
通过采用这样的结构,可以得到优异的抗焊剂效果、边缘短路的防止效果,同时可以很容易地形成抗焊剂。
另外,在构成本发明的电路基板时,优选为设置用于安装BGA以外的电气元件的焊盘,且抗焊剂靠近该焊盘的周围而存在。
通过采用这样的结构,即使是BGA以外的电气元件,也可以与BGA一起容易且同时地进行安装。
另外,本发明的其他的形式提供一种BGA的安装结构,该安装结构是将BGA安装到电路基板上的BGA的安装结构,其特征在于电路基板包含用于安装BGA的焊盘、布线和抗焊剂,同时,该抗焊剂具有用于使焊盘及布线一并露出的开口部,可以解决上述问题。
即,通过采用这样的结构,涂布焊料时的余量增宽,即使在对电路基板安装BGA或CSP时也可以减少安装位置的偏离。
另外,在构成本发明的BGA的安装结构时,优选为将具有以下的特性的底层填料填充到BGA与电路基板之间:
(1)体电阻为1×106~1×1020Ω·cm范围内的值;
(2)抗拉强度为1~200Mpa范围内的值;
(3)延伸率为10~500%范围内的值。
通过采用这样的结构,可以提供环境稳定性、机械特性优异的BGA的安装结构。
另外,本发明的其他的形式是提供一种电光装置,其特征在于作为驱动元件或电源元件,包含安装在电路基板上的BGA,该电路基板由用于安装BGA的焊盘、用于连接该焊盘和外部端子的布线、及具有用于使该焊盘和布线一并露出的开口部的抗焊剂构成,可以解决上述问题。
即,通过采用这样的结构,可以有效地提供利用了BGA的安装位置偏离很少的电路基板的电光装置。
另外,本发明的其他的形式是提供一种电子设备,其特载在于具有上述电光装置和用于控制该电光装置的控制装置,可以解决上述问题。
即,通过采用这样的结构,可以有效地提供包含利用了BGA的安装位置偏离少的电路基板的电光装置的电子设备。
附图说明
图1是用于说明实施例1的电路基板的图。
图2是用于说明电路基板上的抗焊剂的位置的剖面图(之一)。
图3是用于说明电路基板上的抗焊剂的位置的剖面图(之二)。
图4是用于说明将BGA与其他电气元件一起对电路基板同时安装的方法的图。
图5是用于说明FPC的图。
图6是用于说明相邻的焊盘间的距离的图(之一)。
图7是用于说明相邻的焊盘件的距离的图(之二)。
图8是表示焊盘的平面形状的图。
图9(a)~(d)分别是表示变形焊盘的平面形状的图。
图10(a)~(c)分别是表示变形焊盘的平面形状的图。
图11(a)~(b)分别是表示变形焊盘的平面形状的图。
图12是用于说明BGA的结构的剖面图(之一)。
图13是用于说明另一BGA的结构的剖面图(之二)。
图14是用于说明另一BGA的结构的剖面图(之三)。
图15是用于说明WCSP的结构的剖面图。
图16(a)~(b)是用于说明带凸块的半导体元件中的凸块的变形例的图。
图17是用于说明实施例2的带凸块的半导体元件的安装结构的图。
图18是用于说明底层填料的图。
图19(a)~(b)是用于说明对电路基板安装BGA的方法的工序图(之一)。
图20(a)~(b)是用于说明对电路基板安装BGA的另一方法的工序图(之二)。
图21(a)~(b)是用于说明对电路基板安装带凸块的半导体元件的另一方法的工序图(之三)。
图22是表示本发明实施例3的液晶面板的外观的概略立体图。
图23是示意地表示实施例3的面板结构的概略剖面图。
图24是表示本发明的电子设备的实施例的方块结构的概略结构图。
图25是用于说明以往的电路基板的图。
图26是用于说明以往的BGA的安装方法的流程图。
图27是用于说明以往的利用在PCB上设置的凹部的BGA的安装方法的图。
图28是用于说明利用各向异性导电膜(ACF)的带凸块的半导体元件的安装方法的图。
标号说明
11            带凸块的半导体元件(BGA或CSP)
12            夹具
13            凸块
15            焊料
17            焊盘
19            基板(FPC)
39            带凸块的半导体元件以外的电气元件
60、70、80    BGA
64            底层填料
90            WCSP
110、130   带凸块的半导体元件(BGA或CSP)
113        凸块
140        FPC
200        液晶面板
211        第1基板
221        第2基板
222        透明电极
227        带凸块的半导体元件
360、370   安装结构
411        布线
413        焊盘
430        电路基板
431        抗焊剂
433        开口部
具体实施例
下面,参照附图具体说明关于本发明的电路基板、BGA的安装结构和使用该BGA的安装结构的电光装置以及电子设备的实施例。
但是,有关实施例的说明是表示本发明的一个例子的,显然不是对本发明的限定,在本发明的目的的范围内可以任意加以变更。
实施例1.
如图1所示,实施例1是包含用于安装BGA的焊盘413a、用于连接该焊盘413a和外部端子的布线411和抗焊剂431的电路基板,其特征在于抗焊剂431具有使焊盘413a和布线411一并露出的开口部433。
1.电路基板
(1)抗焊剂
①开口部的面积
在将所安装的BGA的面积设为100%时,优选为将抗焊剂的开口部的面积设置为50~150%的范围内的值。
其理由在于,当这样的抗焊剂的开口部的面积为小于50%的值时,在设计焊盘、布线时,有时将受到过度的限制。另一方面,当这样的抗焊剂的开口部的面积超过150%时,有时在安装BGA时难以有效地防止边缘短路的发生。另外,当抗焊剂的开口部的面积超过100%时,有时也容易发生边缘短路,但是,通过调整凸块的高度、或注入底层填料等,可以有效地防止。
因此,在将所安装的BGA的面积设置为100%时,更优选为将抗焊剂的开口部的面积设置为60~99%的范围内的值,再进一步优选为设置为70~90%的范围内的值。
②位置1
另外,如图2所示,在安装BGA11的地方,优选为在从其外周向内侧区域至少0.1mm的地方存在抗焊剂431或其端部。
其理由在于,在安装BGA的地方,如果从其外周向内侧区域至少0.1mm的地方不存在这样的抗焊剂或其端部,就存在有在安装BGA时就难以有效地防止边缘短路的发生的问题。
但是,如果从外周向内侧区域过分地存在抗焊剂,就会出现在设计焊盘、布线时将受到过分的限制等问题。
因此,在安装BGA的地方,更优选为在从其外周向内侧区域0.11mm~1mm的地方存在抗焊剂或其端部,进一步优选为在从其外周向内侧区域0.15mm~0.5mm的地方存在抗焊剂或其端部。
③位置2
另外,如图3所示,混合存在所安装的BGA11的凸块13的间距小于0.6mm的窄的地方和大于或等于0.6mm的宽的地方时,优选为仅对与该BGA11的凸块13的窄的间距相对应的焊盘17设置抗焊剂431的开口部433。
其理由在于,通过采用这样的结构,即使凸块的间距有宽有窄,通过对与BGA的窄的间距相对应的焊盘设置开口部也能够适应,所以,电路基板的设计容易。即,在与BGA的宽的间距相对应的焊盘处不必设置开口部,也可以较宽地获得焊料的涂布余量。
④厚度
另外,如图2所示,优选将抗焊剂431的厚度设置为安装的BGA11的凸块13的高度的1~50%。
其理由在于,通过这样限制抗焊剂的厚度,可以得到优异的抗焊剂效果、对边缘短路的防止效果,同时可以很容易地形成抗焊剂。
因此,更优选将抗焊剂的厚度设置为安装的BGA的凸块高度的1~40%,进一步优选设置为1~30%。
⑤其他开口部
另外,如图4所示,优选为设置有用于安装BGA以外的电气元件39的焊盘38,抗焊剂431靠近该焊盘38的周围而存在。
其理由在于,通过采用这样的结构,在将BGA以外的电气元件安装到电路基板上时,可以与BGA一起很容易且同时地进行安装。
(2)电路基板
①种类
作为电路基板的种类,无论是刚性的玻璃环氧树脂制的PCB、陶瓷制的PCB等都没有特别限制,不过更轻量且薄型的,并且有可以弯曲使用形式的,能够较佳地应用于便携式电话等的用途,所以,如图5所示,更优选为在聚酰亚胺树脂、聚酯树脂等的基材上形成有金属布线的FPC。
即,如图5所示,其原因在于,通过使用在柔性基材141上具有多个焊盘147、同时在两端具有链轮的FPC140,可以连续地安装带凸块的半导体元件。
②焊盘的间距1
另外,如图6所示,在将焊盘413a的间距定义为从焊盘间的中心位置到相邻的焊盘间的中心位置的距离——即CTC(Center to Center)时,优选为将该焊盘的间距设置为0.4~1.0mm的范围内的值。
其理由在于,当这样的焊盘的间距为小于0.4mm的值时,会出现布线的迂回(引回)困难、必须使布线的宽度过度地窄、甚至焊料桥接现象频繁发生等问题。
另一方面,当这样的焊盘的间距超过1mm时,会出现焊盘数受到过度的限制,或难以安装多针的BGA、CSP等问题。
因此,更优选为将焊盘的间距设置为0.45~0.8mm的范围内的值,进一步优选设置为0.5~0.6mm的范围内的值。
③焊盘的间距2
另外,如图7(a)所示,优选为在BGA的底面433的中央附近,设置纵向的焊盘的间距与横向的焊盘的间距不同的区域433a。
其理由在于,配线的迂回有时集中在BGA的底面的中央附近,但是,即使在这种情况下,通过设置间距不同的区域,可以优先从纵向和横向中的任意一个具有较宽的间距的方向引出布线。
另一方面,如图7(b)所示,优选为在BGA的底面433的周边附近,设置纵向的焊盘的间距与横向的焊盘的间距不同的区域433b。
其理由在于,向外部的配线的迂回有时集中在BGA的底面的周边附近,但是,即使在这种情况下,通过设置间距不同的区域,可以优先从纵向和横向中的任意一个具有较宽的间距的方向引出布线。
④焊盘的面积
另外,优选为将焊盘的面积设置为0.01~0.5mm2的范围内的值。
其理由在于,当这样的焊盘的面积小于0.01mm2时,就会出现焊料的涂布变得很困难、或者与BGA的电气连接性就不稳定等问题。
另一方面,当这样的焊盘的面积大于0.5mm2时,就会出现布线的迂回变得困难、使布线的宽度过窄、甚至焊料桥接的现象频繁发生等问题。
因此,更优选为将焊盘的面积设置为0.03~0.3mm2的范围内的值,进一步优选设置为0.05~0.1mm2的范围内的值。
⑤焊盘的平面形状
另外,如图8所示,优选为将焊盘的平面形状设为圆形或正方形。其理由在于,通过采用这样的平面形状,可以重复性良好地加以形成,同时能够有效地利用整个面。
但是,也可以优选为将焊盘的平面形状设为非圆形或非正方形。例如,优选设为图9(a)所示的椭圆、图9(b)所示的菱形、图9(c)所示的变形长方形(H形)、图9(d)所示的鼓形、图10(a)所示的半椭圆(椭圆的一半)、图10(b)所示的半菱形(菱形的一半)、图10(c)所示的半鼓形(鼓形的一半)、图11(a)所示的半圆(圆形的一半)、或图11(b)所示的半多边形(多边形的一半)或者1/3圆、2/3圆、1/5圆、2/5圆、3/5圆、4/5圆等中的至少一种形状。
其理由在于,通过设成具有这样的平面形状的变形焊盘,可以减少阻碍布线的迂回的几率,同时可以较宽地确保涂布焊料时的位置偏离的余量,从而可以提高电路基板的生产效率。另外,如果是这样的平面形状的焊盘,就可以重复性良好地加以形成。
2.BGA
(1)种类
本发明使用的BGA的种类没有特别限制,但为了容易与布线的细间距化、多针化相适应,例如,优选为使用图12~图14所示的BGA60、70、80或图15所示的晶片级芯片尺寸封装(WCSP)90。
这里,图12所示的BGA60是由裸芯片61、用于通过引线键合68搭载裸芯片61的插入件(インタ一ポ一ザ一)63和在插入件63的背面呈间距约0.6~2.54mm的区域阵列状地配置的凸块(焊料球)65构成的带凸块的半导体元件。
另外,图13表示通过在裸芯片61的键合区(点)75上预先形成凸块71、并利用由加热进行的焊料回流、或在加压的状态下使用超声波振动与基板63上的内部引线(图未示)连接的所谓的倒装片方式所得到的BGA70。
另外,图14表示利用预先在裸芯片61上或磁带上的内部引线上形成凸块并通过内部引线键合而相互连接的所谓的TAB(Tape AutomatedBonding,带式自动键合)方式所得到的BGA80。
另一方面,如图15所示,WCSP是不通过插入件而在晶片阶段形成布线103、电气绝缘膜97及107、和配置成间距约0.1~1.0mm的区域阵列状的凸块(焊料球)93的CSP。特别是薄型、轻量,且最适合于希望紧凑的安装结构的情况的带凸块的半导体元件。
(2)凸块
另外,在BGA上设置的凸块的形式,并没有特别限制,但是,例如,如图16(a)所示,优选为将凸块113的前端部设成平坦的形状。
其理由在于,在使BGA与基板的焊盘上位置对齐搭载时,可以使其在焊盘的周围均匀地流动,从而可以将BGA的凸块与焊盘牢固地固定。
另外,在BGA上设置的凸块的形式,如图16(b)所示,优选为在凸块113的前端部的表面设置凹部。
其理由在于,通过采用这样的结构,可以使焊料借助凹部可靠地存在于BGA的凸块和焊盘之间,从而可以将这些部件牢固地固定。
(3)焊料
①种类
作为附着到凸块上的焊料的种类,并没有特别限制,可以使用例如由Sn、Pb/Sn等构成的以往所广泛使用的焊料、松香、松脂等焊剂材料,但更优选使用由不包含Pb的Cu/Sn/Ag构成的焊料与焊剂材料的组合。
实施例2.
如图17所示,实施例2是对电路基板361安装BGA63而构成的BGA的安装结构360,上述电路基板361包含用于安装BGA63的焊盘363、布线(图未示)和抗焊剂367,且上述抗焊剂367具有以使连接到BGA63上的全部或一部分焊盘363及布线露出的方式一并进行开口而成的开口部369。
下面,与实施例1相同的地方适当地省略,以实施例中特征性的地方为中心进行说明。
1.结构
(1)基本结构
实施例2的BGA的安装结构360,基本上可以由BGA63、电路基板361、焊料365构成,而对于BGA63、电路基板361及焊料365,可以分别与实施例1具有相同的内容,所以,此处的说明省略。
(2)底层填料
另一方面,在实施例2中,如图15所示,优选为将具有以下特性的底层填料64填充在带凸块的半导体元件(BGA)与电路基板361之间:
1)体电阻为1×106~1×1020Ω·cm范围内的值;
2)抗拉强度为1~200Mpa范围内的值;
3)延伸率为10~500%范围内的值。
下面,详细说明优选的的底层填料的种类、特性等。
①种类
关于底层填料的种类,优选为热硬化性树脂及光硬化性树脂、或者任意一方的硬化性树脂。
其理由在于,通过使用这样的硬化性树脂,可以很容易满足有关机械特性、耐湿性的作为底层填料的基本特性。
另外,作为热硬化性树脂,优选使用例如环氧树脂、硅树脂,作为光硬化性树脂,优选使用例如环氧树脂、丙烯酰基树脂及硅树脂。
另外,在希望使底层填料具有遮光性时,优选在这些硬化性树脂中添加例如碳粒子、碳纤维、颜料等遮光物质,或者添加紫外线吸收剂、荧光增白剂等。
通过添加这样的化合物,在光从外部侵入时可以有效地进行吸收、或者将从外部侵入的光的波长变换为不会发生光误动作的波长的光。
②体电阻
另外,优选将底层填料的体电阻设置为1×106~1×1020Ω·cm范围内的值。
其理由在于,当这样的底层填料的体电阻为小于1×106Ω·cm的值时,会出现相邻的凸块间的电气绝缘性不充分的情况,另一方面,当这样的底层填料的体电阻超过1×1020Ω·cm时,就存在有可使用的材料的选择的余地将明显受到限制的问题。
因此,更优选将底层填料的体电阻设置为1×108~1×1018Ω·cm范围内的值,进一步优选设置为1×1010~1×1016Ω·cm范围内的值。
③抗拉强度
另外,优选为将底层填料的抗拉强度设置为1~200Mpa范围内的值。
其理由在于,当这样的底层填料的抗拉强度为小于1Mpa的值时,会出现机械强度下降,带凸块的半导体元件的安装结构的电阻稳定性、耐热性下降的问题。另一方面,当这样的底层填料的抗拉强度超过200Mpa时,会出现可以使用的材料的选择的余地将明显受到限制、过度地发生应力畸变而使带凸块的半导体元件的安装结构的电阻稳定性下降等问题。
因此,更优选为将底层填料的抗拉强度设置为5~100Mpa范围内的值,进一步优选设置为10~50Mpa范围内的值。
④延伸率
另外,优选为将底层填料的延伸率设置为10~500%范围内的值。
其理由在于,当这样的底层填料的延伸率为小于10%的值时,会出现柔软性下降,带凸块的半导体元件的安装结构的电阻稳定性、耐热性下降的问题。另一方面,当这样的底层填料的延伸率超过500%时,就会出现可以使用的材料的选择的余地将明显受到限制、机械强度下降等问题。
因此,更优选为将底层填料的延伸率为30~300%范围内的值,进一步优选设置为50~200%范围内的值。
2.安装方法
(1)第1安装方法
作为第1安装方法,优选按照下述工序(A)和(B),如图19所示,将BGA63安装到具有抗焊剂367的电路基板361上。
(A)将焊料365涂布到具有抗焊剂367的电路基板361中的焊盘363上的工序;
(B)通过回流处理将BGA63安装到涂布有焊料365的焊盘363上的工序。
通过这样实施,可以使用以往的涂布装置——例如丝网印刷装置来涂布焊料,同时,可以使用以往的回流装置将BGA安装到电路基板上。
另外,优选为在使BGA与基板上的焊盘位置对齐后进行回流处理。这种情况下,优选为在BGA上预先设置对位标记,以其为目标使BGA对准在焊盘上。
(2)第2安装方法
作为第2安装方法,优选按照下述工序(A’)和(B’),如图20所示,将BGA11安装到具有抗焊剂431的电路基板19上。
(A’)将焊料15涂布到BGA11的凸块13上的工序;
(B’)利用回流处理将涂布有焊料15的BGA11安装到焊盘17上的工序。
通过这样实施,可以省略将焊料涂布到焊盘上时的定位工序,同时,即使对于FPC等比较容易变形的基板也可以高精度地对BGA进行回流安装。即,能够提供一种可迅速且廉价地将BGA、CSP回流安装到基板、特别是FPC上,并且安装不良的发生少的BGA的安装方法。
(3)第3安装方法
作为第3安装方法,优选按照下述工序(A”)、(A”’)和(B’),如图21所示,将BGA11安装到具有抗焊剂431的电路基板19上。
(A”)将焊料的一部分21涂布到电路基板19中的焊盘17上的工序;
(A”’)将焊料的另一部分15涂布到BGA11中的凸块13上的工序;
(B’)利用回流处理将涂布有一部分焊料15的BGA11安装到涂布有一部分焊料21的焊盘17上的工序。
通过这样实施,能够提供一种可高精度地将BGA回流安装到基板、特别是FPC上,并且可牢固地安装的BGA的安装方法。
(4)回流处理条件
另外,在实施第1~第3安装方法时,作为回流处理条件,并没有特别限制,但优选为使用例如红外线、热惰性气体,在峰值温度为200~300℃、同时5秒~10分钟的条件下进行加热。
另外,在回流处理中,为了避免焊料氧化,优选在惰性状态下进行回流处理。
(5)与其他元件的同时安装
另外,在实施第1~第3安装方法时,如图4所示,优选将BGA11与包含电容器的其他电气元件39一起,同时安装到具有抗焊剂431的电路基板19上。
其理由在于,通过将BGA与包含电容器等的其他电气元件一起同时进行安装,可以减少由回流处理以外的ACF等带来的安装工序。因此,可以使BGA的安装工序总体上简洁化和迅速化。
另外,通常,BGA以外的电气元件,例如电容器、电阻元件,通过回流处理进行安装,但对于BGA则利用ACF等进行安装,所以就出现了必须分别利用不同的安装方法进行安装的问题。
实施例3.
实施例3是电光装置,其特征在于作为驱动元件或电源元件,包含被安装到电路基板上的BGA,上述电路基板包含用于安装BGA的焊盘、布线和抗焊剂,且具有以使与BGA连接的全部或一部分焊盘和布线露出的方式一并地进行开口而成的开口部。
下面,以构成图22所示的电光装置的液晶面板为例进行说明。
首先,参照图23对图22所示的液晶面板200的概略结构进行说明。图23是示意地表示图22所示的液晶面板200中的半导体元件(IC)和柔性电路基板(FPC)安装前的状态的图,图面上的尺寸根据图示的需要适当地进行了调整,构成要素也适当地省略。
另外,液晶面板200是将在第1基板211上在反射层212、多个着色层214、表面保护层215的层积结构上形成透明电极216而成的彩色滤光片基板210和与其相对的对向基板220通过密封部件230相互粘贴,并在内部配置液晶材料232而构成的。该透明电极216如上所述地与布线218A连接,该布线218A通过密封部件230与第1基板211之间而引出到基板引出部210T的表面上。另外,在基板引出部210T上还形成有输入端子部219。
并且,基板引出部210T的特征在于,由用于安装BGA的焊盘、用于连接该焊盘和外部端子的布线、和具有使该焊盘和布线一并露出的开口部的抗焊剂构成,且作为液晶面板200的驱动元件或电源元件,包含BGA227。
从而能够提供一种可对基板引出部210T上的焊盘高精度、且宽余量地涂布焊料,从而即使在安装作为带细微的凸块的半导体元件的BGA时,因涂布位置的不良引起的BGA的位置偏离也很少的基板引出部210T。
因此,BGA的液晶驱动稳定,同时,对于液晶面板,能够获得优异的耐久性等。
实施例4.
下面,具体说明将本发明的电光装置作为电子设备的显示装置使用时的实施例。
(1)电子设备的概要
图24是表示本实施例的电子设备的整体结构的概略结构图。该电子设备具有液晶面板180和用于控制该液晶面板180的控制装置190。另外,在图24中,是将液晶面板180概念性地分为面板构造体180A和由半导体IC等构成的驱动电路180B来描绘的。
另外,控制装置190优选为具有显示信息输出源191、显示处理电路192、电源电路193及定时信号发生器194。
另外,显示信息输出源191优选为具有由ROM(Read Only Memory)、RAM(Random Access Memory)等构成的存储器、由磁盘、光盘等构成的存储单元、以及调谐输出数字图像信号的调谐电路,并以根据由定时信号发生器194生成的各种时钟信号将显示信息以规定格式的图像信号等形式供给给显示信息处理电路192的形式构成。
另外,显示信息处理电路192优选为具有串-并变换电路、放大反相电路、旋转电路、伽马修正电路和箝位电路等众所周知的各种电路,进行输入的显示信息的处理,将该图像信息与时钟信号CLK一起向驱动电路180B供给。并且,驱动电路180B优选为包含扫描线驱动电路、数据线驱动电路及检查电路。另外,电源电路193具有分别向上述各结构要素供给规定的电压的功能。
(2)具体例
作为可以应用作为本发明的电光装置的液晶显示装置、有机场致发光装置、无机场致发光装置等、使用了等离子体显示装置、FED(场致发射显示器)装置、LED(发光二极管)显示装置、电泳显示装置、薄型显像管、液晶光闸、数字微镜器件(DMD)的装置等的电子设备,除了个人计算机、便携式电话外,还可以列举有液晶电视、取景器型/监视器直视型的摄像机、汽车驾驶导向装置、呼机、电子记事簿、电子计算器、文字处理机、工作站、可视电话、POS终端、具有触摸面板的电子设备等。
此外,本发明的电光装置和电子设备,不限于上述图示例,在不脱离本发明的主旨的范围内可以进行各种变更。例如,上述各实施例所示的液晶面板具有单纯矩阵型的结构,但也可以应用于使用了TFT(薄膜晶体管)、TFD(薄膜二极管)等有源器件(主动器件)的有源矩阵方式的电光装置。
如上所述,按照本发明的电路基板,通过具有设置了用于使焊盘和布线一并露出的开口部的抗焊剂,能够提供一种可对电路基板上的焊盘高精度、且宽余量地涂布焊料,BGA的安装位置偏离少的电路基板。
另外,按照本发明的BGA的安装结构,通过使用具有用于使焊盘和布线一并露出的开口部的电路基板,能够提供一种BGA的安装位置偏离少的安装结构。
进而,按照本发明的电光装置和包含该电光装置的电子设备,通过使用具有用于使焊盘和布线一并露出的开口部的电路基板,可以提供一种不仅焊料不良等现象少、而且生产效率优异的电光装置和包含该电光装置的电子设备。

Claims (8)

1.一种安装结构,是包括具有安装面的电路基板和具有安装在上述安装面上的焊球网格阵列的半导体元件的安装结构,其特征在于:
在上述安装面上至少设置有:与构成上述焊球网格阵列的多个凸块对应、并用于与上述凸块电连接的多个焊盘;与上述多个焊盘连接的多个布线;以及具有比上述半导体元件的外形小的开口部、并且使上述焊盘和上述布线的一部分从上述开口部露出的抗焊剂;
在上述半导体元件被表面安装在上述安装面上的状态下,
在从上述半导体元件的外周向内侧0.1mm的地方,存在上述抗焊剂。
2.根据权利要求1所述的安装结构,其特征在于:在从上述半导体元件的外周向内侧0.11mm~1mm的地方,存在上述抗焊剂或其端部。
3.根据权利要求1所述的安装结构,其特征在于:在从上述半导体元件的外周向内侧0.15mm~0.5mm的地方,存在上述抗焊剂或其端部。
4.根据权利要求1至3任意一项所述的安装结构,其特征在于:上述抗焊剂的厚度是上述凸块高度的1~50%。
5.根据权利要求1至3任意一项所述的安装结构,其特征在于:在上述安装面上设置有用于安装上述半导体元件以外的电气元件的第2焊盘;
上述抗焊剂靠近上述第2焊盘的周围而存在。
6.一种安装结构,是包括具有安装面的电路基板和具有安装在上述安装面上的焊球网格阵列的半导体元件的安装结构,其特征在于:
根据多个凸块的排列构成的上述焊球网格阵列包含由排列间距小于0.6mm的上述多个凸块构成的窄间距区域和由排列间距大于或等于0.6mm的上述多个凸块构成的宽间距区域;
在上述安装面上至少设置有:与上述凸块对应地设置、并用于与上述凸块电连接的多个焊盘;与上述多个焊盘连接的多个布线;以及具有比上述半导体元件的外形小的开口部、并使上述焊盘和上述布线的一部分从上述开口部露出的抗焊剂;
上述抗焊剂以使至少与上述窄间距区域对应的上述安装面从上述开口部露出的方式形成。
7.一种焊球网格阵列的安装结构,是包括在至少一个面上具有焊球网格阵列的半导体元件和将上述半导体元件表面安装在与上述焊球网格阵列相对的安装面上的电路基板而构成的焊球网格阵列的安装结构,其特征在于:
在上述安装面上至少设置有:与构成上述焊球网格阵列的多个凸块对应、并用于与上述凸块电连接的多个焊盘;与上述多个焊盘连接的多个布线;以及具有比上述半导体元件的外形小的开口部,并使上述焊盘和上述布线的一部分从上述开口部露出的抗焊剂;
在上述半导体元件被表面安装在上述安装面上的状态下,上述抗焊剂以使上述开口部收纳于上述半导体元件的外周内的方式形成,进而,在上述半导体元件和上述电路基板之间,填充由热硬化性树脂和/或光硬化性树脂构成的底层填料。
8.根据权利要求7所述的焊球网格阵列的安装结构,其特征在于:上述底层填料的体电阻在1×106~1×1020Ω·cm的范围内;并且,上述底层填料硬化后的抗拉强度以及延伸率分别是1~200Mpa范围内的值和10~500%范围内的值。
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Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4239310B2 (ja) * 1998-09-01 2009-03-18 ソニー株式会社 半導体装置の製造方法
WO2001097277A1 (fr) * 2000-06-16 2001-12-20 Matsushita Electric Industrial Co., Ltd. Procede d'encapsulation de pieces electroniques et une telle encapsulation
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
WO2005048311A2 (en) 2003-11-10 2005-05-26 Chippac, Inc. Bump-on-lead flip chip interconnection
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
TWI293708B (en) * 2004-11-26 2008-02-21 Innolux Display Corp Liquid crystal display and flexible printed circuit using thereof
JP2008535225A (ja) * 2005-03-25 2008-08-28 スタッツ チップパック リミテッド 基板上に狭い配線部分を有するフリップチップ配線
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20070018308A1 (en) * 2005-04-27 2007-01-25 Albert Schott Electronic component and electronic configuration
JP4797482B2 (ja) * 2005-07-20 2011-10-19 ブラザー工業株式会社 配線基板及び配線基板の製造方法
DE102005042083B4 (de) * 2005-09-05 2011-12-01 Infineon Technologies Ag Chipkartenmodul und Verfahren zur Herstellung eines Chipkartenmoduls
DE102006059127A1 (de) 2006-09-25 2008-03-27 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Anordnung optoelektronischer Bauelemente und Anordnung optoelektronischer Bauelemente
JP2009141237A (ja) * 2007-12-10 2009-06-25 Panasonic Corp 半導体装置及びその製造方法
US7791209B2 (en) * 2008-03-12 2010-09-07 International Business Machines Corporation Method of underfill air vent for flipchip BGA
US8022538B2 (en) * 2008-11-17 2011-09-20 Stats Chippac Ltd. Base package system for integrated circuit package stacking and method of manufacture thereof
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
KR101054440B1 (ko) * 2009-04-27 2011-08-05 삼성전기주식회사 전자 소자 패키지 및 그 제조 방법
US20110001230A1 (en) * 2009-07-02 2011-01-06 Conexant Systems, Inc. Systems and Methods of Improved Heat Dissipation with Variable Pitch Grid Array Packaging
CN101996974B (zh) * 2009-08-28 2012-11-28 广达电脑股份有限公司 球栅阵列印刷电路板、其封装结构及其工艺
US20110278054A1 (en) * 2010-05-14 2011-11-17 I-Tseng Lee Circuit board with notched conductor pads
CN102184905A (zh) * 2011-04-26 2011-09-14 哈尔滨工业大学 单金属间化合物微互连焊点结构
US8514386B2 (en) * 2011-05-25 2013-08-20 International Business Machines Corporation Technique for verifying the microstructure of lead-free interconnects in semiconductor assemblies
JP2013004798A (ja) * 2011-06-17 2013-01-07 Murata Mfg Co Ltd 回路基板
CN105448862B (zh) * 2014-09-29 2018-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其制作方法
KR102373722B1 (ko) * 2015-12-30 2022-03-14 에이에스엠엘 네델란즈 비.브이. 직접 기입 마스크리스 리소그래피를 위한 방법 및 장치
US20170245368A1 (en) * 2016-02-18 2017-08-24 Battelle Energy Alliance, Llc. Electronic circuits comprising energetic substrates and related methods
US10042397B2 (en) 2016-02-18 2018-08-07 Battelle Energy Alliance, Llc. Energetic potting materials, electronic devices potted with the energetic potting materials, and related methods
US10177107B2 (en) * 2016-08-01 2019-01-08 Xilinx, Inc. Heterogeneous ball pattern package
KR20210108583A (ko) 2020-02-26 2021-09-03 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
CN111867245A (zh) * 2020-06-05 2020-10-30 深圳市隆利科技股份有限公司 一种MiniLed基板、模组以及模组制作方法
CN112752398A (zh) * 2020-11-24 2021-05-04 广州朗国电子科技有限公司 一种pcb板的芯片焊盘结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297526A (ja) * 1994-04-20 1995-11-10 Nec Niigata Ltd プリント基板
JPH10290058A (ja) * 1997-04-16 1998-10-27 Seiko Epson Corp プリント基板
JPH10294549A (ja) * 1997-04-21 1998-11-04 Nec Eng Ltd プリント配線基板の製造方法及びプリント配線基板
US6431432B1 (en) * 2000-06-15 2002-08-13 Lsi Logic Corporation Method for attaching solderballs by selectively oxidizing traces

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2842704B2 (ja) 1991-04-17 1999-01-06 イビデン株式会社 プリント配線板およびその製造方法
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JPH10163386A (ja) * 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US6050481A (en) * 1997-06-25 2000-04-18 International Business Machines Corporation Method of making a high melting point solder ball coated with a low melting point solder
US6059172A (en) * 1997-06-25 2000-05-09 International Business Machines Corporation Method for establishing electrical communication between a first object having a solder ball and a second object
JPH11163022A (ja) 1997-11-28 1999-06-18 Sony Corp 半導体装置、その製造方法及び電子機器
JP2000031630A (ja) 1998-07-15 2000-01-28 Kokusai Electric Co Ltd 半導体集積回路素子と配線基板との接続構造
TW434767B (en) * 1998-09-05 2001-05-16 Via Tech Inc Package architecture of ball grid array integrated circuit device
US6291899B1 (en) * 1999-02-16 2001-09-18 Micron Technology, Inc. Method and apparatus for reducing BGA warpage caused by encapsulation
JP2000298352A (ja) 1999-04-14 2000-10-24 Jsr Corp 電子部品用材料およびその使用方法
US6204559B1 (en) * 1999-11-22 2001-03-20 Advanced Semiconductor Engineering, Inc. Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking
US6388335B1 (en) 1999-12-14 2002-05-14 Atmel Corporation Integrated circuit package formed at a wafer level
JP3653460B2 (ja) 2000-10-26 2005-05-25 三洋電機株式会社 半導体モジュールおよびその製造方法
US6570259B2 (en) * 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US6622380B1 (en) * 2002-02-12 2003-09-23 Micron Technology, Inc. Methods for manufacturing microelectronic devices and methods for mounting microelectronic packages to circuit boards
US6906425B2 (en) * 2002-03-05 2005-06-14 Resolution Performance Products Llc Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297526A (ja) * 1994-04-20 1995-11-10 Nec Niigata Ltd プリント基板
JPH10290058A (ja) * 1997-04-16 1998-10-27 Seiko Epson Corp プリント基板
JPH10294549A (ja) * 1997-04-21 1998-11-04 Nec Eng Ltd プリント配線基板の製造方法及びプリント配線基板
US6431432B1 (en) * 2000-06-15 2002-08-13 Lsi Logic Corporation Method for attaching solderballs by selectively oxidizing traces

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