CN100407405C - 半导体元件的制造方法 - Google Patents

半导体元件的制造方法 Download PDF

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CN100407405C
CN100407405C CN2006100923958A CN200610092395A CN100407405C CN 100407405 C CN100407405 C CN 100407405C CN 2006100923958 A CN2006100923958 A CN 2006100923958A CN 200610092395 A CN200610092395 A CN 200610092395A CN 100407405 C CN100407405 C CN 100407405C
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李培瑛
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H10B12/05—Making the transistor
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    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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    • H10B12/488—Word lines

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Abstract

本发明提供一种半导体元件的制造方法，其包括提供一具有凹槽栅极(recessed gates)与深沟槽电容元件于衬底之中，其暴露出凹槽栅极的突出部(protrusions)与深沟槽电容元件的上部(upper portions)，且于上部及突出部的侧壁形成间隙壁，并于间隙壁间的间隙形成一由导电材料组成的埋入层(buried portions)，另对衬底、间隙壁、及埋入层进行图案化以形成平行的浅沟槽结构进而定义有源区，以及于浅沟槽结构内形成一介电材料层，而其中部分埋入层可作为埋入插塞(buried contacts)。

Description

半导体元件的制造方法
技术领域
本发明涉及一种半导体元件的制造方法，且更特别地，涉及一种半导体元件的制造插塞的方法。
背景技术
半导体元件，如存储器元件、用以数据储存的动态随机存取存储器(Dynamic Random Access Memory，DRAM)、或其它种类等，为目前所广泛使用，且许多申请案正进行此方面的研究。
然而，传统上制造晶体管及位线插塞的方法需要至少两道光刻工艺，其导致相关光掩模的高制造成本。于四道光刻工艺之间所造成的严重的对准误差，其包含电容、有源区、晶体管、及位线插塞等四道工艺阶段，且亦影响到工艺环境，特别地，随着动态随机存取存储器尺寸的缩减，这种失败率会益趋严重。据此，目前所需的是提供一种存储器元件的字线及位线插塞的制造方法。
发明内容
本发明为提供一种半导体元件的制造方法。本发明的一实施例为提供一种形成半导体元件的方法，其包括提供一具有凹槽栅极与深沟槽电容元件于衬底之中，其暴露出凹槽栅极的突出部与深沟槽电容元件的上部，且于上部及突出部的侧壁形成间隙壁，并于间隙壁间的间隙形成一由导电材料组成的埋入层，另对衬底、间隙壁、及埋入层进行图案化以形成平行的浅沟槽结构进而定义有源区，以及于浅沟槽结构内形成一介电材料层，而其中部分埋入层可作为埋入插塞。
附图说明
图1为一剖面示意图，其绘示依据本发明的实施例所描述的嵌壁式沟槽的制造方法。
图2为一剖面示意图，其绘示依据本发明的实施例所描述具有突出部的嵌壁式晶体管的制造方法。
图3为一剖面示意图，其绘示依据本发明的实施例所描述以间隙壁形成空隙的制造方法。
图4为一剖面示意图，其绘示依据本发明的实施例所描述形成埋入层(埋入位线插塞)的制造方法。
图5为一俯视示意图，其绘示依据本发明的实施例所描述深沟槽电容元件、凹槽栅极、间隙壁、及埋入层的配置态样。
图6为一俯视示意图，其绘示依据本发明的实施例所描述浅沟槽、图案化深沟槽电容元件、图案化凹槽栅极、图案化间隙壁、及图案化埋入层的配置态样。
简单符号说明
100～衬底；            102～深沟槽电容元件；
104～上部；            106～垫层；
108～介电覆盖层；      110～嵌壁式沟槽；
112～嵌壁式晶体管；    114～沟道区域；
116～栅极介电层；      118～凹槽栅极；
120～突出部；          122～外扩散区域；
124～间隙壁；          126～空隙；
128～源极/漏极区域；   130～埋入层；
132～平行浅沟槽；      134a、134b～图案化埋入层；
136～有源区域。
具体实施方式
本发明将通过以下的优选具体实施例而作更进一步地详细说明，但这些具体实施例仅是作为举例说明，而非用以限定本发明的范畴。
本发明说明书中，诸如“存在于衬底上方(overlying the substrate)”、“在层的上方(above the layer)”、或“位于膜上(on the film)”仅表示相对于衬底层的表面的相对位置关系，并无关乎中间层的存在与否。据此，此种表示不仅指出一或多层直接接触的状态，且指出一或多层的未接触状态。
请参考图1，先行形成一衬底100，于衬底100内具有深沟槽电容元件102，且深沟槽电容元件102的上部104乃位于衬底100的表面，垫层106及如氮化硅(SiN)等的介电覆盖层108形成于深沟槽电容元件102上部104的侧壁，介电覆盖层108为具有凹陷区(concave area)，此凹陷区实质上位于两邻近深沟槽电容的上部104之间的中间位置。是以，可对介电覆盖层108、垫层106、及衬底100进行自行对准且蚀刻工艺以形成位于沟槽电容元件102之间的嵌壁式沟槽110。
请参考图2，对邻接嵌壁式沟槽110的衬底100。进行掺杂以形成环绕嵌壁式沟槽110的沟道区域114，接着，形成一栅极介电层116，优选地为包含氧化硅，于衬底100上的嵌壁式沟槽110之内，再填充一导电材料，如多晶硅、钨、硅化钨，于嵌壁式沟槽110以形成凹槽栅极118。于形成栅极介电层116的热工艺及/或其它后续工艺所发生的热工艺其间，随之形成外扩散区域(out diffusion region)122。
对深沟槽电容元件102的上部104、介电覆盖层108、凹槽栅极118的上部进行平坦化工艺，接着，以选择性湿式蚀刻工艺进行介电覆盖层108的移除以显露深沟槽电容元件102的上部104及凹槽栅极118的突出部120。此平坦化方法包括化学机械研磨工艺、毯覆式回蚀刻、或凹蚀蚀刻工艺。凹槽栅极118的突出部120的上表面实质上与深沟槽电容元件102的上部104为同等平面。
请参考图3，间隙壁124形成于上部104及突出部120的侧壁，如此一来，位于其上的间隙壁124间的空隙126则可自行对准，其中间隙壁124可通过沉积及对化学气相沉积氮化硅薄膜进行干式回蚀刻工艺而形成。是以，间隙壁124乃围住上部104及突出部120，且可以深沟槽电容元件102、嵌壁式晶体管112、及位于环形空隙(circular spaces)126外的间隙壁124覆盖衬底100，接着进行离子注入以于嵌壁式沟道区域114的相反侧及其环形空隙126下方形成源极/漏极区域128。
请参考图4及图5，一导电材料层，优选为包含以掺杂的多晶硅或金属，形成于衬底100之上，并填充于间隙壁124间的空隙126。其后，对导电材料层、间隙壁124、深沟槽电容元件102、及凹槽栅极112进行平坦化工艺以于间隙壁124间的空隙126内形成埋入层130，如图4及5所示，此埋入层130为环绕于深沟槽电容元件102的上部104。此平坦化方法使用化学机械研磨工艺、毯覆式回蚀刻、或凹蚀蚀刻工艺以达成。
图5显示一俯视示意图，其绘示于平坦化工艺后的深沟槽电容元件102的上部104图案、间隙壁124、埋入层130、及嵌壁式晶体管112的突出部120。
请参考图5及图6，对间隙壁124、埋入层130、深沟槽电容元件102、及凹槽栅极112进行图案化工艺以形成平行浅沟槽132，图案化工艺可通过光刻及蚀刻工艺而达成。图案化工艺同时可定义出有源区域136且制造隔离层以隔绝晶体管。平行浅沟槽132接邻深沟槽电容元件102及凹槽栅极112的图案化边缘区域。换句话说，此最终得到的间隙壁124及埋入层130分别位于深沟槽电容102及凹槽栅极112侧边的数个区域，因此，则形成图案化的埋入层134a及134b，且图案化的埋入层134a作为埋入插塞或埋入位线插塞。
介电材料层形成于浅沟槽之内，介电材料可为通过高密度等离子体(HDP)工艺沉积而得的氧化物以形成相关技艺所述的浅沟槽隔离结构，最终，对介电材料进行平坦化以显露上部104、间隙壁124、图案化埋入层134、及突出部120。
虽然本发明以优选实施例揭露如上，然而其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作些许的更动与润饰，因此本发明的保护范围应当以后附的权利要求所界定者为准。

Claims (8)

1.一种半导体元件的制造方法，包括：
提供衬底，其具有凹槽栅极与深沟槽电容元件，其中该凹槽栅极的突出部与深沟槽电容元件的上部露出于该衬底；
于该上部及该突出部的侧壁形成间隙壁；
于该间隙壁间的间隙形成由导电材料构成的多个埋入层；
对该衬底、该间隙壁、及该些埋入层进行图案化以形成平行的浅沟槽结构进而定义出有源区；以及
于该浅沟槽结构内形成介电材料层，其中一些埋入层作为埋入插塞。
2.如权利要求1所述的半导体元件的制造方法，其中该间隙壁包括氮化硅。
3.如权利要求1所述的半导体元件的制造方法，其中该导电材料包括多晶硅。
4.如权利要求1所述的半导体元件的制造方法，其中该间隙壁更进一步环绕于该深沟槽电容元件的上部周围。
5.如权利要求1所述的半导体元件的制造方法，其中该介电材料包括氧化物。
6.如权利要求1所述的半导体元件的制造方法，其中对该衬底、该间隙壁、及该埋入层进行图案化包括光刻工艺及蚀刻工艺。
7.如权利要求1所述的半导体元件的制造方法，其中该平行浅沟槽结构形成于接邻该深沟槽电容元件与该凹槽栅极的图案化边缘。
8.如权利要求1所述的半导体元件的制造方法，其中该埋入式插塞包括位线插塞。
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