CN100388465C - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN100388465C
CN100388465C CNB2006100923943A CN200610092394A CN100388465C CN 100388465 C CN100388465 C CN 100388465C CN B2006100923943 A CNB2006100923943 A CN B2006100923943A CN 200610092394 A CN200610092394 A CN 200610092394A CN 100388465 C CN100388465 C CN 100388465C
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李培瑛
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Nanya Technology Corp
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Abstract

本发明提供一种半导体器件的制造方法，其包括提供一其中具有嵌壁式栅极(recessed gates)与深沟槽电容元件的衬底，其暴露出嵌壁式栅极的突出部(protrusions)与深沟槽电容元件的上部(upper portions)，且在上部及突出部的侧壁形成间隙壁，并在间隙壁间的间隙形成一导电材料的埋入层(buried portions)，另对衬底、间隙壁、及埋入层进行图案化以形成平行的浅沟槽结构进而定义有源区，接着，在浅沟槽结构内形成一介电材料层，而其中部分埋入层可作为埋入式位线接触(buried contacts)；以及形成一穿过嵌壁式栅极的字线，其中字线包括重叠覆盖于嵌壁式栅极上的部分，且重叠覆盖部分的宽度小于嵌壁式栅极的宽度。

Description

半导体器件的制造方法
技术领域
本发明涉及一种半导体器件的制造方法，且更特别地，涉及一种半导体器件的接触的制造方法。
背景技术
半导体器件，如存储器元件、用以数据储存的动态随机存取存储器(Dynamic Random Access Memory，DRAM)、或其它种类等，为目前广泛使用，且许多申请案正进行此方面研究。
然而，传统上制造晶体管及位线接触的方法需要至少两道光刻工艺，其导致相关光掩模的高制造成本。此外，在包含电容、有源区、晶体管、及位线接触(bit line contact)等元件的制作工艺中的四道光刻工艺间所造成的严重的对准误差，也影响到工艺成品率。再者，字线的线宽度会占据位线接触的空间，因此，使位线接触与字线间常发生短路，而提升接触工艺的不成品率。特别地，随着动态随机存取存储器尺寸的缩减，这种失败率会益趋严重。据此，目前所需的是提供一种存储器元件的字线及位线接触的制造方法。
发明内容
本发明提供一种半导体器件的制造方法。本发明的一实施例为提供一种形成半导体器件的方法，其包括提供一具有嵌壁式栅极(recessed gate)与深沟槽电容元件于其中的衬底，其暴露出嵌壁式栅极的突出部与深沟槽电容元件的上部，且在上部及突出部的侧壁形成间隙壁，并在间隙壁间的间隙形成一导电材料的埋入层，另对衬底、间隙壁、及埋入层进行图案化以形成平行的浅沟槽结构进而定义有源区，在浅沟槽结构内形成一介电材料层，而其中部分埋入层可作为埋入式位线接触，以及形成一穿过嵌壁式栅极的字线，其中字线包括重叠覆盖于嵌壁式栅极上的部分，且至少重叠覆盖部分的宽度小于嵌壁式栅极的宽度。
附图说明
图1为一俯视示意图，其绘示依据本发明实施例所描述的深沟槽电容元件及嵌壁式沟槽的配置态样。
图2为一剖面示意图，其绘示依据本发明实施例所描述的嵌壁式沟槽的制造方法。
图3为一剖面示意图，其绘示依据本发明实施例所描述的具有突出部的嵌壁式晶体管的制造方法。
图4为一剖面示意图，其绘示依据本发明实施例所描述的以间隙壁形成空隙的制造方法。
图5为一剖面示意图，其绘示依据本发明实施例所描述的形成埋入层的制造方法。
图6为一俯视示意图，其绘示依据本发明实施例所描述的深沟槽电容元件、嵌壁式栅极、间隙壁、及埋入层的配置态样。
图7为一俯视示意图，其绘示依据本发明的实施例所描述浅沟槽、图案化深沟槽电容元件、图案化嵌壁式栅极、图案化间隙壁、及图案化埋入层的配置态样。
图8为一剖面示意图，其绘示依据本发明实施例所描述的字线的制造方法。
图9为一剖面示意图，其绘示依据本发明实施例所描述的字线的制造方法。
图10为一剖面示意图，其绘示依据本发明实施例所描述的字线的制造方法。
图11为一剖面示意图，其绘示依据本发明实施例所描述的位线接触的制造方法。
图12为一剖面示意图，其绘示依据本发明实施例所描述的位线接触的制造方法。
图13为一剖面示意图，其绘示依据本发明实施例所描述的位线接触的制造方法。
图14为一俯视示意图，其绘示依据本发明实施例所描述的浅沟槽、图案化深沟槽电容元件、图案化嵌壁式栅极、图案化间隙壁、及字线的配置态样。
简单符号说明
100～衬底；                    102～深沟槽电容元件；
104～上部；                    106～垫层；
108～介电覆盖层；              110～嵌壁式沟槽；
112～嵌壁式晶体管；            114～沟道区域；
116～栅极介电层；              118～嵌壁式栅极；
120～突出部；                  122～外扩散区域；
124～间隙壁；                  126～空隙；
128～源极/漏极区域；           130～埋入层；
132～平行浅沟槽；              134a、134b～图案化埋入层；
136～有源区域、导电材料层；    138～介电材料层；
140～字线；                    142～栅极覆盖介电层；
144～间隙壁；                  146～第二介电材料层；
148～位线接触孔；              150～平行位线；
W1、W2～宽度。
具体实施方式
本发明将通过以下的优选具体实施例而作更进一步的详细说明，但这些具体实施例仅是作为举例说明，而非用以限定本发明的范畴。
本发明说明书中，诸如“存在于衬底上方(overlying the substrate)”、“在层的上方(above the layer)”、或“位于膜上(on the film)”仅表示相对于衬底层的表面的相对位置关系，并无关乎中间层的存在与否。据此，此种表示不仅指出一或多层直接接触的状态，且指出一或多层的未接触状态。
请参考图1，俯视示意图，其绘示深沟槽电容元件102及嵌壁式晶体管112的配置状态，其中嵌壁式晶体管的位置通过围绕其周围的深沟槽电容元件与位于深沟槽电容元件的上部侧壁的间隙壁而界定。
请参考图2，先形成一衬底100，在衬底100内具有深沟槽电容元件102，且深沟槽电容元件102的上部104位于衬底100的表面之上，垫层106及如氮化硅(SiN)等的介电覆盖层108形成于深沟槽电容元件102上部104的侧壁，介电覆盖层108具有凹陷区(concave area)，此凹陷区大体上位于两邻近深沟槽电容的上部104之间。于是，可对介电覆盖层108、垫层106、及衬底100进行自行对准的蚀刻工艺以形成位于沟槽电容元件102之间的嵌壁式沟槽110。
请参考图3，对邻接嵌壁式沟槽110的衬底100进行掺杂以形成环绕嵌壁式沟槽110的沟道区域114，接着，一栅极介电层116，优选地为包含氧化硅，形成于衬底100上的嵌壁式沟槽110之内，其中，如可使用一热工艺形成栅极介电材料层116，接着在嵌壁式沟槽110中填充一导电材料，如多晶硅、钨、硅化钨，以形成嵌壁式栅极118。并且在形成栅极介电层116的热工艺及/或其它后续工艺所发生的热工艺期间，在衬底100中随之形成外扩散区域122。
对深沟槽电容元件102的上部104、介电覆盖层108、嵌壁式栅极118的上部进行平坦化工艺，接着，以选择性湿式蚀刻工艺进行介电覆盖层108的移除以显露深沟槽电容元件102的上部104及嵌壁式栅极118的突出部120。此平坦化方法包括化学机械研磨工艺、毯覆式回蚀刻(blanket etchingback)、或凹蚀蚀刻(recess etching)工艺。嵌壁式栅极118的突出部120的上表面大体上与深沟槽电容元件102的上部104为同等平面。
请参考图4，间隙壁124形成于上部104及突出部120的侧壁，如此一来，位于其上的间隙壁124间的空隙126则可自行对准。间隙壁124可通过沉积一化学气相沉积氮化硅薄膜以及对该化学气相沉积氮化硅薄膜进行干式回蚀刻工艺而形成。因此，间隙壁124围住上部104及突出部120，且部份衬底100被深沟槽电容元件102、嵌壁式晶体管112、及位于环形空隙126外的间隙壁124覆盖，是以，接着进行离子注入以在嵌壁式沟道区域114的两侧及其环形空隙126下方形成源极/漏极区域128。
请参考图5及图6，一导电材料层，优选包括掺杂的多晶硅或金属，形成于衬底100之上，且填充于间隙壁124间的空隙126。其后，对导电材料层、间隙壁124、深沟槽电容元件102、及嵌壁式栅极118进行平坦化工艺以在间隙壁124间的空隙126内形成埋入层130，如图5及6所示，此埋入层130环绕于深沟槽电容元件102的上部104。此平坦化方法使用化学机械研磨工艺、毯覆式回蚀刻、或凹蚀蚀刻工艺以达成。
图6显示一俯视示意图，其绘示在平坦化工艺后的深沟槽电容元件102的上部104图案、间隙壁124、埋入层130、及嵌壁式晶体管112的突出部120。
请参考图6及图7，对间隙壁124、埋入层130、深沟槽电容元件102、及嵌壁式栅极118进行图案化工艺以形成平行浅沟槽132，图案化工艺可通过光刻及蚀刻工艺而达成。图案化工艺同时可定义出有源区域136且制造隔离层以隔离晶体管。平行浅沟槽132接邻图案化的深沟槽电容元件102及图案化的嵌壁式栅极118的边缘区域。换句话说，图案化工艺后间隙壁124及埋入层130被分为位于深沟槽电容元件102及嵌壁式栅极118侧边的数个区域，因此，则形成图案化的埋入层134a及134b，且图案化的埋入层134a作为埋入接触或埋入位线接触。
介电材料层形成于浅沟槽之内，介电材料可为通过高密度等离子体(HDP)工艺沉积而得的氧化物，以形成相关技艺所述的浅沟槽隔离结构，最终，对介电材料进行平坦化以显露上部104、间隙壁124、图案化埋入层134、及突出部120。
请参考图8，导电材料层136全面性地沉积于衬底100上，导电材料优选地选自纯粹的金属硅化物，如硅化钨(WSi)，或金属，如钨。优选地，导电材料层136的厚度约为800埃至1500埃，导电材料层136以毯覆式沉积而得。接着，介电材料层138沉积于导电材料层136上，其中此介电材料138优选为选自由化学气相沉积工艺形成的氮化硅，优选地，介电材料层138的厚度约为800埃至1500埃，介电材料层138可作为以后续工艺形成的自行对准的上部位线接触孔的蚀刻停止层。
是以，本发明的优势之处在于纯金属与纯金属硅化物直接沉积于嵌壁式栅极118的顶端，无须毯覆式多晶硅层的参与。此外，纯金属或纯金属硅化物用以作为一栅极导体，而由于没有多晶硅层的加入，因此可降低栅极导体的厚度，栅极导体厚度的降低可使后续的SAC位线接触孔蚀刻工艺更为易于施行，且其也可降低位线与字线间的耦合效应。
请参考图9，对介电材料层138与导电材料层136进行图案化工艺，其使用光刻工艺与蚀刻工艺以形成字线140与栅极覆盖介电层142，以在部分深沟槽电容元件102及/或越过部分嵌壁式栅极118之上形成字线140。
其中字线140包括重叠于嵌壁式栅极118的重叠部分，且至少一该些重叠部分具有一宽度W1，此宽度W1比至少一嵌壁式栅极118的宽度W2窄。
在本发明部分实施例中，字线平行地形成，字线的宽度比嵌壁式栅极118的宽度窄。
请参考图14，在本发明实施例中，至少一字线具有数个不同宽度的部分，其中之一和嵌壁式栅极118重叠部分具有一宽度W1，此宽度W1比该嵌壁式栅极118的宽度W2窄。
请参考图10，间隙壁144形成于字线140与栅极覆盖介电层142的侧壁，优选地为氮化物，可以化学气相沉积工艺及反应离子蚀刻(RIE)回蚀刻工艺形成，优选地，氮化物间隙壁144的厚度范围为300至1000埃。
请参考图11，在衬底上方形成一第二介电材料层146，例如，此第二介电材料层146可先沉积一层硼磷硅酸盐玻璃(BPSG)，再进行现有的热回流工艺(reflow process)形成之。
请参考图12，通过光刻工艺及蚀刻工艺对此第二介电材料层146进行图案化以形成位线接触孔148并暴露出埋入位线接触134a。
请参考图13，一第二金属材料层(未显示)形成于第二介电材料层146上，且填充至位线接触孔148以形成上部位线接触，最终地，对金属材料层进行图案化以形成平行位线150。
在另一实施例中(未显示)，可选择性地以传统双金属镶嵌工艺形成位线与上部位线接触(upper bit line contacts)，上部位线接触孔148通过选择性自行对准反应离子蚀刻回蚀刻工艺而形成并显露出埋入位线接触孔134a，且可通过施以简单硼磷硅酸盐玻璃蚀刻穿透工艺而形成位线沟槽。接着，沉积金属导线(化学气相沉积或物理气相沉积钛/氮化钛)与化学气相沉积钨位线并施以化学机械研磨以形成双金属镶嵌位线与上部位线接触。
当与现有技术比较而言，本发明的字线占据了较小的空间，字线结构为位线接触节省了空间，且增大了形成上部位线接触的工艺裕度。此外，字线结构的另一优势在于其可改善字线阻容迟滞(RC delay)的表现，且其也可降低位线与字线间的耦合效应。
虽然本发明以优选实施例揭露如上，然而其并非用以限定本发明，本领域的技术人员在不脱离本发明的精神和范围内，可作些许的更动与润饰，因此本发明的保护范围应当以权利要求所界定者为准。

Claims (8)

1.一种半导体器件的制造方法，包括：
提供衬底，其具有嵌壁式栅极与深沟槽电容元件，其中该嵌壁式栅极的突出部与深沟槽电容元件的上部露出于该衬底；
在该上部及该突出部的侧壁形成间隙壁；
在该间隙壁间的间隙形成由导电材料构成的多个埋入层；
对该衬底、该间隙壁、及该些埋入层进行图案化工艺以形成平行的浅沟槽结构进而定义出有源区，该些埋入层通过该图案化工艺形成为位于该深沟槽电容元件和该嵌壁式栅极侧边的图案化的埋入层；
在该浅沟槽结构内形成介电材料层，其中位于该深沟槽电容元件侧边及位于该嵌壁式栅极侧边的该图案化的埋入层之一作为埋入式位线接触；以及
形成跨过该嵌壁式栅极的字线，其中该字线包括重叠覆盖于该嵌壁式栅极上的部分，且该重叠覆盖部分的宽度小于该嵌壁式栅极的宽度。
2.如权利要求1所述的半导体器件的制造方法，其中该间隙壁包括氮化硅。
3.如权利要求1所述的半导体器件的制造方法，其中该导电材料包括多晶硅。
4.如权利要求1所述的半导体器件的制造方法，其中该间隙更进一步环绕于该深沟槽电容元件的上部周围。
5.如权利要求1所述的半导体器件的制造方法，其中该介电材料包括氧化物。
6.如权利要求1所述的半导体器件的制造方法，其中该图案化工艺包括光刻工艺及蚀刻工艺。
7.如权利要求1所述的半导体器件的制造方法，其中该平行浅沟槽结构形成于邻接图案化的该深沟槽电容元件与图案化的该嵌壁式栅极的边缘。
8.如权利要求1所述的半导体器件的制造方法，其还包括在该埋入式位线接触上形成上部位线接触，且形成位线以与该上部位线接触连接。
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